On 19/10/2023 09:23, Wei-Ning Huang wrote:
Allow userspace to configure cycle count threshold through perf_event_attr config. The last high 12-bit of config value is used to store the cycle count threshold.
We have queued the support already in coreisght next tree, patches posted here [0]
[0] - https://lore.kernel.org/r/20230921033631.1298723-1-anshuman.khandual@arm.com
Suzuki
Signed-off-by: Wei-Ning Huang wnhuang@google.com
drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++- include/linux/coresight-pmu.h | 14 ++++++++------ tools/include/linux/coresight-pmu.h | 14 ++++++++------ 3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 77b0271ce6eb..155441668b4a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -645,6 +645,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; int preset;
- u64 cyc_threadhold;
/* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -667,7 +668,10 @@ static int etm4_parse_event_config(struct coresight_device *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */
config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) &ETM_OPT_CYC_THRESHOLD_MASK;config->ccctlr = cyc_threshold ? cyc_threshold :ETM_CYC_THRESHOLD_DEFAULT;diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 51ac441a37c3..14f48658ff1c 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -29,12 +29,14 @@
- ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
- directly use below macros as config bits.
*/ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_BRANCH_BROADCAST 8 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_BB 3 diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 51ac441a37c3..14f48658ff1c 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -29,12 +29,14 @@
- ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
- directly use below macros as config bits.
*/ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_BRANCH_BROADCAST 8 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_BB 3
Didn't notice that. Thanks for the pointers!
Wei-Ning
On Thu, Oct 19, 2023 at 5:23 PM Suzuki K Poulose suzuki.poulose@arm.com wrote:
On 19/10/2023 09:23, Wei-Ning Huang wrote:
Allow userspace to configure cycle count threshold through perf_event_attr config. The last high 12-bit of config value is used to store the cycle count threshold.
We have queued the support already in coreisght next tree, patches posted here [0]
[0] -
https://lore.kernel.org/r/20230921033631.1298723-1-anshuman.khandual@arm.com
Suzuki
Signed-off-by: Wei-Ning Huang wnhuang@google.com
drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++- include/linux/coresight-pmu.h | 14 ++++++++------ tools/include/linux/coresight-pmu.h | 14 ++++++++------ 3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 77b0271ce6eb..155441668b4a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -645,6 +645,7 @@ static int etm4_parse_event_config(struct
coresight_device *csdev,
struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; int preset;
u64 cyc_threadhold; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config));@@ -667,7 +668,10 @@ static int etm4_parse_event_config(struct
coresight_device *csdev,
if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */
config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
cyc_threshold = ((attr->config >>ETM_OPT_CYC_THRESHOLD_SHIFT) &
ETM_OPT_CYC_THRESHOLD_MASK;config->ccctlr = cyc_threshold ? cyc_threshold :ETM_CYC_THRESHOLD_DEFAULT; } if (attr->config & BIT(ETM_OPT_TS)) { /*diff --git a/include/linux/coresight-pmu.h
b/include/linux/coresight-pmu.h
index 51ac441a37c3..14f48658ff1c 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -29,12 +29,14 @@
- ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
- directly use below macros as config bits.
*/ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_BRANCH_BROADCAST 8 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff
/* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_BB 3 diff --git a/tools/include/linux/coresight-pmu.h
b/tools/include/linux/coresight-pmu.h
index 51ac441a37c3..14f48658ff1c 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -29,12 +29,14 @@
- ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
- directly use below macros as config bits.
*/ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_BRANCH_BROADCAST 8 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff
/* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_BB 3
-
Suzuki K Poulose -
Wei-Ning Huang