On 26 July 2017 at 09:38, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Good day,
I have a few questions about perf and decoder road maps and bug fixes. Here is a list of issues that
I have found out. I like to know if these are known problems and what is the process to get them resolved.
- Snapshot mode (option –S) does not work. Ideally we need to run perf
record with options –a and –S
to trace in snapshot mode on all the cores
That shouldn't be hard to fix - I'll open a card for this.
- Perf record with option –C also does not work. We want, in some cases,
limit the trace to a subset of cores
I've been trying to fix this for a while but have failed completely. To address the issue I don't see any other way than to change the perf ABI between user and kernel space, something that has been rejected by the community in no uncertain terms. I will sit down with Peter Z. at Linux Plumbers in September to see how best to move forward.
This is very high on my list of priorities. It is also the first step in supporting a multi-sink topology.
- Time and cycle information is in the raw trace but perf decoder cannot
decode it
That one is for Mike. It will also require modifications to the perf tools.
Thanks for all your help.
Any time, Mathieu
Regards, Reza
Thanks Mike.
Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 11:52 AM To: Etemadi, Mohammad mohammad.etemadi@intel.com Cc: Mike Leach mike.leach@linaro.org; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 09:38, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Good day,
I have a few questions about perf and decoder road maps and bug fixes. Here is a list of issues that
I have found out. I like to know if these are known problems and what is the process to get them resolved.
- Snapshot mode (option –S) does not work. Ideally we need to run
perf record with options –a and –S
to trace in snapshot mode on all the cores
That shouldn't be hard to fix - I'll open a card for this.
- Perf record with option –C also does not work. We want, in some
cases, limit the trace to a subset of cores
I've been trying to fix this for a while but have failed completely. To address the issue I don't see any other way than to change the perf ABI between user and kernel space, something that has been rejected by the community in no uncertain terms. I will sit down with Peter Z. at Linux Plumbers in September to see how best to move forward.
This is very high on my list of priorities. It is also the first step in supporting a multi-sink topology.
- Time and cycle information is in the raw trace but perf decoder
cannot decode it
That one is for Mike. It will also require modifications to the perf tools.
Thanks for all your help.
Any time, Mathieu
Regards, Reza
On 26 July 2017 at 17:54, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Thanks Mike.
Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 11:52 AM To: Etemadi, Mohammad mohammad.etemadi@intel.com Cc: Mike Leach mike.leach@linaro.org; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 09:38, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Good day,
I have a few questions about perf and decoder road maps and bug fixes. Here is a list of issues that
I have found out. I like to know if these are known problems and what is the process to get them resolved.
- Snapshot mode (option –S) does not work. Ideally we need to run
perf record with options –a and –S
to trace in snapshot mode on all the coresThat shouldn't be hard to fix - I'll open a card for this.
- Perf record with option –C also does not work. We want, in some
cases, limit the trace to a subset of cores
I've been trying to fix this for a while but have failed completely. To address the issue I don't see any other way than to change the perf ABI between user and kernel space, something that has been rejected by the community in no uncertain terms. I will sit down with Peter Z. at Linux Plumbers in September to see how best to move forward.
This is very high on my list of priorities. It is also the first step in supporting a multi-sink topology.
- Time and cycle information is in the raw trace but perf decoder
cannot decode it
That one is for Mike. It will also require modifications to the perf tools.
At present the timestamp and cycle count packets are being decoded and passed to the perf toolchain. It is the perf tools that need to process this information into something meaningful in the perf environment. The specific code withing the cs-etm module in perf is ignoring these packets at present.
Regards
Mike
Thanks for all your help.
Any time, Mathieu
Regards, Reza
On 26 July 2017 at 11:01, Mike Leach mike.leach@linaro.org wrote:
On 26 July 2017 at 17:54, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Thanks Mike.
Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 11:52 AM To: Etemadi, Mohammad mohammad.etemadi@intel.com Cc: Mike Leach mike.leach@linaro.org; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 09:38, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Good day,
I have a few questions about perf and decoder road maps and bug fixes. Here is a list of issues that
I have found out. I like to know if these are known problems and what is the process to get them resolved.
- Snapshot mode (option –S) does not work. Ideally we need to run
perf record with options –a and –S
to trace in snapshot mode on all the coresThat shouldn't be hard to fix - I'll open a card for this.
- Perf record with option –C also does not work. We want, in some
cases, limit the trace to a subset of cores
I've been trying to fix this for a while but have failed completely. To address the issue I don't see any other way than to change the perf ABI between user and kernel space, something that has been rejected by the community in no uncertain terms. I will sit down with Peter Z. at Linux Plumbers in September to see how best to move forward.
This is very high on my list of priorities. It is also the first step in supporting a multi-sink topology.
- Time and cycle information is in the raw trace but perf decoder
cannot decode it
That one is for Mike. It will also require modifications to the perf tools.
At present the timestamp and cycle count packets are being decoded and passed to the perf toolchain. It is the perf tools that need to process this information into something meaningful in the perf environment. The specific code withing the cs-etm module in perf is ignoring these packets at present.
I'll open another card for this. That way we can keep track of what needs to be done.
Regards
Mike
Thanks for all your help.
Any time, Mathieu
Regards, Reza
-- Mike Leach Principal Engineer, ARM Ltd. Blackburn Design Centre. UK
Hello Mathieu, Mike
Are there patches for (1), (2) and (3) ?
Regards, Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 12:12 PM To: Mike Leach mike.leach@linaro.org Cc: Etemadi, Mohammad mohammad.etemadi@intel.com; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 11:01, Mike Leach mike.leach@linaro.org wrote:
On 26 July 2017 at 17:54, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Thanks Mike.
Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 11:52 AM To: Etemadi, Mohammad mohammad.etemadi@intel.com Cc: Mike Leach mike.leach@linaro.org; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 09:38, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Good day,
I have a few questions about perf and decoder road maps and bug fixes. Here is a list of issues that
I have found out. I like to know if these are known problems and what is the process to get them resolved.
- Snapshot mode (option –S) does not work. Ideally we need to run
perf record with options –a and –S
to trace in snapshot mode on all the coresThat shouldn't be hard to fix - I'll open a card for this.
- Perf record with option –C also does not work. We want, in some
cases, limit the trace to a subset of cores
I've been trying to fix this for a while but have failed completely. To address the issue I don't see any other way than to change the perf ABI between user and kernel space, something that has been rejected by the community in no uncertain terms. I will sit down with Peter Z. at Linux Plumbers in September to see how best to move forward.
This is very high on my list of priorities. It is also the first step in supporting a multi-sink topology.
- Time and cycle information is in the raw trace but perf decoder
cannot decode it
That one is for Mike. It will also require modifications to the perf tools.
At present the timestamp and cycle count packets are being decoded and passed to the perf toolchain. It is the perf tools that need to process this information into something meaningful in the perf environment. The specific code withing the cs-etm module in perf is ignoring these packets at present.
I'll open another card for this. That way we can keep track of what needs to be done.
Regards
Mike
Thanks for all your help.
Any time, Mathieu
Regards, Reza
-- Mike Leach Principal Engineer, ARM Ltd. Blackburn Design Centre. UK
On 6 September 2017 at 13:23, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Are there patches for (1), (2) and (3) ?
I am working on 2, there are plans for 1 and nothing on the horizon for 3.
Regards, Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 12:12 PM To: Mike Leach mike.leach@linaro.org Cc: Etemadi, Mohammad mohammad.etemadi@intel.com; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 11:01, Mike Leach mike.leach@linaro.org wrote:
On 26 July 2017 at 17:54, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Thanks Mike.
Reza
-----Original Message----- From: Mathieu Poirier [mailto:mathieu.poirier@linaro.org] Sent: Wednesday, July 26, 2017 11:52 AM To: Etemadi, Mohammad mohammad.etemadi@intel.com Cc: Mike Leach mike.leach@linaro.org; coresight@lists.linaro.org Subject: Re: CoreSight Perf Decoder
On 26 July 2017 at 09:38, Etemadi, Mohammad mohammad.etemadi@intel.com wrote:
Hello Mathieu, Mike
Good day,
I have a few questions about perf and decoder road maps and bug fixes. Here is a list of issues that
I have found out. I like to know if these are known problems and what is the process to get them resolved.
- Snapshot mode (option –S) does not work. Ideally we need to run
perf record with options –a and –S
to trace in snapshot mode on all the coresThat shouldn't be hard to fix - I'll open a card for this.
- Perf record with option –C also does not work. We want, in some
cases, limit the trace to a subset of cores
I've been trying to fix this for a while but have failed completely. To address the issue I don't see any other way than to change the perf ABI between user and kernel space, something that has been rejected by the community in no uncertain terms. I will sit down with Peter Z. at Linux Plumbers in September to see how best to move forward.
This is very high on my list of priorities. It is also the first step in supporting a multi-sink topology.
- Time and cycle information is in the raw trace but perf decoder
cannot decode it
That one is for Mike. It will also require modifications to the perf tools.
At present the timestamp and cycle count packets are being decoded and passed to the perf toolchain. It is the perf tools that need to process this information into something meaningful in the perf environment. The specific code withing the cs-etm module in perf is ignoring these packets at present.
I'll open another card for this. That way we can keep track of what needs to be done.
Regards
Mike
Thanks for all your help.
Any time, Mathieu
Regards, Reza
-- Mike Leach Principal Engineer, ARM Ltd. Blackburn Design Centre. UK
-
Etemadi, Mohammad -
Mathieu Poirier -
Mike Leach