It's in the Juno Technical Reference Manual (TRM), see "Application processor memory map".

STM register base address = 0x20100000.

STM stimulus area = 0x28000000 to 0x28ffffff.

Al

-----Original Message----- From: CoreSight [mailto:coresight-bounces@lists.linaro.org] On Behalf Of Chunyan Zhang Sent: 06 January 2016 08:22 To: Mike Leach; Mathieu Poirier Cc: coresight@lists.linaro.org Subject: Where can I get STM base address

Hi All,

I'd like to add STM entry for Juno based on Mathieu's patch [1]. But where can I find the STM base address and STM stimulus base address and their ranges.

Thanks, Chunyan

[1] https://git.linaro.org/people/mathieu.poirier/coresight.git/commit/202357a34 5ac9269185b60f8a5ee5f7894d7a868 _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Long time no see, thanks for your reply. STM on the Juno works well now. But I'm wondering why the size must be set 4K in DT rather than 64K, I noticed Juno TRM shows that STM Debug APB takes 64K.

The APB interface is actually 4K. The DT should define them as 4K and the OS can map 4K pages to them and make the pages consecutive if it wants. They are 64K aligned in the physical address space because some OSes (or hypervisors etc.) want to use a minimum page size of 64K while still having flexibility over the mapping for individual peripherals, so this means not having multiple peripherals within one physical 64K region.

It's not just CoreSight, even the UARTs and other tiny peripherals are on 64K boundaries in Juno. I would expect quite a few SoCs are like that. The TRM is just saving space by not showing a 60K hole between them all.

Al

Thanks, Chunyan

On Wed, Jan 6, 2016 at 6:03 PM, Al Grant Al.Grant@arm.com wrote:

...

It's in the Juno Technical Reference Manual (TRM), see "Application

processor memory map".

...

STM register base address = 0x20100000.

STM stimulus area = 0x28000000 to 0x28ffffff.

Al

...

-----Original Message----- From: CoreSight [mailto:coresight-bounces@lists.linaro.org] On Behalf Of Chunyan Zhang Sent: 06 January 2016 08:22 To: Mike Leach; Mathieu Poirier Cc: coresight@lists.linaro.org Subject: Where can I get STM base address

Hi All,

I'd like to add STM entry for Juno based on Mathieu's patch [1]. But where can I find the STM base address and STM stimulus base address and their ranges.

Thanks, Chunyan

[1] https://git.linaro.org/people/mathieu.poirier/coresight.git/commit/20 2357a34 5ac9269185b60f8a5ee5f7894d7a868 _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight

IMPORTANT NOTICE: The contents of this email and any attachments are

confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.