Good day Jan,
Please CC the coresight mailing list when you have questions such as this one. There is a lot of knowledgeable people on it that are also be able to help you.
On Fri, 18 Oct 2019 at 07:42, Jan Hoogerbrugge jan.hoogerbrugge@nxp.com wrote:
Hi Mathieu,
I am trying to understand Coresight support in the Linux kernel. I am using a Xilinx Zynq Ultrascale+ system. I configured the kernel with coresight support enabled. When the system is running I see the /sys/bus/coresight directory but the devices directory in it stays empty. Also, I do not see messages about coresight reported when booting:
root@xilinx-zcu102-2017_4:~# ls -R /sys/bus/coresight /sys/bus/coresight: devices drivers_autoprobe uevent drivers drivers_probe
/sys/bus/coresight/devices:
/sys/bus/coresight/drivers: root@xilinx-zcu102-2017_4:~# dmesg | grep -i coresight root@xilinx-zcu102-2017_4:~#
Any idea what I am doing wrong?
My guess it that coresight devices for that processor have not been specified in the device tree. If I'm not mistaking some people (also on this list) from Xiling have been experiencing with coresight on that specific platform - hopefully they will chime in.
I want to use Coresight to obtain some TPUI/ETM traces so that I can experiment with them.
Note that a driver for the TPIU IP block is currently not available. I never had time to write a driver and nobody has ever submitted one.
I hope that I can dump some traces to file so that I can process them later. Do you know about publicly accessible archives with traces on the Internet? This might be then an alternative for me.
I do not know of any.
Thanks, Mathieu
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
I hope that I can dump some traces to file so that I can process them later. Do you know about publicly accessible archives with traces on the Internet? This might be then an alternative for me.
There's a good selection of captured traces in the test suite for the ETM decoder, together with the binaries needed to decode them:
https://github.com/Linaro/OpenCSD
Al IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
On Fri, 18 Oct 2019 at 09:55, Al Grant Al.Grant@arm.com wrote:
I hope that I can dump some traces to file so that I can process them later. Do you know about publicly accessible archives with traces on the Internet? This might be then an alternative for me.
There's a good selection of captured traces in the test suite for the ETM decoder, together with the binaries needed to decode them:
Right, but those are not related to the integration with the perf framework.
Al IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
hi Janhave you checked your device tree file? this file is used by the kernel during boot time to know which device exists and load its respective driver. list of coresight IPs as well as their relative address map is available in "Zynq UltraScale+ Device TRM" UG1085 (v2.1) August 21, 2019 page 1163B.R.Zied Guermazi On Friday, October 18, 2019, 05:44:30 PM GMT+2, Mathieu Poirier mathieu.poirier@linaro.org wrote:
Good day Jan,
Please CC the coresight mailing list when you have questions such as this one. There is a lot of knowledgeable people on it that are also be able to help you.
On Fri, 18 Oct 2019 at 07:42, Jan Hoogerbrugge jan.hoogerbrugge@nxp.com wrote:
Hi Mathieu,
I am trying to understand Coresight support in the Linux kernel. I am using a Xilinx Zynq Ultrascale+ system. I configured the kernel with coresight support enabled. When the system is running I see the /sys/bus/coresight directory but the devices directory in it stays empty. Also, I do not see messages about coresight reported when booting:
root@xilinx-zcu102-2017_4:~# ls -R /sys/bus/coresight /sys/bus/coresight: devices drivers_autoprobe uevent drivers drivers_probe
/sys/bus/coresight/devices:
/sys/bus/coresight/drivers: root@xilinx-zcu102-2017_4:~# dmesg | grep -i coresight root@xilinx-zcu102-2017_4:~#
Any idea what I am doing wrong?
My guess it that coresight devices for that processor have not been specified in the device tree. If I'm not mistaking some people (also on this list) from Xiling have been experiencing with coresight on that specific platform - hopefully they will chime in.
I want to use Coresight to obtain some TPUI/ETM traces so that I can experiment with them.
Note that a driver for the TPIU IP block is currently not available. I never had time to write a driver and nobody has ever submitted one.
I hope that I can dump some traces to file so that I can process them later. Do you know about publicly accessible archives with traces on the Internet? This might be then an alternative for me.
I do not know of any.
Thanks, Mathieu
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
_______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
Hi all,
Indeed the information for Coresight is missing in the device tree file.
I will first see whether trace files from the OpenCSD can help me. Later I will try to add the missing information to the device tree.
Thanks for the feedback!
Regards, Jan -- Jan Hoogerbrugge Principal Security Architect Competence Center Crypto & Security NXP Semiconductors High Tech Campus 46, 5656AE Eindhoven, The Netherlands Phone: +31 6 57728704
From: zied guermazi guermazi_zied@yahoo.com Sent: Friday, October 18, 2019 6:27 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com; Mathieu Poirier mathieu.poirier@linaro.org Cc: Coresight ML coresight@lists.linaro.org Subject: [EXT] Re: Coresight support in Linux kernel
Caution: EXT Email hi Jan have you checked your device tree file? this file is used by the kernel during boot time to know which device exists and load its respective driver. list of coresight IPs as well as their relative address map is available in "Zynq UltraScale+ Device TRM" UG1085 (v2.1) August 21, 2019 page 1163 B.R. Zied Guermazi
On Friday, October 18, 2019, 05:44:30 PM GMT+2, Mathieu Poirier <mathieu.poirier@linaro.orgmailto:mathieu.poirier@linaro.org> wrote:
Good day Jan,
Please CC the coresight mailing list when you have questions such as this one. There is a lot of knowledgeable people on it that are also be able to help you.
On Fri, 18 Oct 2019 at 07:42, Jan Hoogerbrugge <jan.hoogerbrugge@nxp.commailto:jan.hoogerbrugge@nxp.com> wrote:
Hi Mathieu,
I am trying to understand Coresight support in the Linux kernel. I am using a Xilinx Zynq Ultrascale+ system. I configured the kernel with coresight support enabled. When the system is running I see the /sys/bus/coresight directory but the devices directory in it stays empty. Also, I do not see messages about coresight reported when booting:
root@xilinx-zcu102-2017_4mailto:root@xilinx-zcu102-2017_4:~# ls -R /sys/bus/coresight /sys/bus/coresight: devices drivers_autoprobe uevent drivers drivers_probe
/sys/bus/coresight/devices:
/sys/bus/coresight/drivers: root@xilinx-zcu102-2017_4mailto:root@xilinx-zcu102-2017_4:~# dmesg | grep -i coresight root@xilinx-zcu102-2017_4mailto:root@xilinx-zcu102-2017_4:~#
Any idea what I am doing wrong?
My guess it that coresight devices for that processor have not been specified in the device tree. If I'm not mistaking some people (also on this list) from Xiling have been experiencing with coresight on that specific platform - hopefully they will chime in.
I want to use Coresight to obtain some TPUI/ETM traces so that I can experiment with them.
Note that a driver for the TPIU IP block is currently not available. I never had time to write a driver and nobody has ever submitted one.
I hope that I can dump some traces to file so that I can process them later. Do you know about publicly accessible archives with traces on the Internet? This might be then an alternative for me.
I do not know of any.
Thanks, Mathieu
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
_______________________________________________ CoreSight mailing list CoreSight@lists.linaro.orgmailto:CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresighthttps://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.linaro.org%2Fmailman%2Flistinfo%2Fcoresight&data=02%7C01%7Cjan.hoogerbrugge%40nxp.com%7C7bf457591e354c104ff008d753e8091c%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637070128357375014&sdata=0HNEjBItj7pXJhfWqO4hCA6G01IswF5GHTvaM8Zdn5A%3D&reserved=0
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first: 1. I'm successfully using this configuration on Xilinx ZCU104 board running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
6. I based the DTS file on what I've found here: https://gitlab.fel.cvut.cz/barysmax/diploma-sw-hw-xilinx/ The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
From: Wojciech Zmuda wzmuda@n7space.com
Inspired by work of Maxim Baryshnikov barysmax@fel.cvut.cz found here: https://gitlab.fel.cvut.cz/barysmax/diploma-sw-hw-xilinx/blob/master/0001-dt... --- .../boot/dts/xilinx/zynqmp-coresight.dtsi | 300 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 301 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi new file mode 100644 index 000000000000..e2e07dd6940f --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi @@ -0,0 +1,300 @@ +/ { + misc_clk: misc_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + etm0@fec40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfec40000 0 0x1000>; + cpu = <&cpu0>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel1_in_port0>; + }; + }; + }; + }; + + etm1@fed40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfed40000 0 0x1000>; + cpu = <&cpu1>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel1_in_port1>; + }; + }; + }; + }; + + etm2@fee40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfee40000 0 0x1000>; + cpu = <&cpu2>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel1_in_port2>; + }; + }; + }; + }; + + etm3@fef40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xfef40000 0 0x1000>; + cpu = <&cpu3>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&funnel1_in_port3>; + }; + }; + }; + }; + + debug0@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfec10000 0 0x1000>; + cpu = <&cpu0>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + }; + + debug1@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfed10000 0 0x1000>; + cpu = <&cpu1>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + }; + + debug2@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfee10000 0 0x1000>; + cpu = <&cpu2>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + }; + + debug3@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfef10000 0 0x1000>; + cpu = <&cpu3>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + }; + + funnel1@fe920000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xfe920000 0 0x1000>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + in-ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + port@0 { + reg = <0x0>; + funnel1_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + port@1 { + reg = <0x1>; + funnel1_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; + port@2 { + reg = <0x2>; + funnel1_in_port2: endpoint { + slave-mode; + remote-endpoint = <&etm2_out_port>; + }; + }; + port@3 { + reg = <0x3>; + funnel1_in_port3: endpoint { + slave-mode; + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + out-ports { + port { + funnel1_out_port0: endpoint { + remote-endpoint = <&etf1_in_port>; + }; + }; + }; + }; + + funnel2@fe930000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xfe930000 0 0x1000>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + in-ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + port@0 { + reg = <0x0>; + funnel2_in_port0: endpoint { + slave-mode; + remote-endpoint = <&stm_out_port>; + }; + }; + port@1 { + reg = <0x1>; + funnel2_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etf1_out_port>; + }; + }; + // Funnel2 has another input port connected to + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs. + }; + out-ports { + port { + funnel2_out_port0: endpoint { + remote-endpoint = <&etf2_in_port>; + }; + }; + }; + }; + + etf1@fe940000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xfe940000 0 0x1000>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + in-ports { + port { + etf1_in_port: endpoint { + slave-mode; + remote-endpoint = <&funnel1_out_port0>; + }; + }; + }; + out-ports { + port { + etf1_out_port: endpoint { + remote-endpoint = <&funnel2_in_port1>; + }; + }; + }; + }; + + etf2@fe950000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xfe950000 0 0x1000>; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + in-ports { + port { + etf2_in_port: endpoint { + slave-mode; + remote-endpoint = <&funnel2_out_port0>; + }; + }; + }; + out-ports { + port { + etf2_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-replicator"; + in-ports { + port { + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf2_out_port>; + }; + }; + }; + out-ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + port@0 { + reg = <0x0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + port@1 { + reg = <0x1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + }; + + etr@fe970000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xfe970000 0 0x1000>; + + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + in-ports { + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + tpiu@fe980000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xfe980000 0 0x1000>; + + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + stm@fe9c0000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0xfe9c0000 0 0x1000>, + <0 0xf8000000 0 0x1000000>; + reg-names = "stm-base", "stm-stimulus-base"; + clocks = <&misc_clk>; + clock-names = "apb_pclk"; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&funnel2_in_port0>; + }; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index d4ad19a38c93..c345b9aa7be6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -10,6 +10,7 @@ /dts-v1/;
#include "zynqmp.dtsi" +#include "zynqmp-coresight.dtsi" #include "zynqmp-clk.dtsi" #include <dt-bindings/gpio/gpio.h>
Hi Wojciech,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why?
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# cat /sys/bus/coresight/devices/fec40000.etm0/enable_source 0 root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > /sys/bus/coresight/devices/fec40000.etm0/enable_source [ 9786.121394] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices#
It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
________________________________ From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 12:20 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com; Wojciech Żmuda wzmuda@n7space.com Subject: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first: 1. I'm successfully using this configuration on Xilinx ZCU104 board running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
6. I based the DTS file on what I've found here: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fel... The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
-- 2.20.1
Hi Jan,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
Happy to hear that!
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why? It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
It is because you need to enable sink first. I've just tried it:
root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 0 root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source -bash: echo: write error: Invalid argument root@zynq:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 1
I recall having similar problem couple of months back. Please take a look at this discussion, where Mathieu, Leo, Mike and Al helped me greatly with Zynq. Perhaps you find some answers there to your next questions: https://lists.linaro.org/pipermail/coresight/2019-March/002342.html
Regards, Wojciech
________________________________________ From: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Sent: Wednesday, October 23, 2019 16:23 To: Wojciech Żmuda Cc: coresight@lists.linaro.org; mathieu.poirier@linaro.org; guermazi_zied@yahoo.com; al.grant@arm.com; Michal Mosdorf; Michał Kurowski Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Hi Wojciech,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why?
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# cat /sys/bus/coresight/devices/fec40000.etm0/enable_source 0 root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > /sys/bus/coresight/devices/fec40000.etm0/enable_source [ 9786.121394] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices#
It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
________________________________ From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 12:20 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com; Wojciech Żmuda wzmuda@n7space.com Subject: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first: 1. I'm successfully using this configuration on Xilinx ZCU104 board running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
6. I based the DTS file on what I've found here: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fel... The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
-- 2.20.1
Hi Wojciech,
Unfortunately it still does not work:
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source [ 3943.161518] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source [ 3973.385463] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# uname -a Linux xilinx-zcu102-2017_4 4.9.0-xilinx-v2017.4 #2 SMP Wed Oct 23 13:07:05 CEST 2019 aarch64 GNU/Linux
Notice that you get 'Invalid argument returned' on the first write to etm/enable_source while I get 'No such device'. Could it be that I need a more recent kernel (with a more recent coresight.c)? As you can see above, I use 4.9.0.
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
________________________________ From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 5:13 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
Hi Jan,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
Happy to hear that!
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why? It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
It is because you need to enable sink first. I've just tried it:
root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 0 root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source -bash: echo: write error: Invalid argument root@zynq:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 1
I recall having similar problem couple of months back. Please take a look at this discussion, where Mathieu, Leo, Mike and Al helped me greatly with Zynq. Perhaps you find some answers there to your next questions: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.lina...
Regards, Wojciech
________________________________________ From: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Sent: Wednesday, October 23, 2019 16:23 To: Wojciech Żmuda Cc: coresight@lists.linaro.org; mathieu.poirier@linaro.org; guermazi_zied@yahoo.com; al.grant@arm.com; Michal Mosdorf; Michał Kurowski Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Hi Wojciech,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why?
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# cat /sys/bus/coresight/devices/fec40000.etm0/enable_source 0 root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > /sys/bus/coresight/devices/fec40000.etm0/enable_source [ 9786.121394] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices#
It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
________________________________ From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 12:20 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com; Wojciech Żmuda wzmuda@n7space.com Subject: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first: 1. I'm successfully using this configuration on Xilinx ZCU104 board running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
6. I based the DTS file on what I've found here: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fel... The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
-- 2.20.1
Hi Jan,
Notice that you get 'Invalid argument returned' on the first write to etm/enable_source while I get 'No such device'. Could it be that I need a more recent kernel (with a more recent coresight.c)? As you can see above, I use 4.9.0.
I think the kernel version may be the issue here. However, this would need a Linaro team member confirmation, as I'm not proficient with changes introduced to subsequent kernel releases. Personally, I have never used anything lower than 5.0-rcX for my Coresight experiments.
Anyway, the development in the Coresight field is very dynamic, so I would suggest you to update to the most recent kernel version. That way you would get all the benefits from the most up to date Coresight drivers and Perf subsystem changes. I believe it would make your work easier, as some problems you may encounter with older releases may already be patched in the new ones.
Regards, Wojciech
________________________________________ From: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Sent: Thursday, October 24, 2019 12:39 To: Wojciech Żmuda Cc: coresight@lists.linaro.org; mathieu.poirier@linaro.org; guermazi_zied@yahoo.com; al.grant@arm.com; Michal Mosdorf; Michał Kurowski Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Hi Wojciech,
Unfortunately it still does not work:
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source [ 3943.161518] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source [ 3973.385463] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# uname -a Linux xilinx-zcu102-2017_4 4.9.0-xilinx-v2017.4 #2 SMP Wed Oct 23 13:07:05 CEST 2019 aarch64 GNU/Linux
Notice that you get 'Invalid argument returned' on the first write to etm/enable_source while I get 'No such device'. Could it be that I need a more recent kernel (with a more recent coresight.c)? As you can see above, I use 4.9.0.
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
________________________________ From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 5:13 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
Hi Jan,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
Happy to hear that!
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why? It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
It is because you need to enable sink first. I've just tried it:
root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 0 root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source -bash: echo: write error: Invalid argument root@zynq:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 1
I recall having similar problem couple of months back. Please take a look at this discussion, where Mathieu, Leo, Mike and Al helped me greatly with Zynq. Perhaps you find some answers there to your next questions: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.lina...
Regards, Wojciech
________________________________________ From: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Sent: Wednesday, October 23, 2019 16:23 To: Wojciech Żmuda Cc: coresight@lists.linaro.org; mathieu.poirier@linaro.org; guermazi_zied@yahoo.com; al.grant@arm.com; Michal Mosdorf; Michał Kurowski Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Hi Wojciech,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why?
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# cat /sys/bus/coresight/devices/fec40000.etm0/enable_source 0 root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > /sys/bus/coresight/devices/fec40000.etm0/enable_source [ 9786.121394] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices#
It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
________________________________ From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 12:20 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com; Wojciech Żmuda wzmuda@n7space.com Subject: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first: 1. I'm successfully using this configuration on Xilinx ZCU104 board running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
6. I based the DTS file on what I've found here: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fel... The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
-- 2.20.1
On Thu, 24 Oct 2019 at 05:01, Wojciech Żmuda wzmuda@n7space.com wrote:
Hi Jan,
Notice that you get 'Invalid argument returned' on the first write to etm/enable_source while I get 'No such device'. Could it be that I need a more recent kernel (with a more recent coresight.c)? As you can see above, I use 4.9.0.
I think the kernel version may be the issue here. However, this would need a Linaro team member confirmation, as I'm not proficient with changes introduced to subsequent kernel releases. Personally, I have never used anything lower than 5.0-rcX for my Coresight experiments.
Anyway, the development in the Coresight field is very dynamic, so I would suggest you to update to the most recent kernel version. That way you would get all the benefits from the most up to date Coresight drivers and Perf subsystem changes. I believe it would make your work easier, as some problems you may encounter with older releases may already be patched in the new ones.
As Wojciech mentioned 4.4.9 is more than 3 years old and I certainly wouldn't remember the feature set we supported back then. Upgrading to the latest kernel will help us understand what the problem is.
Regards, Wojciech
From: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Sent: Thursday, October 24, 2019 12:39 To: Wojciech Żmuda Cc: coresight@lists.linaro.org; mathieu.poirier@linaro.org; guermazi_zied@yahoo.com; al.grant@arm.com; Michal Mosdorf; Michał Kurowski Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Hi Wojciech,
Unfortunately it still does not work:
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source [ 3943.161518] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source [ 3973.385463] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# uname -a Linux xilinx-zcu102-2017_4 4.9.0-xilinx-v2017.4 #2 SMP Wed Oct 23 13:07:05 CEST 2019 aarch64 GNU/Linux
Notice that you get 'Invalid argument returned' on the first write to etm/enable_source while I get 'No such device'. Could it be that I need a more recent kernel (with a more recent coresight.c)? As you can see above, I use 4.9.0.
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 5:13 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
Hi Jan,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
Happy to hear that!
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why? It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
It is because you need to enable sink first. I've just tried it:
root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 0 root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source -bash: echo: write error: Invalid argument root@zynq:/sys/bus/coresight/devices# echo 1 > fe970000.etr/enable_sink root@zynq:/sys/bus/coresight/devices# echo 1 > fec40000.etm0/enable_source root@zynq:/sys/bus/coresight/devices# cat fec40000.etm0/enable_source 1
I recall having similar problem couple of months back. Please take a look at this discussion, where Mathieu, Leo, Mike and Al helped me greatly with Zynq. Perhaps you find some answers there to your next questions: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.lina...
Regards, Wojciech
From: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Sent: Wednesday, October 23, 2019 16:23 To: Wojciech Żmuda Cc: coresight@lists.linaro.org; mathieu.poirier@linaro.org; guermazi_zied@yahoo.com; al.grant@arm.com; Michal Mosdorf; Michał Kurowski Subject: Re: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Hi Wojciech,
Thanks for the patch. The patch works. The devices are recognized by the kernel.
@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why?
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# cat /sys/bus/coresight/devices/fec40000.etm0/enable_source 0 root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > /sys/bus/coresight/devices/fec40000.etm0/enable_source [ 9786.121394] building path(s) failed -sh: echo: write error: No such device root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices#
It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?
Regards,
Jan
--
Jan Hoogerbrugge
Principal Security Architect
Competence Center Crypto & Security
NXP Semiconductors
High Tech Campus 46, 5656AE Eindhoven, The Netherlands
Phone: +31 6 57728704
From: Wojciech Żmuda wzmuda@n7space.com Sent: Wednesday, October 23, 2019 12:20 PM To: Jan Hoogerbrugge jan.hoogerbrugge@nxp.com Cc: coresight@lists.linaro.org coresight@lists.linaro.org; mathieu.poirier@linaro.org mathieu.poirier@linaro.org; guermazi_zied@yahoo.com guermazi_zied@yahoo.com; al.grant@arm.com al.grant@arm.com; Michal Mosdorf mmosdorf@n7space.com; Michał Kurowski mkurowski@n7space.com; Wojciech Żmuda wzmuda@n7space.com Subject: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
Caution: EXT Email
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first:
- I'm successfully using this configuration on Xilinx ZCU104 board
running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
- I based the DTS file on what I've found here:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fel... The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
-- 2.20.1
Good morning Wojciech,
On Wed, 23 Oct 2019 at 04:21, Wojciech Żmuda wzmuda@n7space.com wrote:
From: Wojciech Zmuda wzmuda@n7space.com
Hello Jan, hello all,
Sorry for not keeping up with the list recently. I had plans to deliver working Coresight support for Zynq Ultrascale+, but it looks like I won't be able to dedicate a proper time slice for that in the nearest future.
I guess, the best solution for everybody would be to share what I've got so far.
A few notes first:
- I'm successfully using this configuration on Xilinx ZCU104 board
running mainline Linux 5.1-rc1 with some Linaro patches applied. Since I can see those patches have already made it into mainline, I think this DTS should work, with a minor tweaks, the on current mainline. 2. Since I forked Linux, bindings for funnel and replicator has changed. The ones used here are obsolete now. I think they should still work, but warnings will be issued in dmesg. New bindings are described in Documentation/devicetree/bindings/arm/coresight.txt in Linux tree. 3. I'm successfully tracing with all four ETMs to both ETFs and ETR. This suggests ETM, ETF and ETR bindings as well as replicators and funnels bindings should be correct. 4. However, I haven't tested the TPIU port or STM. While the description seems accurate with the Zynq US+ TRM, I cannot confirm it is complete. 5. Platform specific: for timestamp support, the timestamp generator must be enabled. It can be done from uBoot with the following command:
ZynqMP> mw fe900000 1
Not doing this will cause Perf to report 'Timestamp: 0x0' when the 'timestamp' flag is added to cs_etm event. This is described in details somewhere on this list.
- I based the DTS file on what I've found here:
https://gitlab.fel.cvut.cz/barysmax/diploma-sw-hw-xilinx/ The DTS patch stored in this repo didn't work out of the box, but gave me a starting point.
Many thanks for the Linaro team, who offered me a great help on enabling and testing Coresight on this SoC. I'll try to monitor Zynq-related threads on the list and to offer my help.
Wojciech Zmuda (1): zynqmp: Add CoreSight support to DTS
.../boot/dts/xilinx/zynqmp-coresight.dtsi | 312 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + 2 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
First and foremost thank you for the work. Unfortunately can't take this set because I do not maintain the Xilinx device tree files. I suggest to use the "get_maintainer.pl" script to know the complete set of addresses to send your work to. Include me in your respin and I will make sure to review your work. From there it will be up to Michal Simek to pick up your patches since he is the Xiling SoC maintainer.
Regards, Mathieu
-- 2.20.1
-
Al Grant -
Jan Hoogerbrugge -
Mathieu Poirier -
Wojciech Żmuda -
zied guermazi