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2902 discussions

Re: [PATCH v6 05/10] accel/rocket: Add a new driver for Rockchip's NPU

by Robin Murphy

[ Since Daniel made me look... ] On 2025-06-04 8:57 am, Tomeu Vizoso wrote: [...] > diff --git a/drivers/accel/rocket/Kconfig b/drivers/accel/rocket/Kconfig > new file mode 100644 > index 0000000000000000000000000000000000000000..9a59c6c61bf4d6460d8008b16331f001c97de67d > --- /dev/null > +++ b/drivers/accel/rocket/Kconfig > @@ -0,0 +1,25 @@ > +# SPDX-License-Identifier: GPL-2.0-only > + > +config DRM_ACCEL_ROCKET > + tristate "Rocket (support for Rockchip NPUs)" > + depends on DRM > + depends on ARM64 || COMPILE_TEST Best make that "(ARCH_ROCKCHIP && ARM64) || COMPILE_TEST" now before someone else inevitably does. Or perhaps just a pre-emptive "ARCH_ROCKCHIP || COMPILE_TEST" if this is the same NPU that's in RV1126 etc. > + depends on MMU > + select DRM_SCHED > + select IOMMU_SUPPORT Selecting user-visible symbols is often considered bad form, but this one isn't even functional - all you're doing here is forcing the top-level availability of all the IOMMU driver/API options. If you really want to nanny the user and dissuade them from building a config which is unlikely to be useful in practice, then at best maybe "depends on ROCKCHIP_IOMMU || COMPILE_TEST", but TBH I wouldn't even bother with that. Even if you want to rely on using the IOMMU client API unconditionally, it'll fail decisively enough at runtime if there's no IOMMU present (or the API is stubbed out entirely). > + select IOMMU_IO_PGTABLE_LPAE And I have no idea what this might think it's here for :/ Thanks, Robin. > + select DRM_GEM_SHMEM_HELPER > + help > + Choose this option if you have a Rockchip SoC that contains a > + compatible Neural Processing Unit (NPU), such as the RK3588. Called by > + Rockchip either RKNN or RKNPU, it accelerates inference of neural > + networks. > + > + The interface exposed to userspace is described in > + include/uapi/drm/rocket_accel.h and is used by the Rocket userspace > + driver in Mesa3D. > + > + If unsure, say N. > + > + To compile this driver as a module, choose M here: the > + module will be called rocket.

3 weeks

Re: [RFC PATCH 17/30] iommufd/device: Add TSM Bind/Unbind for TIO support

by Jason Gunthorpe

On Wed, Jun 04, 2025 at 02:10:43PM +0530, Aneesh Kumar K.V wrote: > Jason Gunthorpe <jgg(a)nvidia.com> writes: > > > On Tue, Jun 03, 2025 at 02:20:51PM +0800, Xu Yilun wrote: > >> > Wouldn’t it be simpler to skip the reference count increment altogether > >> > and just call tsm_unbind in the virtual device’s destroy callback? > >> > (iommufd_vdevice_destroy()) > >> > >> The vdevice refcount is the main concern, there is also an IOMMU_DESTROY > >> ioctl. User could just free the vdevice instance if no refcount, while VFIO > >> is still in bound state. That seems not the correct free order. > > > > Freeing the vdevice should automatically unbind it.. > > > > One challenge I ran into during implementation was the dependency of > vfio on iommufd_device. When vfio needs to perform a tsm_unbind, > it only has access to an iommufd_device. VFIO should never do that except by destroying the idevice.. > However, TSM operations like binding and unbinding are handled at the > iommufd_vdevice level. The issue? There’s no direct link from > iommufd_device back to iommufd_vdevice. Yes. > To address this, I modified the following structures: > > modified drivers/iommu/iommufd/iommufd_private.h > @@ -428,6 +428,7 @@ struct iommufd_device { > /* protect iopf_enabled counter */ > struct mutex iopf_lock; > unsigned int iopf_enabled; > + struct iommufd_vdevice *vdev; > }; Locking will be painful: > Updating vdevice->idev requires holding vdev->mutex (vdev_lock). > Updating device->vdev requires idev->igroup->lock (idev_lock). I wonder if that can work on the destory paths.. You also have to prevent more than one vdevice from being created for an idevice, I don't think we do that today. > tsm_unbind in vdevice_destroy: > > vdevice_destroy() ends up calling tsm_unbind() while holding only the > vdev_lock. At first glance, this seems unsafe. But in practice, it's > fine because the corresponding iommufd_device has already been destroyed > when the VFIO device file descriptor was closed—triggering > vfio_df_iommufd_unbind(). This needs some kind of fixing the idevice should destroy the vdevices during idevice destruction so we don't get this out of order where the idevice is destroyed before the vdevice. This should be a separate patch as it is an immediate bug fix.. Jason

3 weeks

Re: [PATCH v6 03/10] arm64: dts: rockchip: Enable the NPU on quartzpro64

by Heiko Stübner

Am Mittwoch, 4. Juni 2025, 09:57:16 Mitteleuropäische Sommerzeit schrieb Tomeu Vizoso: > Enable the nodes added in a previous commit to the rk3588s device tree. shouldn't the quartzpro64 also need a vdd_npu regulator, like the rock-5b support at the end of the series? If not, please mention that in the commit message. Also, it'd make sense to collect all dts patches in one location (probably at the bottom of the series= Heiko > v2: > - Split nodes (Sebastian Reichel) > - Sort nodes (Sebastian Reichel) > - Add board regulators (Sebastian Reichel) > > Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net> > --- > .../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 30 ++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts > index 78aaa6635b5d20a650aba8d8c2d0d4f498ff0d33..2e45b213c25b99571dd71ce90bc7970418f60276 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts > @@ -415,6 +415,36 @@ &pcie3x4 { > status = "okay"; > }; > > +&rknn_core_top { > + npu-supply = <&vdd_npu_s0>; > + sram-supply = <&vdd_npu_mem_s0>; > + status = "okay"; > +}; > + > +&rknn_core_1 { > + npu-supply = <&vdd_npu_s0>; > + sram-supply = <&vdd_npu_mem_s0>; > + status = "okay"; > +}; > + > +&rknn_core_2 { > + npu-supply = <&vdd_npu_s0>; > + sram-supply = <&vdd_npu_mem_s0>; > + status = "okay"; > +}; > + > +&rknn_mmu_top { > + status = "okay"; > +}; > + > +&rknn_mmu_1 { > + status = "okay"; > +}; > + > +&rknn_mmu_2 { > + status = "okay"; > +}; > + > &saradc { > vref-supply = <&vcc_1v8_s0>; > status = "okay"; > >

3 weeks, 1 day

Re: [PATCH v6 01/10] dt-bindings: npu: rockchip,rknn: Add bindings

by Heiko Stübner

Am Mittwoch, 4. Juni 2025, 09:57:14 Mitteleuropäische Sommerzeit schrieb Tomeu Vizoso: > Add the bindings for the Neural Processing Unit IP from Rockchip. > > v2: > - Adapt to new node structure (one node per core, each with its own > IOMMU) > - Several misc. fixes from Sebastian Reichel > > v3: > - Split register block in its constituent subblocks, and only require > the ones that the kernel would ever use (Nicolas Frattaroli) > - Group supplies (Rob Herring) > - Explain the way in which the top core is special (Rob Herring) > > v4: > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > - Remove unneeded items: (Krzysztof Kozlowski) > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > - Add reg-names to list of required properties (Krzysztof Kozlowski) > - Fix example (Krzysztof Kozlowski) > > v5: > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > - Streamline compatible property (Krzysztof Kozlowski) > > v6: > - Remove mention to NVDLA, as the hardware is only incidentally related > (Kever Yang) > - Mark pclk and npu clocks as required by all clocks (Rob Herring) > > Signed-off-by: Sebastian Reichel <sebastian.reichel(a)collabora.com> > Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > --- > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 144 +++++++++++++++++++++ > 1 file changed, 144 insertions(+) > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..9a5e9e213912d0997da2f6ae26189adf044dcc7b > --- /dev/null > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > @@ -0,0 +1,144 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Neural Processing Unit IP from Rockchip > + > +maintainers: > + - Tomeu Vizoso <tomeu(a)tomeuvizoso.net> > + > +description: > + Rockchip IP for accelerating inference of neural networks. > + > + There is to be a node per each core in the NPU. In Rockchip's design there > + will be one core that is special and needs to be powered on before any of the > + other cores can be used. This special core is called the top core and should > + have the compatible string that corresponds to top cores. > + > +properties: > + $nodename: > + pattern: '^npu@[a-f0-9]+$' > + > + compatible: > + enum: > + - rockchip,rk3588-rknn-core-top > + - rockchip,rk3588-rknn-core > + > + reg: > + maxItems: 3 > + > + reg-names: > + items: > + - const: pc > + - const: cna > + - const: core > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: aclk > + - const: hclk > + - const: npu > + - const: pclk > + > + interrupts: > + maxItems: 1 > + > + iommus: > + maxItems: 1 > + > + npu-supply: true > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 2 > + > + reset-names: > + items: > + - const: srst_a > + - const: srst_h > + > + sram-supply: true > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interrupts > + - iommus > + - power-domains > + - resets > + - reset-names > + - npu-supply > + - sram-supply > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - rockchip,rknn-core-top should be rockchip,rk3588-rknn-core-top I think > + then: > + properties: > + clocks: > + minItems: 4 > + > + clock-names: > + minItems: 4 > + - if: > + properties: > + compatible: > + contains: > + enum: > + - rockchip,rknn-core should be rockchip,rk3588-rknn-core > + then: > + properties: > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 Heiko

3 weeks, 1 day

Re: [PATCH v5 07/10] accel/rocket: Add job submission IOCTL

by Rob Herring

On Tue, May 20, 2025 at 12:27:00PM +0200, Tomeu Vizoso wrote: > Using the DRM GPU scheduler infrastructure, with a scheduler for each > core. > > Userspace can decide for a series of tasks to be executed sequentially > in the same core, so SRAM locality can be taken advantage of. > > The job submission code was initially based on Panfrost. > > v2: > - Remove hardcoded number of cores > - Misc. style fixes (Jeffrey Hugo) > - Repack IOCTL struct (Jeffrey Hugo) > > v3: > - Adapt to a split of the register block in the DT bindings (Nicolas > Frattaroli) > - Make use of GPL-2.0-only for the copyright notice (Jeff Hugo) > - Use drm_* logging functions (Thomas Zimmermann) > - Rename reg i/o macros (Thomas Zimmermann) > - Add padding to ioctls and check for zero (Jeff Hugo) > - Improve error handling (Nicolas Frattaroli) > > Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net> > diff --git a/drivers/accel/rocket/rocket_job.c b/drivers/accel/rocket/rocket_job.c > new file mode 100644 > index 0000000000000000000000000000000000000000..aee6ebdb2bd227439449fdfcab3ce7d1e39cd4c4 > --- /dev/null > +++ b/drivers/accel/rocket/rocket_job.c > @@ -0,0 +1,723 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* Copyright 2019 Linaro, Ltd, Rob Herring <robh(a)kernel.org> */ > +/* Copyright 2019 Collabora ltd. */ > +/* Copyright 2024-2025 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */ > + > +#include <drm/drm_print.h> > +#include <drm/drm_file.h> > +#include <drm/drm_gem.h> > +#include <drm/rocket_accel.h> > +#include <linux/interrupt.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > + > +#include "rocket_core.h" > +#include "rocket_device.h" > +#include "rocket_drv.h" > +#include "rocket_job.h" > +#include "rocket_registers.h" > + > +#define JOB_TIMEOUT_MS 500 > + > +static struct rocket_job * > +to_rocket_job(struct drm_sched_job *sched_job) > +{ > + return container_of(sched_job, struct rocket_job, base); > +} > + > +struct rocket_fence { > + struct dma_fence base; > + struct drm_device *dev; > + /* rocket seqno for signaled() test */ > + u64 seqno; > + int queue; AFAICT, you are not using any of the elements here. So you can just drop rocket_fence and use dma_fence. Rob

3 weeks, 1 day

Re: [PATCH v4 2/9] dma-fence: Use a flag for 64-bit seqnos

by Christian König

On 6/3/25 17:00, Tvrtko Ursulin wrote: > > On 03/06/2025 14:13, Maxime Ripard wrote: >> Hi, >> >> On Mon, Jun 02, 2025 at 04:42:27PM +0200, Christian König wrote: >>> On 6/2/25 15:05, Tvrtko Ursulin wrote: >>>> On 15/05/2025 14:15, Christian König wrote: >>>>> Hey drm-misc maintainers, >>>>> >>>>> can you guys please backmerge drm-next into drm-misc-next? >>>>> >>>>> I want to push this patch here but it depends on changes which are partially in drm-next and partially in drm-misc-next. >>>> >>>> Looks like the backmerge is still pending? >>> >>> Yes, @Maarten, @Maxime and @Thomas ping on this. >> >> It's done > > Thanks Maxime! > > Christian, I can merge 2-5 to take some load off you if you want? Sure, go ahead. Then I can call it a day for today :) Cheers, Christian. > > Regards, > > Tvrtko >

3 weeks, 1 day

Re: [PATCH v4 2/9] dma-fence: Use a flag for 64-bit seqnos

by Christian König

On 6/2/25 15:05, Tvrtko Ursulin wrote: > > Hi, > > On 15/05/2025 14:15, Christian König wrote: >> Hey drm-misc maintainers, >> >> can you guys please backmerge drm-next into drm-misc-next? >> >> I want to push this patch here but it depends on changes which are partially in drm-next and partially in drm-misc-next. > > Looks like the backmerge is still pending? Yes, @Maarten, @Maxime and @Thomas ping on this. > In the meantime, Christian, any chance you will have some bandwith to think about the tail end of the series? Specifically patch 6 and how that is used onward. Well the RCU grace period is quite a nifty hack. I wanted to go over it again after merging the first patches from this series. In general looks like a good idea to me, I just don't like that we explicitely need to expose dma_fence_access_begin() and dma_fence_access_end(). Especially we can't do that while calling fence->ops->release. Regards, Christian. > > Regards, > > Tvrtko > >> On 5/15/25 11:49, Tvrtko Ursulin wrote: >>> With the goal of reducing the need for drivers to touch (and dereference) >>> fence->ops, we move the 64-bit seqnos flag from struct dma_fence_ops to >>> the fence->flags. >>> >>> Drivers which were setting this flag are changed to use new >>> dma_fence_init64() instead of dma_fence_init(). >>> >>> v2: >>> * Streamlined init and added kerneldoc. >>> * Rebase for amdgpu userq which landed since. >>> >>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)igalia.com> >>> Reviewed-by: Christian König <christian.koenig(a)amd.com> # v1 >>> --- >>> drivers/dma-buf/dma-fence-chain.c | 5 +- >>> drivers/dma-buf/dma-fence.c | 69 ++++++++++++++----- >>> .../drm/amd/amdgpu/amdgpu_eviction_fence.c | 7 +- >>> .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 5 +- >>> .../gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c | 5 +- >>> include/linux/dma-fence.h | 14 ++-- >>> 6 files changed, 64 insertions(+), 41 deletions(-) >>> >>> diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c >>> index 90424f23fd73..a8a90acf4f34 100644 >>> --- a/drivers/dma-buf/dma-fence-chain.c >>> +++ b/drivers/dma-buf/dma-fence-chain.c >>> @@ -218,7 +218,6 @@ static void dma_fence_chain_set_deadline(struct dma_fence *fence, >>> } >>> const struct dma_fence_ops dma_fence_chain_ops = { >>> - .use_64bit_seqno = true, >>> .get_driver_name = dma_fence_chain_get_driver_name, >>> .get_timeline_name = dma_fence_chain_get_timeline_name, >>> .enable_signaling = dma_fence_chain_enable_signaling, >>> @@ -262,8 +261,8 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, >>> seqno = max(prev->seqno, seqno); >>> } >>> - dma_fence_init(&chain->base, &dma_fence_chain_ops, >>> - &chain->lock, context, seqno); >>> + dma_fence_init64(&chain->base, &dma_fence_chain_ops, &chain->lock, >>> + context, seqno); >>> /* >>> * Chaining dma_fence_chain container together is only allowed through >>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >>> index f0cdd3e99d36..705b59787731 100644 >>> --- a/drivers/dma-buf/dma-fence.c >>> +++ b/drivers/dma-buf/dma-fence.c >>> @@ -989,24 +989,9 @@ void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq) >>> } >>> EXPORT_SYMBOL(dma_fence_describe); >>> -/** >>> - * dma_fence_init - Initialize a custom fence. >>> - * @fence: the fence to initialize >>> - * @ops: the dma_fence_ops for operations on this fence >>> - * @lock: the irqsafe spinlock to use for locking this fence >>> - * @context: the execution context this fence is run on >>> - * @seqno: a linear increasing sequence number for this context >>> - * >>> - * Initializes an allocated fence, the caller doesn't have to keep its >>> - * refcount after committing with this fence, but it will need to hold a >>> - * refcount again if &dma_fence_ops.enable_signaling gets called. >>> - * >>> - * context and seqno are used for easy comparison between fences, allowing >>> - * to check which fence is later by simply using dma_fence_later(). >>> - */ >>> -void >>> -dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> - spinlock_t *lock, u64 context, u64 seqno) >>> +static void >>> +__dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> + spinlock_t *lock, u64 context, u64 seqno, unsigned long flags) >>> { >>> BUG_ON(!lock); >>> BUG_ON(!ops || !ops->get_driver_name || !ops->get_timeline_name); >>> @@ -1017,9 +1002,55 @@ dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> fence->lock = lock; >>> fence->context = context; >>> fence->seqno = seqno; >>> - fence->flags = 0UL; >>> + fence->flags = flags; >>> fence->error = 0; >>> trace_dma_fence_init(fence); >>> } >>> + >>> +/** >>> + * dma_fence_init - Initialize a custom fence. >>> + * @fence: the fence to initialize >>> + * @ops: the dma_fence_ops for operations on this fence >>> + * @lock: the irqsafe spinlock to use for locking this fence >>> + * @context: the execution context this fence is run on >>> + * @seqno: a linear increasing sequence number for this context >>> + * >>> + * Initializes an allocated fence, the caller doesn't have to keep its >>> + * refcount after committing with this fence, but it will need to hold a >>> + * refcount again if &dma_fence_ops.enable_signaling gets called. >>> + * >>> + * context and seqno are used for easy comparison between fences, allowing >>> + * to check which fence is later by simply using dma_fence_later(). >>> + */ >>> +void >>> +dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> + spinlock_t *lock, u64 context, u64 seqno) >>> +{ >>> + __dma_fence_init(fence, ops, lock, context, seqno, 0UL); >>> +} >>> EXPORT_SYMBOL(dma_fence_init); >>> + >>> +/** >>> + * dma_fence_init64 - Initialize a custom fence with 64-bit seqno support. >>> + * @fence: the fence to initialize >>> + * @ops: the dma_fence_ops for operations on this fence >>> + * @lock: the irqsafe spinlock to use for locking this fence >>> + * @context: the execution context this fence is run on >>> + * @seqno: a linear increasing sequence number for this context >>> + * >>> + * Initializes an allocated fence, the caller doesn't have to keep its >>> + * refcount after committing with this fence, but it will need to hold a >>> + * refcount again if &dma_fence_ops.enable_signaling gets called. >>> + * >>> + * Context and seqno are used for easy comparison between fences, allowing >>> + * to check which fence is later by simply using dma_fence_later(). >>> + */ >>> +void >>> +dma_fence_init64(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> + spinlock_t *lock, u64 context, u64 seqno) >>> +{ >>> + __dma_fence_init(fence, ops, lock, context, seqno, >>> + BIT(DMA_FENCE_FLAG_SEQNO64_BIT)); >>> +} >>> +EXPORT_SYMBOL(dma_fence_init64); >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c >>> index 1a7469543db5..79713421bffe 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c >>> @@ -134,7 +134,6 @@ static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f) >>> } >>> static const struct dma_fence_ops amdgpu_eviction_fence_ops = { >>> - .use_64bit_seqno = true, >>> .get_driver_name = amdgpu_eviction_fence_get_driver_name, >>> .get_timeline_name = amdgpu_eviction_fence_get_timeline_name, >>> .enable_signaling = amdgpu_eviction_fence_enable_signaling, >>> @@ -160,9 +159,9 @@ amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr) >>> ev_fence->evf_mgr = evf_mgr; >>> get_task_comm(ev_fence->timeline_name, current); >>> spin_lock_init(&ev_fence->lock); >>> - dma_fence_init(&ev_fence->base, &amdgpu_eviction_fence_ops, >>> - &ev_fence->lock, evf_mgr->ev_fence_ctx, >>> - atomic_inc_return(&evf_mgr->ev_fence_seq)); >>> + dma_fence_init64(&ev_fence->base, &amdgpu_eviction_fence_ops, >>> + &ev_fence->lock, evf_mgr->ev_fence_ctx, >>> + atomic_inc_return(&evf_mgr->ev_fence_seq)); >>> return ev_fence; >>> } >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c >>> index 029cb24c28b3..5e92d00a591f 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c >>> @@ -239,8 +239,8 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, >>> fence = &userq_fence->base; >>> userq_fence->fence_drv = fence_drv; >>> - dma_fence_init(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, >>> - fence_drv->context, seq); >>> + dma_fence_init64(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, >>> + fence_drv->context, seq); >>> amdgpu_userq_fence_driver_get(fence_drv); >>> dma_fence_get(fence); >>> @@ -334,7 +334,6 @@ static void amdgpu_userq_fence_release(struct dma_fence *f) >>> } >>> static const struct dma_fence_ops amdgpu_userq_fence_ops = { >>> - .use_64bit_seqno = true, >>> .get_driver_name = amdgpu_userq_fence_get_driver_name, >>> .get_timeline_name = amdgpu_userq_fence_get_timeline_name, >>> .signaled = amdgpu_userq_fence_signaled, >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c >>> index 51cddfa3f1e8..5d26797356a3 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c >>> @@ -71,7 +71,6 @@ static void amdgpu_tlb_fence_work(struct work_struct *work) >>> } >>> static const struct dma_fence_ops amdgpu_tlb_fence_ops = { >>> - .use_64bit_seqno = true, >>> .get_driver_name = amdgpu_tlb_fence_get_driver_name, >>> .get_timeline_name = amdgpu_tlb_fence_get_timeline_name >>> }; >>> @@ -101,8 +100,8 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm >>> INIT_WORK(&f->work, amdgpu_tlb_fence_work); >>> spin_lock_init(&f->lock); >>> - dma_fence_init(&f->base, &amdgpu_tlb_fence_ops, &f->lock, >>> - vm->tlb_fence_context, atomic64_read(&vm->tlb_seq)); >>> + dma_fence_init64(&f->base, &amdgpu_tlb_fence_ops, &f->lock, >>> + vm->tlb_fence_context, atomic64_read(&vm->tlb_seq)); >>> /* TODO: We probably need a separate wq here */ >>> dma_fence_get(&f->base); >>> diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h >>> index 48b5202c531d..a34a0dcdc446 100644 >>> --- a/include/linux/dma-fence.h >>> +++ b/include/linux/dma-fence.h >>> @@ -97,6 +97,7 @@ struct dma_fence { >>> }; >>> enum dma_fence_flag_bits { >>> + DMA_FENCE_FLAG_SEQNO64_BIT, >>> DMA_FENCE_FLAG_SIGNALED_BIT, >>> DMA_FENCE_FLAG_TIMESTAMP_BIT, >>> DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >>> @@ -124,14 +125,6 @@ struct dma_fence_cb { >>> * >>> */ >>> struct dma_fence_ops { >>> - /** >>> - * @use_64bit_seqno: >>> - * >>> - * True if this dma_fence implementation uses 64bit seqno, false >>> - * otherwise. >>> - */ >>> - bool use_64bit_seqno; >>> - >>> /** >>> * @get_driver_name: >>> * >>> @@ -262,6 +255,9 @@ struct dma_fence_ops { >>> void dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> spinlock_t *lock, u64 context, u64 seqno); >>> +void dma_fence_init64(struct dma_fence *fence, const struct dma_fence_ops *ops, >>> + spinlock_t *lock, u64 context, u64 seqno); >>> + >>> void dma_fence_release(struct kref *kref); >>> void dma_fence_free(struct dma_fence *fence); >>> void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); >>> @@ -454,7 +450,7 @@ static inline bool __dma_fence_is_later(struct dma_fence *fence, u64 f1, u64 f2) >>> * 32bit sequence numbers. Use a 64bit compare when the driver says to >>> * do so. >>> */ >>> - if (fence->ops->use_64bit_seqno) >>> + if (test_bit(DMA_FENCE_FLAG_SEQNO64_BIT, &fence->flags)) >>> return f1 > f2; >>> return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; >> >

3 weeks, 1 day

Re: [PATCH v4 0/4] Implement dmabuf direct I/O via copy_file_range

by Christoph Hellwig

This is a really weird interface. No one has yet to explain why dmabuf is so special that we can't support direct I/O to it when we can support it to otherwise exotic mappings like PCI P2P ones.

3 weeks, 1 day

Re: [PATCH v4 2/9] dma-fence: Use a flag for 64-bit seqnos

by Christian König

On 6/3/25 14:48, Tvrtko Ursulin wrote: > > On 03/06/2025 13:40, Christian König wrote: >> On 6/3/25 13:30, Tvrtko Ursulin wrote: >>> >>> On 02/06/2025 19:00, Christian König wrote: >>>> On 6/2/25 17:25, Tvrtko Ursulin wrote: >>>>> >>>>> On 02/06/2025 15:42, Christian König wrote: >>>>>> On 6/2/25 15:05, Tvrtko Ursulin wrote: >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> On 15/05/2025 14:15, Christian König wrote: >>>>>>>> Hey drm-misc maintainers, >>>>>>>> >>>>>>>> can you guys please backmerge drm-next into drm-misc-next? >>>>>>>> >>>>>>>> I want to push this patch here but it depends on changes which are partially in drm-next and partially in drm-misc-next. >>>>>>> >>>>>>> Looks like the backmerge is still pending? >>>>>> >>>>>> Yes, @Maarten, @Maxime and @Thomas ping on this. >>>>>> >>>>>>> In the meantime, Christian, any chance you will have some bandwith to think about the tail end of the series? Specifically patch 6 and how that is used onward. >>>>>> >>>>>> Well the RCU grace period is quite a nifty hack. I wanted to go over it again after merging the first patches from this series. >>>>>> >>>>>> In general looks like a good idea to me, I just don't like that we explicitely need to expose dma_fence_access_begin() and dma_fence_access_end(). >>>>>> >>>>>> Especially we can't do that while calling fence->ops->release. >>>>> >>>>> Hm why not? You think something will take offence of the rcu_read_lock()? >>>> >>>> Yes, especially it is perfectly legitimate to call synchronize_rcu() or lock semaphores/mutexes from that callback. >>>> >>>> Either keep the RCU critical section only for the trace or even better come up with some different approach, e.g. copying the string under the RCU lock or something like that. >>> >>> Hmm but the kerneldoc explicity says callback can be called from irq context: >>> >>> /** >>> * @release: >>> * >>> * Called on destruction of fence to release additional resources. >>> * Can be called from irq context. This callback is optional. If it is >>> * NULL, then dma_fence_free() is instead called as the default >>> * implementation. >>> */ >>> void (*release)(struct dma_fence *fence); >> >> Ah, right. I mixed that up with the dma-buf object. >> >> Yeah in that case that is probably harmless. We delegate the final free to a work item if necessary anyway. >> >> But I would still like to avoid having the RCU cover the release as well. Or why is there any reason why we would explicitely want to do this? > > I can't remember there was a particular reason. Obviously the driver/timeline name vfunc access I needed a dma_fence_access_begin/end() block so maybe I was just sloppy and put the end at the end of the function instead of at the end of the block which can dereference them. Yeah that's the next topic I would rather like to improve. We are kind of hiding that the returned strings are using RCU protection. In other words it would be nicer if we could add an __rcu tag to the get_driver_name/get_timeline_name callbacks and let the automated tools complain if somebody isn't doing the proper RCU handling. The problem is that as far as I know that is not supported by the automated tools (would be cool if somebody could double check that). +We would need to convert the get_timeline/get_timeline_name function to something like func(struct dma_fence *fence, const char __rcu **out) to make that work. Regards, Christian. > > I will pull it earlier for the next respin, assuming no gotchas get discovered in the process. > > Regards, > > Tvrtko > >> >> Regards, >> Christian. >> >>> >>> >>> Regards, >>> >>> Tvrtko >>> >>>> >>>> Regards, >>>> Christian. >>>> >>>>> >>>>> Regards, >>>>> >>>>> Tvrtko >>>>> >>>>>>>> On 5/15/25 11:49, Tvrtko Ursulin wrote: >>>>>>>>> With the goal of reducing the need for drivers to touch (and dereference) >>>>>>>>> fence->ops, we move the 64-bit seqnos flag from struct dma_fence_ops to >>>>>>>>> the fence->flags. >>>>>>>>> >>>>>>>>> Drivers which were setting this flag are changed to use new >>>>>>>>> dma_fence_init64() instead of dma_fence_init(). >>>>>>>>> >>>>>>>>> v2: >>>>>>>>> * Streamlined init and added kerneldoc. >>>>>>>>> * Rebase for amdgpu userq which landed since. >>>>>>>>> >>>>>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)igalia.com> >>>>>>>>> Reviewed-by: Christian König <christian.koenig(a)amd.com> # v1 >>>>>>>>> --- >>>>>>>>> drivers/dma-buf/dma-fence-chain.c | 5 +- >>>>>>>>> drivers/dma-buf/dma-fence.c | 69 ++++++++++++++----- >>>>>>>>> .../drm/amd/amdgpu/amdgpu_eviction_fence.c | 7 +- >>>>>>>>> .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 5 +- >>>>>>>>> .../gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c | 5 +- >>>>>>>>> include/linux/dma-fence.h | 14 ++-- >>>>>>>>> 6 files changed, 64 insertions(+), 41 deletions(-) >>>>>>>>> >>>>>>>>> diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c >>>>>>>>> index 90424f23fd73..a8a90acf4f34 100644 >>>>>>>>> --- a/drivers/dma-buf/dma-fence-chain.c >>>>>>>>> +++ b/drivers/dma-buf/dma-fence-chain.c >>>>>>>>> @@ -218,7 +218,6 @@ static void dma_fence_chain_set_deadline(struct dma_fence *fence, >>>>>>>>> } >>>>>>>>> const struct dma_fence_ops dma_fence_chain_ops = { >>>>>>>>> - .use_64bit_seqno = true, >>>>>>>>> .get_driver_name = dma_fence_chain_get_driver_name, >>>>>>>>> .get_timeline_name = dma_fence_chain_get_timeline_name, >>>>>>>>> .enable_signaling = dma_fence_chain_enable_signaling, >>>>>>>>> @@ -262,8 +261,8 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, >>>>>>>>> seqno = max(prev->seqno, seqno); >>>>>>>>> } >>>>>>>>> - dma_fence_init(&chain->base, &dma_fence_chain_ops, >>>>>>>>> - &chain->lock, context, seqno); >>>>>>>>> + dma_fence_init64(&chain->base, &dma_fence_chain_ops, &chain->lock, >>>>>>>>> + context, seqno); >>>>>>>>> /* >>>>>>>>> * Chaining dma_fence_chain container together is only allowed through >>>>>>>>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >>>>>>>>> index f0cdd3e99d36..705b59787731 100644 >>>>>>>>> --- a/drivers/dma-buf/dma-fence.c >>>>>>>>> +++ b/drivers/dma-buf/dma-fence.c >>>>>>>>> @@ -989,24 +989,9 @@ void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq) >>>>>>>>> } >>>>>>>>> EXPORT_SYMBOL(dma_fence_describe); >>>>>>>>> -/** >>>>>>>>> - * dma_fence_init - Initialize a custom fence. >>>>>>>>> - * @fence: the fence to initialize >>>>>>>>> - * @ops: the dma_fence_ops for operations on this fence >>>>>>>>> - * @lock: the irqsafe spinlock to use for locking this fence >>>>>>>>> - * @context: the execution context this fence is run on >>>>>>>>> - * @seqno: a linear increasing sequence number for this context >>>>>>>>> - * >>>>>>>>> - * Initializes an allocated fence, the caller doesn't have to keep its >>>>>>>>> - * refcount after committing with this fence, but it will need to hold a >>>>>>>>> - * refcount again if &dma_fence_ops.enable_signaling gets called. >>>>>>>>> - * >>>>>>>>> - * context and seqno are used for easy comparison between fences, allowing >>>>>>>>> - * to check which fence is later by simply using dma_fence_later(). >>>>>>>>> - */ >>>>>>>>> -void >>>>>>>>> -dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> - spinlock_t *lock, u64 context, u64 seqno) >>>>>>>>> +static void >>>>>>>>> +__dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> + spinlock_t *lock, u64 context, u64 seqno, unsigned long flags) >>>>>>>>> { >>>>>>>>> BUG_ON(!lock); >>>>>>>>> BUG_ON(!ops || !ops->get_driver_name || !ops->get_timeline_name); >>>>>>>>> @@ -1017,9 +1002,55 @@ dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> fence->lock = lock; >>>>>>>>> fence->context = context; >>>>>>>>> fence->seqno = seqno; >>>>>>>>> - fence->flags = 0UL; >>>>>>>>> + fence->flags = flags; >>>>>>>>> fence->error = 0; >>>>>>>>> trace_dma_fence_init(fence); >>>>>>>>> } >>>>>>>>> + >>>>>>>>> +/** >>>>>>>>> + * dma_fence_init - Initialize a custom fence. >>>>>>>>> + * @fence: the fence to initialize >>>>>>>>> + * @ops: the dma_fence_ops for operations on this fence >>>>>>>>> + * @lock: the irqsafe spinlock to use for locking this fence >>>>>>>>> + * @context: the execution context this fence is run on >>>>>>>>> + * @seqno: a linear increasing sequence number for this context >>>>>>>>> + * >>>>>>>>> + * Initializes an allocated fence, the caller doesn't have to keep its >>>>>>>>> + * refcount after committing with this fence, but it will need to hold a >>>>>>>>> + * refcount again if &dma_fence_ops.enable_signaling gets called. >>>>>>>>> + * >>>>>>>>> + * context and seqno are used for easy comparison between fences, allowing >>>>>>>>> + * to check which fence is later by simply using dma_fence_later(). >>>>>>>>> + */ >>>>>>>>> +void >>>>>>>>> +dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> + spinlock_t *lock, u64 context, u64 seqno) >>>>>>>>> +{ >>>>>>>>> + __dma_fence_init(fence, ops, lock, context, seqno, 0UL); >>>>>>>>> +} >>>>>>>>> EXPORT_SYMBOL(dma_fence_init); >>>>>>>>> + >>>>>>>>> +/** >>>>>>>>> + * dma_fence_init64 - Initialize a custom fence with 64-bit seqno support. >>>>>>>>> + * @fence: the fence to initialize >>>>>>>>> + * @ops: the dma_fence_ops for operations on this fence >>>>>>>>> + * @lock: the irqsafe spinlock to use for locking this fence >>>>>>>>> + * @context: the execution context this fence is run on >>>>>>>>> + * @seqno: a linear increasing sequence number for this context >>>>>>>>> + * >>>>>>>>> + * Initializes an allocated fence, the caller doesn't have to keep its >>>>>>>>> + * refcount after committing with this fence, but it will need to hold a >>>>>>>>> + * refcount again if &dma_fence_ops.enable_signaling gets called. >>>>>>>>> + * >>>>>>>>> + * Context and seqno are used for easy comparison between fences, allowing >>>>>>>>> + * to check which fence is later by simply using dma_fence_later(). >>>>>>>>> + */ >>>>>>>>> +void >>>>>>>>> +dma_fence_init64(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> + spinlock_t *lock, u64 context, u64 seqno) >>>>>>>>> +{ >>>>>>>>> + __dma_fence_init(fence, ops, lock, context, seqno, >>>>>>>>> + BIT(DMA_FENCE_FLAG_SEQNO64_BIT)); >>>>>>>>> +} >>>>>>>>> +EXPORT_SYMBOL(dma_fence_init64); >>>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c >>>>>>>>> index 1a7469543db5..79713421bffe 100644 >>>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c >>>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c >>>>>>>>> @@ -134,7 +134,6 @@ static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f) >>>>>>>>> } >>>>>>>>> static const struct dma_fence_ops amdgpu_eviction_fence_ops = { >>>>>>>>> - .use_64bit_seqno = true, >>>>>>>>> .get_driver_name = amdgpu_eviction_fence_get_driver_name, >>>>>>>>> .get_timeline_name = amdgpu_eviction_fence_get_timeline_name, >>>>>>>>> .enable_signaling = amdgpu_eviction_fence_enable_signaling, >>>>>>>>> @@ -160,9 +159,9 @@ amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr) >>>>>>>>> ev_fence->evf_mgr = evf_mgr; >>>>>>>>> get_task_comm(ev_fence->timeline_name, current); >>>>>>>>> spin_lock_init(&ev_fence->lock); >>>>>>>>> - dma_fence_init(&ev_fence->base, &amdgpu_eviction_fence_ops, >>>>>>>>> - &ev_fence->lock, evf_mgr->ev_fence_ctx, >>>>>>>>> - atomic_inc_return(&evf_mgr->ev_fence_seq)); >>>>>>>>> + dma_fence_init64(&ev_fence->base, &amdgpu_eviction_fence_ops, >>>>>>>>> + &ev_fence->lock, evf_mgr->ev_fence_ctx, >>>>>>>>> + atomic_inc_return(&evf_mgr->ev_fence_seq)); >>>>>>>>> return ev_fence; >>>>>>>>> } >>>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c >>>>>>>>> index 029cb24c28b3..5e92d00a591f 100644 >>>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c >>>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c >>>>>>>>> @@ -239,8 +239,8 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, >>>>>>>>> fence = &userq_fence->base; >>>>>>>>> userq_fence->fence_drv = fence_drv; >>>>>>>>> - dma_fence_init(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, >>>>>>>>> - fence_drv->context, seq); >>>>>>>>> + dma_fence_init64(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, >>>>>>>>> + fence_drv->context, seq); >>>>>>>>> amdgpu_userq_fence_driver_get(fence_drv); >>>>>>>>> dma_fence_get(fence); >>>>>>>>> @@ -334,7 +334,6 @@ static void amdgpu_userq_fence_release(struct dma_fence *f) >>>>>>>>> } >>>>>>>>> static const struct dma_fence_ops amdgpu_userq_fence_ops = { >>>>>>>>> - .use_64bit_seqno = true, >>>>>>>>> .get_driver_name = amdgpu_userq_fence_get_driver_name, >>>>>>>>> .get_timeline_name = amdgpu_userq_fence_get_timeline_name, >>>>>>>>> .signaled = amdgpu_userq_fence_signaled, >>>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c >>>>>>>>> index 51cddfa3f1e8..5d26797356a3 100644 >>>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c >>>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c >>>>>>>>> @@ -71,7 +71,6 @@ static void amdgpu_tlb_fence_work(struct work_struct *work) >>>>>>>>> } >>>>>>>>> static const struct dma_fence_ops amdgpu_tlb_fence_ops = { >>>>>>>>> - .use_64bit_seqno = true, >>>>>>>>> .get_driver_name = amdgpu_tlb_fence_get_driver_name, >>>>>>>>> .get_timeline_name = amdgpu_tlb_fence_get_timeline_name >>>>>>>>> }; >>>>>>>>> @@ -101,8 +100,8 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm >>>>>>>>> INIT_WORK(&f->work, amdgpu_tlb_fence_work); >>>>>>>>> spin_lock_init(&f->lock); >>>>>>>>> - dma_fence_init(&f->base, &amdgpu_tlb_fence_ops, &f->lock, >>>>>>>>> - vm->tlb_fence_context, atomic64_read(&vm->tlb_seq)); >>>>>>>>> + dma_fence_init64(&f->base, &amdgpu_tlb_fence_ops, &f->lock, >>>>>>>>> + vm->tlb_fence_context, atomic64_read(&vm->tlb_seq)); >>>>>>>>> /* TODO: We probably need a separate wq here */ >>>>>>>>> dma_fence_get(&f->base); >>>>>>>>> diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h >>>>>>>>> index 48b5202c531d..a34a0dcdc446 100644 >>>>>>>>> --- a/include/linux/dma-fence.h >>>>>>>>> +++ b/include/linux/dma-fence.h >>>>>>>>> @@ -97,6 +97,7 @@ struct dma_fence { >>>>>>>>> }; >>>>>>>>> enum dma_fence_flag_bits { >>>>>>>>> + DMA_FENCE_FLAG_SEQNO64_BIT, >>>>>>>>> DMA_FENCE_FLAG_SIGNALED_BIT, >>>>>>>>> DMA_FENCE_FLAG_TIMESTAMP_BIT, >>>>>>>>> DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >>>>>>>>> @@ -124,14 +125,6 @@ struct dma_fence_cb { >>>>>>>>> * >>>>>>>>> */ >>>>>>>>> struct dma_fence_ops { >>>>>>>>> - /** >>>>>>>>> - * @use_64bit_seqno: >>>>>>>>> - * >>>>>>>>> - * True if this dma_fence implementation uses 64bit seqno, false >>>>>>>>> - * otherwise. >>>>>>>>> - */ >>>>>>>>> - bool use_64bit_seqno; >>>>>>>>> - >>>>>>>>> /** >>>>>>>>> * @get_driver_name: >>>>>>>>> * >>>>>>>>> @@ -262,6 +255,9 @@ struct dma_fence_ops { >>>>>>>>> void dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> spinlock_t *lock, u64 context, u64 seqno); >>>>>>>>> +void dma_fence_init64(struct dma_fence *fence, const struct dma_fence_ops *ops, >>>>>>>>> + spinlock_t *lock, u64 context, u64 seqno); >>>>>>>>> + >>>>>>>>> void dma_fence_release(struct kref *kref); >>>>>>>>> void dma_fence_free(struct dma_fence *fence); >>>>>>>>> void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); >>>>>>>>> @@ -454,7 +450,7 @@ static inline bool __dma_fence_is_later(struct dma_fence *fence, u64 f1, u64 f2) >>>>>>>>> * 32bit sequence numbers. Use a 64bit compare when the driver says to >>>>>>>>> * do so. >>>>>>>>> */ >>>>>>>>> - if (fence->ops->use_64bit_seqno) >>>>>>>>> + if (test_bit(DMA_FENCE_FLAG_SEQNO64_BIT, &fence->flags)) >>>>>>>>> return f1 > f2; >>>>>>>>> return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> >

3 weeks, 1 day

Re: [PATCH v4 2/4] dmabuf: Implement copy_file_range callback for dmabuf direct I/O prep

by Christoph Hellwig

On Tue, Jun 03, 2025 at 05:52:43PM +0800, wangtao wrote: > +static ssize_t dma_buf_rw_file(struct dma_buf *dmabuf, loff_t my_pos, > + struct file *file, loff_t pos, size_t count, bool is_write) > +{ > + if (!dmabuf->ops->rw_file) > + return -EINVAL; > + > + if (my_pos >= dmabuf->size) > + count = 0; > + else > + count = min_t(size_t, count, dmabuf->size - my_pos); > + if (!count) > + return 0; > + > + return dmabuf->ops->rw_file(dmabuf, my_pos, file, pos, count, is_write); So despite claiming in the cover letter that dmabufs can't support direct I/O you are just reimplementing it badly here using a side interface.

3 weeks, 1 day

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