Am Freitag, 6. Juni 2025, 08:28:20 Mitteleuropäische Sommerzeit schrieb Tomeu Vizoso:

This series adds a new driver for the NPU that Rockchip includes in its newer SoCs, developed by them on the NVDLA base.

In its current form, it supports the specific NPU in the RK3588 SoC.

The userspace driver is part of Mesa and an initial draft can be found at:

https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29698

Signed-off-by: Tomeu Vizoso tomeu@tomeuvizoso.net

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Nicolas Frattaroli (2): arm64: dts: rockchip: add pd_npu label for RK3588 power domains arm64: dts: rockchip: enable NPU on ROCK 5B

Tomeu Vizoso (8): accel/rocket: Add registers header accel/rocket: Add a new driver for Rockchip's NPU accel/rocket: Add IOCTL for BO creation accel/rocket: Add job submission IOCTL accel/rocket: Add IOCTLs for synchronizing memory accesses dt-bindings: npu: rockchip,rknn: Add bindings arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-base arm64: dts: rockchip: Enable the NPU on quartzpro64

from a handling point of view, I would expect patch 1 - 6 (driver code + dt-binding patch) to go through some driver tree but have not clue which one that is.

And afterwards, I would pick up the arm64 devicetree additions patches 7 - 10 .

Heiko