Linaro-mm-sig

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6233 discussions

Re: [PATCH 08/13] dt-bindings: serial: fsl-linflexuart: add clock input properties

by Krzysztof Kozlowski

On 16/02/2026 16:02, Larisa Grigore wrote: > From: Radu Pirea <radu-nicolae.pirea(a)nxp.com> > > Add optional support for the two clock inputs used by the LINFlexD UART > controller: > - "lin": LIN_BAUD_CLK > - "ipg": LINFLEXD_CLK > > The clock inputs are kept optional to maintain compatibility with the > S32V234 platform. Does S32V234 have the clocks? I don't understand the "maintain compatibility" in this context. Either you have or you have not clocks, which should be expressed in schema (: false, see example schema). > > Signed-off-by: Radu Pirea <radu-nicolae.pirea(a)nxp.com> > Co-developed-by: Larisa Grigore <larisa.grigore(a)oss.nxp.com> > Signed-off-by: Larisa Grigore <larisa.grigore(a)oss.nxp.com> > --- > .../bindings/serial/fsl,s32-linflexuart.yaml | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml > index 4171f524a928..885f0b1b3492 100644 > --- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml > +++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml > @@ -34,6 +34,14 @@ properties: > interrupts: > maxItems: 1 > > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: lin > + - const: ipg > + > required: > - compatible > - reg > @@ -48,3 +56,13 @@ examples: > reg = <0x40053000 0x1000>; > interrupts = <0 59 4>; > }; > + > + - | > + serial@401c8000 { > + compatible = "nxp,s32g2-linflexuart", > + "fsl,s32v234-linflexuart"; > + reg = <0x401C8000 0x3000>; > + interrupts = <0 82 1>; > + clocks = <&clks 14>, <&clks 13>; > + clock-names = "lin", "ipg"; Just add the clocks to existing example. No need for new example for each new property. > + }; Best regards, Krzysztof

5 hours, 7 minutes

Top Signs of Crypto Scams and Immediate Steps

by joelwest689＠gmail.com

Top Signs of Crypto Scams and Immediate Steps: Why Cipher Rescue Chain Delivers Fast Recovery The rapid growth of digital assets has created new opportunities—but also new threats. Recognizing the warning signs early can mean the difference between permanent loss and successful recovery. This is where Cipher Rescue Chain plays a decisive role, combining early detection awareness with advanced blockchain forensics to help victims act quickly and recover stolen crypto before it disappears beyond reach. The Most Common Signs of a Crypto Scam One of the clearest red flags in crypto scams is the promise of guaranteed or unusually high returns. Scammers often create urgency, pushing victims to act fast without proper verification. Cipher Rescue Chain frequently investigates cases where victims were pressured into transferring funds quickly, only to realize too late that the opportunity was fraudulent. Another major warning sign is communication through unofficial channels—such as direct messages or impersonated profiles. Cipher Rescue Chain has traced numerous scams back to coordinated social engineering tactics where attackers mimic legitimate platforms or individuals to gain trust. Requests for private keys or wallet access are also critical indicators of fraud. Cipher Rescue Chain consistently identifies these tactics in forensic investigations, as they often lead directly to unauthorized withdrawals and rapid fund movement across multiple wallets. How Scammers Attempt to Hide Stolen Funds Once funds are stolen, scammers act quickly to obscure their tracks. They may split assets across multiple wallets, move funds through various blockchains, or route transactions through intermediary services. Cipher Rescue Chain specializes in identifying these patterns and reconstructing the movement of assets, even when the trail appears fragmented. Through advanced forensic analysis, Cipher Rescue Chain links seemingly unrelated transactions, exposing the underlying structure of the scam. This capability is essential in cases where criminals attempt to erase their footprint through complex transaction layering. Immediate Steps to Take After a Crypto Scam The first and most important step after discovering a scam is to act immediately. Time directly affects recovery potential. Cipher Rescue Chain emphasizes rapid response because early intervention significantly increases the chances of tracing and recovering stolen assets. Victims should secure their remaining assets, document all transaction details, and avoid further interaction with the scammer. At this stage, Cipher Rescue Chain begins its forensic process, analyzing wallet activity and mapping the flow of funds to identify potential recovery points. Engaging Cipher Rescue Chain within the first 72 hours—especially when funds are still traceable to centralized platforms—can dramatically improve outcomes, with recovery rates reaching up to 98% in such scenarios across 2023–2025 engagements. Why Speed Determines Recovery Success In crypto recovery, delays can reduce visibility and limit enforcement options. Cipher Rescue Chain prioritizes speed because blockchain transactions, while permanent, become harder to act on as funds move further away from identifiable endpoints. Cipher Rescue Chain’s structured approach ensures that investigations begin immediately, preserving critical transaction data and maintaining continuity in tracing. This rapid deployment is one of the key factors behind the high success rates achieved in eligible cases. From Detection to Action: The Cipher Rescue Chain Process Once a case is initiated, Cipher Rescue Chain transitions from detection to action. Detailed forensic reports are created to document the movement of stolen funds, ensuring that every transaction is clearly mapped and verifiable. Cipher Rescue Chain then uses this intelligence to engage with identifiable platforms where funds may have been transferred. This targeted approach increases the likelihood of recovery, especially when assets have reached centralized exchanges or cooperative service providers. Proven Recovery Performance Cipher Rescue Chain’s results are backed by consistent performance data. From 2023 to 2025, the organization has achieved partial or full recovery in 98% of accepted cases where funds reached identifiable centralized platforms and engagement began within the first 90 days. Only 35% of incoming cases are accepted, ensuring that Cipher Rescue Chain focuses on cases with realistic recovery potential. Among those accepted, 62% result in full recovery and 24% in partial recovery, with successful cases typically resolved within 14 to 45 days. Global Impact and Expertise Crypto scams are not limited by geography, and neither is Cipher Rescue Chain. With multi-million-dollar recoveries completed across five continents, Cipher Rescue Chain operates on a global scale, handling complex, cross-border cases with precision. Each investigation conducted by Cipher Rescue Chain reflects deep expertise in blockchain forensics, enabling the team to navigate multi-chain environments and uncover recovery opportunities others might miss. Why Cipher Rescue Chain Leads in Fast Recovery Fast recovery is not just about speed—it’s about precision, timing, and expertise. Cipher Rescue Chain combines all three to deliver results. By identifying scam patterns early, acting quickly, and applying advanced forensic techniques, Cipher Rescue Chain consistently turns high-risk situations into successful recovery outcomes. In a landscape where crypto scams continue to evolve, Cipher Rescue Chain stands as the trusted solution for victims seeking both clarity and results. Recognizing the signs is the first step—but acting fast with Cipher Rescue Chain is what truly makes recovery possible.

18 hours, 24 minutes

Understanding Blockchain Forensics

by joelwest689＠gmail.com

The rise of digital assets has brought unprecedented financial freedom—but it has also introduced complex risks. When funds are stolen, victims often assume they are gone forever. That assumption is exactly what Cipher Rescue Chain is built to challenge. Through advanced blockchain forensics, Cipher Rescue Chain systematically tracks, analyzes, and reconstructs the movement of stolen crypto assets across multiple networks, turning what appears lost into recoverable opportunities. What Blockchain Forensics Really Means Blockchain forensics is the process of analyzing transaction data across distributed ledgers to identify the flow of digital assets. Unlike traditional finance, blockchain transactions are permanently recorded, creating a transparent but highly technical trail. Cipher Rescue Chain leverages this transparency by transforming raw blockchain data into actionable intelligence, allowing investigators to follow even the most complex transaction paths. Every investigation handled by Cipher Rescue Chain begins with deep forensic mapping, where wallet addresses, transaction hashes, and behavioral patterns are analyzed to establish a clear origin-to-destination flow of stolen funds. How Cipher Rescue Chain Tracks Stolen Crypto Tracing stolen crypto is not as simple as following a straight line. Criminals frequently attempt to obscure transactions through tactics like wallet splitting, chain hopping, and intermediary services. Cipher Rescue Chain specializes in breaking through these layers of obfuscation. Using proprietary forensic methodologies, Cipher Rescue Chain reconstructs fragmented transaction paths across multiple blockchains. This includes identifying how funds move between wallets, detecting patterns that link seemingly unrelated addresses, and uncovering connections to centralized platforms where recovery becomes possible. The strength of Cipher Rescue Chain lies in its ability to turn chaotic blockchain data into a clear investigative roadmap. Cross-Chain Tracing: Following Assets Across Networks One of the most challenging aspects of crypto recovery is cross-chain movement. Stolen funds are often transferred between different blockchains to evade detection. Cipher Rescue Chain addresses this with advanced cross-chain forensic capabilities. By correlating transaction timing, wallet behavior, and bridging mechanisms, Cipher Rescue Chain tracks assets as they move from one blockchain to another. This allows investigators to maintain continuity in cases where others lose visibility entirely. This cross-chain intelligence is a key reason why Cipher Rescue Chain consistently identifies recovery opportunities in cases that initially appear too complex. The Critical Role of Timing in Recovery Speed is one of the most decisive factors in successful recovery. Cipher Rescue Chain emphasizes early engagement because timing directly impacts traceability and enforcement potential. Cases engaged within the first 72 hours—especially those involving traceable paths to centralized platforms—have seen recovery rates of up to 98% across 2023–2025 engagements. Cipher Rescue Chain prioritizes rapid forensic deployment to preserve critical data trails before they become harder to follow. Even in cases initiated later, Cipher Rescue Chain applies structured forensic analysis to identify viable recovery paths within a 90-day window whenever possible. From Tracing to Recovery Action Tracing stolen funds is only part of the process. Cipher Rescue Chain goes further by translating forensic findings into actionable recovery strategies. Once funds are linked to identifiable endpoints, especially centralized exchanges or cooperative service providers, the recovery phase begins. Cipher Rescue Chain prepares detailed forensic reports that clearly document the flow of assets, ensuring that every movement is verifiable and defensible. These reports form the foundation for recovery actions, enabling efficient engagement with platforms that can facilitate fund retrieval. Proven Outcomes Backed by Data The effectiveness of Cipher Rescue Chain is reflected in real-world outcomes. From 2023 to 2025, Cipher Rescue Chain has achieved partial or full recovery in 98% of accepted cases where funds reached identifiable centralized platforms and engagement began within the first 90 days. Only 35% of inquiries are accepted, ensuring that Cipher Rescue Chain focuses exclusively on cases with realistic recovery potential. Among those accepted cases, 62% result in full recovery and 24% in partial recovery. Successful cases are typically resolved within an average timeframe of 14 to 45 days, demonstrating the efficiency of Cipher Rescue Chain’s forensic and recovery process. Global Reach and Complex Case Handling Crypto crime is borderless, and so is the work of Cipher Rescue Chain. With multi-million-dollar recoveries completed across five continents, Cipher Rescue Chain operates at a truly global scale. Each case handled by Cipher Rescue Chain reflects a combination of technical expertise, investigative precision, and strategic execution. Whether funds move across multiple blockchains or jurisdictions, Cipher Rescue Chain maintains a consistent focus on traceability and recovery. Why Blockchain Forensics Changes the Outcome The belief that stolen crypto is unrecoverable is outdated. Blockchain forensics, when executed at the highest level, transforms transparency into a powerful recovery tool. Cipher Rescue Chain exemplifies this by turning complex transaction data into successful recovery outcomes. By combining cross-chain tracing, rapid response, and data-driven investigation, Cipher Rescue Chain stands as the global benchmark for crypto recovery. Every traced transaction, every reconstructed path, and every recovered asset reinforces the same conclusion: with the right forensic expertise, recovery is not only possible—it is highly achievable.

18 hours, 24 minutes

Understanding Blockchain Forensics:

by joelwest689＠gmail.com

By combining cross-chain tracing, rapid response, and data-driven investigation, Cipher Rescue Chain stands as the global benchmark for crypto recovery. Every traced transaction, every reconstructed path, and every recovered asset reinforces the same conclusion: with the right forensic expertise, recovery is not only possible—it is highly achievable.

18 hours, 25 minutes

Re: [PATCH v5 0/2] dma-buf: heaps: system: add an option to allocate explicitly shared/decrypted memory

by Marek Szyprowski

On 25.03.2026 20:23, Jiri Pirko wrote: > From: Jiri Pirko <jiri(a)nvidia.com> > > Confidential computing (CoCo) VMs/guests, such as AMD SEV and Intel TDX, > run with private/encrypted memory which creates a challenge > for devices that do not support DMA to it (no TDISP support). > > For kernel-only DMA operations, swiotlb bounce buffering provides a > transparent solution by copying data through shared memory. > However, the only way to get this memory into userspace is via the DMA > API's dma_alloc_pages()/dma_mmap_pages() type interfaces which limits > the use of the memory to a single DMA device, and is incompatible with > pin_user_pages(). > > These limitations are particularly problematic for the RDMA subsystem > which makes heavy use of pin_user_pages() and expects flexible memory > usage between many different DMA devices. > > This patch series enables userspace to explicitly request shared > (decrypted) memory allocations from new dma-buf system_cc_shared heap. > Userspace can mmap this memory and pass the dma-buf fd to other > existing importers such as RDMA or DRM devices to access the > memory. The DMA API is improved to allow the dma heap exporter to DMA > map the shared memory to each importing device. > > Based on dma-mapping-for-next e7442a68cd1ee797b585f045d348781e9c0dde0d I would like to merge this to dma-mapping-next, but I feel a bit uncomfortable with my lack of knowledge about CoCo and friends. Could those who know a bit more about it provide some Reviewed-by tags? Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland

18 hours, 32 minutes

Re: [PATCH v5 2/2] dma-buf: heaps: system: add system_cc_shared heap for explicitly shared memory

by T.J. Mercier

On Wed, Mar 25, 2026 at 12:23 PM Jiri Pirko <jiri(a)resnulli.us> wrote: > > From: Jiri Pirko <jiri(a)nvidia.com> > > Add a new "system_cc_shared" dma-buf heap to allow userspace to > allocate shared (decrypted) memory for confidential computing (CoCo) > VMs. > > On CoCo VMs, guest memory is private by default. The hardware uses an > encryption bit in page table entries (C-bit on AMD SEV, "shared" bit on > Intel TDX) to control whether a given memory access is private or > shared. The kernel's direct map is set up as private, > so pages returned by alloc_pages() are private in the direct map > by default. To make this memory usable for devices that do not support > DMA to private memory (no TDISP support), it has to be explicitly > shared. A couple of things are needed to properly handle > shared memory for the dma-buf use case: > > - set_memory_decrypted() on the direct map after allocation: > Besides clearing the encryption bit in the direct map PTEs, this > also notifies the hypervisor about the page state change. On free, > the inverse set_memory_encrypted() must be called before returning > pages to the allocator. If re-encryption fails, pages > are intentionally leaked to prevent shared memory from being > reused as private. > > - pgprot_decrypted() for userspace and kernel virtual mappings: > Any new mapping of the shared pages, be it to userspace via > mmap or to kernel vmalloc space via vmap, creates PTEs independent > of the direct map. These must also have the encryption bit cleared, > otherwise accesses through them would see encrypted (garbage) data. > > - DMA_ATTR_CC_SHARED for DMA mapping: > Since the pages are already shared, the DMA API needs to be > informed via DMA_ATTR_CC_SHARED so it can map them correctly > as unencrypted for device access. > > On non-CoCo VMs, the system_cc_shared heap is not registered > to prevent misuse by userspace that does not understand > the security implications of explicitly shared memory. > > Signed-off-by: Jiri Pirko <jiri(a)nvidia.com> Reviewed-by: T.J. Mercier <tjmercier(a)google.com>

18 hours, 32 minutes

Re: (subset) [PATCH v9 0/7] Rust bindings for gem shmem

by Miguel Ojeda

On Thu, Mar 26, 2026 at 2:15 AM Danilo Krummrich <dakr(a)kernel.org> wrote: > > @Lyude, Alice, Miguel: Please have a look at what I came up with below. Sounds fine to me, thanks! - Regarding the enabled unstable feature: looks good -- it will go away this cycle anyway, so we may get a conflict, but that is fine. - Regarding the `&raw`, that sounds also good. I see you did it similarly to how I did it for `bitmap.rs` -- thanks! (And for future reference, the `bitmap.rs` one was 1.92 instead of 1.82 because that one was for unions, while this one is https://blog.rust-lang.org/2024/10/17/Rust-1.82.0/#safely-addressing-unsafe…). - Regarding the `expect(unused)` -- using `cfg_attr` is fine since it is a simple case, but if it becomes a big issue, then of course please feel free to use `allow` (you already know this, but in case it helps others: I wrote some considerations about this at https://docs.kernel.org/rust/coding-guidelines.html#lints). Cheers, Miguel

1 day, 4 hours

[PATCH v3 0/8] dma-buf: heaps: Turn heaps into modules

by Maxime Ripard

Hi, The recent introduction of heaps in the optee driver [1] made possible the creation of heaps as modules. It's generally a good idea if possible, including for the already existing system and CMA heaps. The system one is pretty trivial, the CMA one is a bit more involved, especially since we have a call from kernel/dma/contiguous.c to the CMA heap code. This was solved by turning the logic around and making the CMA heap call into the contiguous DMA code. Let me know what you think, Maxime 1: https://lore.kernel.org/dri-devel/20250911135007.1275833-4-jens.wiklander@l… Signed-off-by: Maxime Ripard <mripard(a)kernel.org> --- Changes in v3: - Squashed cma_get_name and cma_alloc/release patches - Fixed typo in Export dev_get_cma_area commit title - Fixed compilation failure with DMA_CMA but not OF_RESERVED_MEM - Link to v2: https://lore.kernel.org/r/20260227-dma-buf-heaps-as-modules-v2-0-454aee7e06… Changes in v2: - Collect tags - Don't export dma_contiguous_default_area anymore, but export dev_get_cma_area instead - Mentioned that heap modules can't be removed - Link to v1: https://lore.kernel.org/r/20260225-dma-buf-heaps-as-modules-v1-0-2109225a09… --- Maxime Ripard (8): dma: contiguous: Turn heap registration logic around dma: contiguous: Make dev_get_cma_area() a proper function dma: contiguous: Make dma_contiguous_default_area static dma: contiguous: Export dev_get_cma_area() mm: cma: Export cma_alloc(), cma_release() and cma_get_name() dma-buf: heaps: Export mem_accounting parameter dma-buf: heaps: cma: Turn the heap into a module dma-buf: heaps: system: Turn the heap into a module drivers/dma-buf/dma-heap.c | 1 + drivers/dma-buf/heaps/Kconfig | 4 ++-- drivers/dma-buf/heaps/cma_heap.c | 21 +++++---------------- drivers/dma-buf/heaps/system_heap.c | 5 +++++ include/linux/dma-map-ops.h | 18 ++++++++++-------- kernel/dma/contiguous.c | 37 ++++++++++++++++++++++++++++++++++--- mm/cma.c | 3 +++ 7 files changed, 60 insertions(+), 29 deletions(-) --- base-commit: 499a718536dc0e1c1d1b6211847207d58acd9916 change-id: 20260225-dma-buf-heaps-as-modules-1034b3ec9f2a Best regards, -- Maxime Ripard <mripard(a)kernel.org>

1 day, 5 hours

Re: [PATCH v4 00/12] drm/amdgpu: use all SDMA instances for TTM clears and moves

by Christian König

Finally coming back to this patch set here. Fell free to add Reviewed-by: Christian König <christian.koenig(a)amd.com> to the first two patches as well and then please start pushing the patches to amd-staging-drm-next. I probably need to go over the last patches once more, but I think it would be better to have the first few upstream first. Regards, Christian. On 2/3/26 11:22, Pierre-Eric Pelloux-Prayer wrote: > The drm/ttm patch modifies TTM to support multiple contexts for the pipelined moves. > > Then amdgpu/ttm is updated to express dependencies between jobs explicitely, > instead of relying on the ordering of execution guaranteed by the use of a single > instance. > With all of this in place, we can use multiple entities, with each having access > to the available SDMA instances. > > This rework also gives the opportunity to merge the clear functions into a single > one and to optimize a bit GART usage. > > Since v3 some patches have been already reviewed and merged separately: > - https://lists.freedesktop.org/archives/amd-gfx/2026-January/137747.html > - https://gitlab.freedesktop.org/drm/kernel/-/commit/ddf055b80a544d6f36f77be5… > This version depend on them. > > v3: https://lists.freedesktop.org/archives/dri-devel/2025-November/537830.html > > Pierre-Eric Pelloux-Prayer (12): > drm/amdgpu: allocate clear entities dynamically > drm/amdgpu: allocate move entities dynamically > drm/amdgpu: round robin through clear_entities in amdgpu_fill_buffer > drm/amdgpu: use TTM_NUM_MOVE_FENCES when reserving fences > drm/amdgpu: use multiple entities in amdgpu_move_blit > drm/amdgpu: pass all the sdma scheds to amdgpu_mman > drm/amdgpu: only use working sdma schedulers for ttm > drm/amdgpu: create multiple clear/move ttm entities > drm/amdgpu: give ttm entities access to all the sdma scheds > drm/amdgpu: get rid of amdgpu_ttm_clear_buffer > drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_ttm_clear_buffer > drm/amdgpu: split amdgpu_ttm_set_buffer_funcs_status in 2 funcs > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 4 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 329 ++++++++++-------- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 29 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 6 +- > drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 13 +- > drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +- > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +- > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 15 +- > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 +- > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 11 +- > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 14 +- > drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 +- > drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 5 +- > drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 12 +- > drivers/gpu/drm/amd/amdgpu/si_dma.c | 12 +- > drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 5 +- > drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 3 +- > .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +- > .../drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 6 +- > 23 files changed, 300 insertions(+), 243 deletions(-) >

2 days, 1 hour

[PATCH] dma-buf/dma_fence_array: remove unused functionality

by Christian König

Amdgpu was the only user of the signal on any feature and we dropped that use case recently, so we can remove that functionality again. This allows to simplfy the dma_fence_array code a lot and saves us from the need to install a callback on all fences at the same time. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/dma-fence-array.c | 133 +++++++----------- drivers/dma-buf/dma-fence-unwrap.c | 3 +- drivers/dma-buf/dma-resv.c | 3 +- drivers/dma-buf/st-dma-fence-unwrap.c | 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +- drivers/gpu/drm/xe/xe_sync.c | 2 +- drivers/gpu/drm/xe/xe_vm.c | 4 +- include/linux/dma-fence-array.h | 28 +--- 8 files changed, 63 insertions(+), 115 deletions(-) diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma-fence-array.c index 089f69469524..0d54bf2e47ba 100644 --- a/drivers/dma-buf/dma-fence-array.c +++ b/drivers/dma-buf/dma-fence-array.c @@ -42,97 +42,71 @@ static void dma_fence_array_clear_pending_error(struct dma_fence_array *array) cmpxchg(&array->base.error, PENDING_ERROR, 0); } -static void irq_dma_fence_array_work(struct irq_work *wrk) +static void dma_fence_array_cb_func(struct dma_fence *f, + struct dma_fence_cb *cb) { - struct dma_fence_array *array = container_of(wrk, typeof(*array), work); + struct dma_fence_array *array = + container_of(cb, struct dma_fence_array, callback); - dma_fence_array_clear_pending_error(array); - - dma_fence_signal(&array->base); - dma_fence_put(&array->base); + irq_work_queue(&array->work); } -static void dma_fence_array_cb_func(struct dma_fence *f, - struct dma_fence_cb *cb) +static void irq_dma_fence_array_work(struct irq_work *wrk) { - struct dma_fence_array_cb *array_cb = - container_of(cb, struct dma_fence_array_cb, cb); - struct dma_fence_array *array = array_cb->array; + struct dma_fence_array *array = container_of(wrk, typeof(*array), work); - dma_fence_array_set_pending_error(array, f->error); + while (array->num_pending--) { + struct dma_fence *f = array->fences[array->num_pending]; - if (atomic_dec_and_test(&array->num_pending)) - irq_work_queue(&array->work); - else - dma_fence_put(&array->base); + if (!dma_fence_add_callback(f, &array->callback, + dma_fence_array_cb_func)) + return; + + dma_fence_array_set_pending_error(array, f->error); + } + + dma_fence_signal(&array->base); + dma_fence_put(&array->base); } static bool dma_fence_array_enable_signaling(struct dma_fence *fence) { struct dma_fence_array *array = to_dma_fence_array(fence); - struct dma_fence_array_cb *cb = array->callbacks; - unsigned i; - - for (i = 0; i < array->num_fences; ++i) { - cb[i].array = array; - /* - * As we may report that the fence is signaled before all - * callbacks are complete, we need to take an additional - * reference count on the array so that we do not free it too - * early. The core fence handling will only hold the reference - * until we signal the array as complete (but that is now - * insufficient). - */ - dma_fence_get(&array->base); - if (dma_fence_add_callback(array->fences[i], &cb[i].cb, - dma_fence_array_cb_func)) { - int error = array->fences[i]->error; - - dma_fence_array_set_pending_error(array, error); - dma_fence_put(&array->base); - if (atomic_dec_and_test(&array->num_pending)) { - dma_fence_array_clear_pending_error(array); - return false; - } - } - } + /* + * As we may report that the fence is signaled before all + * callbacks are complete, we need to take an additional + * reference count on the array so that we do not free it too + * early. The core fence handling will only hold the reference + * until we signal the array as complete (but that is now + * insufficient). + */ + dma_fence_get(&array->base); + irq_dma_fence_array_work(&array->work); return true; } static bool dma_fence_array_signaled(struct dma_fence *fence) { struct dma_fence_array *array = to_dma_fence_array(fence); - int num_pending; + int num_pending, error = 0; unsigned int i; /* - * We need to read num_pending before checking the enable_signal bit - * to avoid racing with the enable_signaling() implementation, which - * might decrement the counter, and cause a partial check. - * atomic_read_acquire() pairs with atomic_dec_and_test() in - * dma_fence_array_enable_signaling() - * - * The !--num_pending check is here to account for the any_signaled case - * if we race with enable_signaling(), that means the !num_pending check - * in the is_signalling_enabled branch might be outdated (num_pending - * might have been decremented), but that's fine. The user will get the - * right value when testing again later. + * Reading num_pending is just an optimization, it is perfectly + * acceptable to have a stale value for it. */ - num_pending = atomic_read_acquire(&array->num_pending); - if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &array->base.flags)) { - if (num_pending <= 0) - goto signal; - return false; - } + num_pending = READ_ONCE(array->num_pending); + for (i = 0; i < num_pending; ++i) { + struct dma_fence *f = array->fences[i]; - for (i = 0; i < array->num_fences; ++i) { - if (dma_fence_is_signaled(array->fences[i]) && !--num_pending) - goto signal; - } - return false; + if (!dma_fence_is_signaled(f)) + return false; -signal: + if (!error) + error = f->error; + } + dma_fence_array_set_pending_error(array, error); dma_fence_array_clear_pending_error(array); return true; } @@ -171,15 +145,12 @@ EXPORT_SYMBOL(dma_fence_array_ops); /** * dma_fence_array_alloc - Allocate a custom fence array - * @num_fences: [in] number of fences to add in the array * * Return dma fence array on success, NULL on failure */ -struct dma_fence_array *dma_fence_array_alloc(int num_fences) +struct dma_fence_array *dma_fence_array_alloc(void) { - struct dma_fence_array *array; - - return kzalloc_flex(*array, callbacks, num_fences); + return kzalloc_obj(struct dma_fence_array); } EXPORT_SYMBOL(dma_fence_array_alloc); @@ -190,21 +161,22 @@ EXPORT_SYMBOL(dma_fence_array_alloc); * @fences: [in] array containing the fences * @context: [in] fence context to use * @seqno: [in] sequence number to use - * @signal_on_any: [in] signal on any fence in the array * * Implementation of @dma_fence_array_create without allocation. Useful to init * a preallocated dma fence array in the path of reclaim or dma fence signaling. */ void dma_fence_array_init(struct dma_fence_array *array, int num_fences, struct dma_fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) + u64 context, unsigned seqno) { static struct lock_class_key dma_fence_array_lock_key; WARN_ON(!num_fences || !fences); array->num_fences = num_fences; + array->num_pending = num_fences; + array->fences = fences; + array->base.error = PENDING_ERROR; dma_fence_init(&array->base, &dma_fence_array_ops, NULL, context, seqno); @@ -222,11 +194,6 @@ void dma_fence_array_init(struct dma_fence_array *array, */ lockdep_set_class(&array->base.inline_lock, &dma_fence_array_lock_key); - atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); - array->fences = fences; - - array->base.error = PENDING_ERROR; - /* * dma_fence_array objects should never contain any other fence * containers or otherwise we run into recursion and potential kernel @@ -249,7 +216,6 @@ EXPORT_SYMBOL(dma_fence_array_init); * @fences: [in] array containing the fences * @context: [in] fence context to use * @seqno: [in] sequence number to use - * @signal_on_any: [in] signal on any fence in the array * * Allocate a dma_fence_array object and initialize the base fence with * dma_fence_init(). @@ -264,17 +230,16 @@ EXPORT_SYMBOL(dma_fence_array_init); */ struct dma_fence_array *dma_fence_array_create(int num_fences, struct dma_fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) + u64 context, unsigned seqno) { struct dma_fence_array *array; - array = dma_fence_array_alloc(num_fences); + array = dma_fence_array_alloc(); if (!array) return NULL; dma_fence_array_init(array, num_fences, fences, - context, seqno, signal_on_any); + context, seqno); return array; } diff --git a/drivers/dma-buf/dma-fence-unwrap.c b/drivers/dma-buf/dma-fence-unwrap.c index 07fe9bf45aea..53bb40e70b27 100644 --- a/drivers/dma-buf/dma-fence-unwrap.c +++ b/drivers/dma-buf/dma-fence-unwrap.c @@ -180,8 +180,7 @@ struct dma_fence *__dma_fence_unwrap_merge(unsigned int num_fences, if (count > 1) { result = dma_fence_array_create(count, array, - dma_fence_context_alloc(1), - 1, false); + dma_fence_context_alloc(1), 1); if (!result) { for (i = 0; i < count; i++) dma_fence_put(array[i]); diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index ce9e6c04897f..39a92d9f2413 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -648,8 +648,7 @@ int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, } array = dma_fence_array_create(count, fences, - dma_fence_context_alloc(1), - 1, false); + dma_fence_context_alloc(1), 1); if (!array) { while (count--) dma_fence_put(fences[count]); diff --git a/drivers/dma-buf/st-dma-fence-unwrap.c b/drivers/dma-buf/st-dma-fence-unwrap.c index 9c74195f47fd..45413666970e 100644 --- a/drivers/dma-buf/st-dma-fence-unwrap.c +++ b/drivers/dma-buf/st-dma-fence-unwrap.c @@ -65,7 +65,7 @@ static struct dma_fence *mock_array(unsigned int num_fences, ...) array = dma_fence_array_create(num_fences, fences, dma_fence_context_alloc(1), - 1, false); + 1); if (!array) goto error_free; return &array->base; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index e7918f896a26..1ac91a46d87f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -3203,8 +3203,7 @@ eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd) fence_array = dma_fence_array_create(eb->num_batches, fences, eb->context->parallel.fence_context, - eb->context->parallel.seqno++, - false); + eb->context->parallel.seqno++); if (!fence_array) { kfree(fences); return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c index 24d6d9af20d6..37866768d64c 100644 --- a/drivers/gpu/drm/xe/xe_sync.c +++ b/drivers/gpu/drm/xe/xe_sync.c @@ -376,7 +376,7 @@ xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync, xe_assert(vm->xe, current_fence == num_fence); cf = dma_fence_array_create(num_fence, fences, dma_fence_context_alloc(1), - 1, false); + 1); if (!cf) goto err_out; diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 548b0769b3ef..b916a9d90104 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3196,7 +3196,7 @@ static struct dma_fence *ops_execute(struct xe_vm *vm, goto err_trace; } - cf = dma_fence_array_alloc(n_fence); + cf = dma_fence_array_alloc(); if (!cf) { fence = ERR_PTR(-ENOMEM); goto err_out; @@ -3240,7 +3240,7 @@ static struct dma_fence *ops_execute(struct xe_vm *vm, xe_assert(vm->xe, current_fence == n_fence); dma_fence_array_init(cf, n_fence, fences, dma_fence_context_alloc(1), - 1, false); + 1); fence = &cf->base; for_each_tile(tile, vm->xe, id) { diff --git a/include/linux/dma-fence-array.h b/include/linux/dma-fence-array.h index 370b3d2bba37..3ee55c0e2fa4 100644 --- a/include/linux/dma-fence-array.h +++ b/include/linux/dma-fence-array.h @@ -15,16 +15,6 @@ #include <linux/dma-fence.h> #include <linux/irq_work.h> -/** - * struct dma_fence_array_cb - callback helper for fence array - * @cb: fence callback structure for signaling - * @array: reference to the parent fence array object - */ -struct dma_fence_array_cb { - struct dma_fence_cb cb; - struct dma_fence_array *array; -}; - /** * struct dma_fence_array - fence to represent an array of fences * @base: fence base class @@ -33,18 +23,17 @@ struct dma_fence_array_cb { * @num_pending: fences in the array still pending * @fences: array of the fences * @work: internal irq_work function - * @callbacks: array of callback helpers + * @callback: callback structure for signaling */ struct dma_fence_array { struct dma_fence base; - unsigned num_fences; - atomic_t num_pending; + unsigned int num_fences; + unsigned int num_pending; struct dma_fence **fences; struct irq_work work; - - struct dma_fence_array_cb callbacks[] __counted_by(num_fences); + struct dma_fence_cb callback; }; /** @@ -78,16 +67,13 @@ to_dma_fence_array(struct dma_fence *fence) for (index = 0, fence = dma_fence_array_first(head); fence; \ ++(index), fence = dma_fence_array_next(head, index)) -struct dma_fence_array *dma_fence_array_alloc(int num_fences); +struct dma_fence_array *dma_fence_array_alloc(void); void dma_fence_array_init(struct dma_fence_array *array, int num_fences, struct dma_fence **fences, - u64 context, unsigned seqno, - bool signal_on_any); - + u64 context, unsigned seqno); struct dma_fence_array *dma_fence_array_create(int num_fences, struct dma_fence **fences, - u64 context, unsigned seqno, - bool signal_on_any); + u64 context, unsigned seqno); bool dma_fence_match_context(struct dma_fence *fence, u64 context); -- 2.43.0

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