Il 12/03/24 15:50, Alexandre Mergnat ha scritto:

On 26/02/2024 16:25, AngeloGioacchino Del Regno wrote:

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+    if (enable) { +        /* set gpio mosi mode */ +        regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, GPIO_MODE2_CLEAR_ALL); +        regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET, GPIO8_MODE_SET_AUD_CLK_MOSI | +                                  GPIO9_MODE_SET_AUD_DAT_MOSI0 | +                                  GPIO10_MODE_SET_AUD_DAT_MOSI1 | +                                  GPIO11_MODE_SET_AUD_SYNC_MOSI);

Are you sure that you need to write to MODE2_SET *and* to MODE2?!

This is downstream code and these registers aren't in my documentation. I've removed the MODE2_SET write and test the audio: it's still working.

So I will keep the spurious write removed for v2. :)

Usually, MediaTek registers are laid out like "REG" being R/legacy-W and "REG_SET/CLR" for setting and clearing bits in "REG" internally, and that might account for internal latencies and such.

Can you please try to remove the MODE2 write instead of the MODE2_SET one and check if that works?

You're already using the SETCLR way when manipulating registers in here, so I would confidently expect that to work.

Cheers, Angelo