Linaro-uefi

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811 discussions

[PATCH v2 11/24] D03/D05: Change to access EEPROM data bytewise

by Heyi Guo

We would get incorrect data when accessing multiple bytes at one time and going across EEPROM page boundary, so we change to access EEPROM by single byte each time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li <lipeicong(a)huawei.com> --- .../D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c index 994ed6a..31fd333 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -110,6 +110,7 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) UINT16 I2cOffset; UINT16 crc16; NIC_MAC_ADDRESS stMacDesc = {0}; + UINT32 Index; Status = I2CInit(0, EEPROM_I2C_PORT, Normal); if (EFI_ERROR(Status)) @@ -124,9 +125,10 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); - if (EFI_ERROR(Status)) - { + for (Index = 0; Index < sizeof(NIC_MAC_ADDRESS); Index++) { + Status |= I2CRead(&stI2cDev, I2cOffset + Index, 1, (UINT8 *)&stMacDesc + Index); + } + if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); return Status; } @@ -150,6 +152,7 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) EFI_STATUS Status; UINT16 I2cOffset; NIC_MAC_ADDRESS stMacDesc = {0}; + UINTN Index; stMacDesc.MacLen = MAC_ADDR_LEN; @@ -170,9 +173,11 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); - if (EFI_ERROR(Status)) - { + for (Index = 0; Index < sizeof(NIC_MAC_ADDRESS); Index++) { + Status |= I2CWrite(&stI2cDev, I2cOffset + Index, 1, (UINT8 *)&stMacDesc + Index); + } + + if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); return Status; } -- 1.9.1

8 years, 2 months

[PATCH v2 11/24] D03/D05: Change to access EEPROM data bytewise

by Heyi Guo

From: Peicong Li <lipeicong(a)huawei.com> We would get incorrect data when accessing multiple bytes at one time and going across EEPROM page boundary, so we change to access EEPROM by single byte each time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li <lipeicong(a)huawei.com> --- .../D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c index 994ed6a..31fd333 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -110,6 +110,7 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) UINT16 I2cOffset; UINT16 crc16; NIC_MAC_ADDRESS stMacDesc = {0}; + UINT32 Index; Status = I2CInit(0, EEPROM_I2C_PORT, Normal); if (EFI_ERROR(Status)) @@ -124,9 +125,10 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); - if (EFI_ERROR(Status)) - { + for (Index = 0; Index < sizeof(NIC_MAC_ADDRESS); Index++) { + Status |= I2CRead(&stI2cDev, I2cOffset + Index, 1, (UINT8 *)&stMacDesc + Index); + } + if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); return Status; } @@ -150,6 +152,7 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) EFI_STATUS Status; UINT16 I2cOffset; NIC_MAC_ADDRESS stMacDesc = {0}; + UINTN Index; stMacDesc.MacLen = MAC_ADDR_LEN; @@ -170,9 +173,11 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); - if (EFI_ERROR(Status)) - { + for (Index = 0; Index < sizeof(NIC_MAC_ADDRESS); Index++) { + Status |= I2CWrite(&stI2cDev, I2cOffset + Index, 1, (UINT8 *)&stMacDesc + Index); + } + + if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); return Status; } -- 1.9.1

8 years, 2 months

[PATCH 0/2] Add support for SoftIron Overdrive 1000

by Alan Ott

Add support for the SoftIron Overdrive 1000. This requires first moving FdtDxe/ from OverdriveBoard/ to Drivers/, so that it can be used by OverdriveBoard/ and Overdrive1000Board/ Alan. Alan Ott (2): Platforms/AMD/Styx: Move FdtDxe/ from OverdriveBoard/ to Drivers/ Platforms/AMD/Styx: Add configuration for Overdrive 1000 .../FdtDxe/BdsLinuxFdt.c | 0 .../{OverdriveBoard => Drivers}/FdtDxe/FdtDxe.c | 0 .../{OverdriveBoard => Drivers}/FdtDxe/FdtDxe.h | 0 .../{OverdriveBoard => Drivers}/FdtDxe/FdtDxe.inf | 0 .../FdtDxe/LinuxLoader.h | 0 .../FdtDxe/LinuxLoaderHelper.c | 0 .../Overdrive1000Board/Binary/PreUefiFirmware.bin | Bin 0 -> 401408 bytes .../FdtBlob/styx-overdrive1000.dtb | Bin 0 -> 8329 bytes .../FdtBlob/styx-overdrive1000.dts | 458 +++++++++++++ .../Styx/Overdrive1000Board/Overdrive1000Board.dsc | 734 +++++++++++++++++++++ .../Styx/Overdrive1000Board/Overdrive1000Board.fdf | 412 ++++++++++++ .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 +- .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 2 +- 13 files changed, 1606 insertions(+), 2 deletions(-) rename Platforms/AMD/Styx/{OverdriveBoard => Drivers}/FdtDxe/BdsLinuxFdt.c (100%) rename Platforms/AMD/Styx/{OverdriveBoard => Drivers}/FdtDxe/FdtDxe.c (100%) rename Platforms/AMD/Styx/{OverdriveBoard => Drivers}/FdtDxe/FdtDxe.h (100%) rename Platforms/AMD/Styx/{OverdriveBoard => Drivers}/FdtDxe/FdtDxe.inf (100%) rename Platforms/AMD/Styx/{OverdriveBoard => Drivers}/FdtDxe/LinuxLoader.h (100%) rename Platforms/AMD/Styx/{OverdriveBoard => Drivers}/FdtDxe/LinuxLoaderHelper.c (100%) create mode 100644 Platforms/AMD/Styx/Overdrive1000Board/Binary/PreUefiFirmware.bin create mode 100644 Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb create mode 100644 Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts create mode 100644 Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc create mode 100644 Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.fdf -- 2.5.0

8 years, 2 months

Best baseline for new platform support?

by Scott Telford

Hi folks, I'm looking at getting TianoCore/EDK2 running on a simulated SoC platform using a Cortex-A53 processor, which should bear some resemblance to SBSA. I'm a bit confused, though, about which EDK2 repo/branch would be best to use as a baseline at the moment? Also, I'm guessing OpenPlatformPkg is the way to go now for new ARM platform-specific code, rather than ArmPlatformPkg? Cheers, Scott.

8 years, 2 months

[PATCH v2 0/5] Armada 7040 UTMI, Reset and I2c fix

by Marcin Wojtas

Hi, Jan has prepared v2 version of the patchset, which fixes minor issues pointed in UTMI library. Also Reset functionality was re-implemented in order to use ResetRuntimeDxe. The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog v1->v2: * Change ResetSystem driver to implementation of EfiResetSystemLibrary - Use EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf - Adjust naming properly - Replace 4K in size and 4K aligned memory allocation to 64K in size and 64K aligned * Sort #include entries and PCDs * Change ResetLib documentation and UTMI-related files format to DOS (remove CheckPatch errors) * UTMI - Remove debug info prints improperly marked as "DEBUG_ERROR" - Break up long prints (over 80 characters), but unbreak format strings * Rebase on top of the newest opp baseline Bartosz Szczepanek (2): Platforms/Marvell: Add MvResetSystemLib Platforms/Marvell: Enable MvResetSystemLib for A70x0 platform Jan Dąbroś (3): Drivers/I2c: Fix enumaration of I2c devices Platforms/Marvell: Add UtmiPhyLib Platforms/Marvell: Enable UtmiPhyLib for Armada70x0 Platforms Documentation/Marvell/PortingGuide/Reset.txt | 7 + Documentation/Marvell/PortingGuide/Utmi.txt | 35 ++ Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 13 +- Platforms/Marvell/Armada/Armada.dsc.inc | 3 +- Platforms/Marvell/Armada/Armada70x0.dsc | 11 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 2 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 1 + Platforms/Marvell/Include/Library/UtmiPhyLib.h | 43 +++ .../Library/ResetSystemLib/MvResetSystemLib.c | 153 +++++++++ .../Library/ResetSystemLib/MvResetSystemLib.inf | 58 ++++ Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 353 +++++++++++++++++++++ Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 110 +++++++ .../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 64 ++++ Platforms/Marvell/Marvell.dec | 11 + 14 files changed, 857 insertions(+), 7 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/Reset.txt create mode 100644 Documentation/Marvell/PortingGuide/Utmi.txt create mode 100644 Platforms/Marvell/Include/Library/UtmiPhyLib.h create mode 100644 Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.c create mode 100644 Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.inf create mode 100644 Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c create mode 100644 Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h create mode 100644 Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf -- 1.8.3.1

8 years, 2 months

[PATCH 1/1] ArmPlatformPkg/ArmTrustZone: Add support for specifying Subregions to be disabled

by Bhupesh Sharma

ARM TZASC-380 IP provides a mechanism to split memory regions being protected via it into eight equal-sized sub-regions, with a bit setting allowing the corresponding subregion to be disabled. Several NXP/FSL SoCs support the TZASC-380 IP block and allow the DDR connected via the TZASC to be partitioned into regions having different security settings. This patch enables this support and can be used for SoCs which support such partition of DDR regions. Details of the 'subregion_disable' register can be viewed here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0431c/CJABCF… Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)nxp.com> Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- .../Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c | 21 ++++++++++++++------- ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c | 5 +++-- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c index 6fa0774..d358d65 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c @@ -72,18 +72,21 @@ ArmPlatformSecTrustzoneInit ( // NOR Flash 0 non secure (BootMon) TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED, ARM_VE_SMB_NOR0_BASE,0, - TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, + 0); // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin) if (PcdGetBool (PcdTrustzoneSupport) == TRUE) { //Note: Your OS Kernel must be aware of the secure regions before to enable this region TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED, ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0, - TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, + 0); } else { TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED, ARM_VE_SMB_NOR1_BASE,0, - TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, + 0); } // Base of SRAM. Only half of SRAM in Non Secure world @@ -92,22 +95,26 @@ ArmPlatformSecTrustzoneInit ( //Note: Your OS Kernel must be aware of the secure regions before to enable this region TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED, ARM_VE_SMB_SRAM_BASE,0, - TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW, + 0); } else { TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED, ARM_VE_SMB_SRAM_BASE,0, - TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, + 0); } // Memory Mapped Peripherals. All in non secure world TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED, ARM_VE_SMB_PERIPH_BASE,0, - TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, + 0); // MotherBoard Peripherals and On-chip peripherals. TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED, ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0, - TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW); + TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW, + 0); } /** diff --git a/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c b/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c index 070c0dc..5cd41ef 100644 --- a/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c +++ b/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c @@ -87,7 +87,8 @@ TZASCSetRegion ( IN UINTN LowAddress, IN UINTN HighAddress, IN UINTN Size, - IN UINTN Security + IN UINTN Security, + IN UINTN SubregionDisableMask ) { UINT32* Region; @@ -100,7 +101,7 @@ TZASCSetRegion ( MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000); MmioWrite32((UINTN)(Region+1), HighAddress); - MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1)); + MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((SubregionDisableMask & 0xFF) << 8) | ((Size & 0x3F) << 1) | (Enabled & 0x1)); return EFI_SUCCESS; } -- 1.9.1

8 years, 2 months

[PATCH 01/11] D02/D03: WA to fix timer interrupt issue

by Heyi Guo

Timer interrupt cannot be reported after EDK2 commit 7989300, for GIC on D02/D03 is not fully ARM GIC compliant. The issue has been fixed on newer chips so we use a WA for D02 and D03 only. On D02 and D03, IRQ will be latched in GIC logic except virutal timer interrupt IRQ #27, so we change to use virtual timer instead of physical in UEFI. Change-Id: Ie8eca7e4dea45a3a318ee32783ddaa15363065e2 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo(a)linaro.org> --- Platforms/Hisilicon/D02/Pv660D02.dsc | 10 ++++++++-- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- Platforms/Hisilicon/D03/D03.dsc | 10 +++++++++- Platforms/Hisilicon/D03/D03.fdf | 2 +- 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index d025bdd..4b4a0b7 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -72,6 +72,13 @@ PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf +## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when +## input signal is deasserted, except for virtual timer interrupt IRQ #27. So +## we choose to use virutal timer instead of physical one as a workaround. +## This library instance is to override the one in Pv660.dsc.inc. +[LibraryClasses.AARCH64] + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf + [LibraryClasses.common.SEC] ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf @@ -341,8 +348,7 @@ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - #ArmPkg/Drivers/TimerDxe/TimerDxe - ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index 69be1f1..fa0dc2d 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -195,7 +195,7 @@ READ_LOCK_STATUS = TRUE #INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf # diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 83a18b1..ccf16a2 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -81,6 +81,14 @@ LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf + +## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when +## input signal is deasserted, except for virtual timer interrupt IRQ #27. So +## we choose to use virutal timer instead of physical one as a workaround. +## This library instance is to override the one in Pv660.dsc.inc. +[LibraryClasses.AARCH64] + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf + [LibraryClasses.common.SEC] ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf @@ -396,7 +404,7 @@ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 8144151..8ba3bd0 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -187,7 +187,7 @@ READ_LOCK_STATUS = TRUE # Simple TextIn/TextOut for UEFI Terminal INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf -- 1.9.1

8 years, 2 months

[PATCH 00/11] Enable Hisilicon new platform "D05"

by Heyi Guo

Hisilicon new platform D05 will be pushed to Linaro Reference Platform 16.12 release, and these patches are to enable Hisilicon D05 in OPP. Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-05-d05 Heyi Guo (9): D02/D03: WA to fix timer interrupt issue Hisilicon/Hi1610/PCIe: Added performance tuning Hisilicon/Hi1610/PCIe: Remove lane reversal code Hisilicon/PCIe: Add support for Hi1616 Hisilicon/I2CLib: Extend to support Hi1616 Hisilicon: Update some headers file to support Hi1616 Platforms/Hisilicon: Add D05 support UpdateFdtDxe: Add GenericMemTestProtocol dependency Platforms/Hisilicon: Add D05 binary files Peicong Li (2): D03/D05: Change to access EEPROM data one by one Serdes: Modify get Serdes parameter function interface .../Library/Hi1616Serdes/Hi1616SerdesLib.inf | 48 + .../Library/Hi1616Serdes/Hi1616SerdesLib.lib | Bin 0 -> 707246 bytes .../PlatformSysCtrlLibHi1616.inf | 55 + .../PlatformSysCtrlLibHi1616.lib | Bin 0 -> 358602 bytes .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 299 +++++ .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni | 22 + .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 59 + .../HisiAcpiPlatformDxe/AcpiPlatformExtra.uni | 20 + .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 127 ++ .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 214 +++- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 + .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 9 +- .../Type09/MiscSystemSlotDesignationFunction.c | 3 +- .../Drivers/UpdateFdtDxe/UpdateFdtDxe.inf | 4 +- .../Hi1610/Drivers/PcieInit1610/PcieInit.c | 61 +- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 5 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 410 ++++++- .../Hi1610/Drivers/PcieInit1610/PcieKernelApi.h | 4 +- Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 58 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 651 +++++++++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 127 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 64 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 129 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 +++++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 37 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1234 ++++++++++++++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 58 + .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 460 ++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 436 +++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 247 ++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 136 +++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 96 ++ .../Hi1616/D05AcpiTables/Hi1616Platform.h | 48 + .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 282 +++++ Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 78 ++ Chips/Hisilicon/HisiPkg.dec | 117 +- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 19 +- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 60 +- Chips/Hisilicon/Include/Library/I2CLib.h | 2 +- Chips/Hisilicon/Include/Library/OemMiscLib.h | 1 + Chips/Hisilicon/Include/Library/PlatformPciLib.h | 136 ++- .../Hisilicon/Include/Library/PlatformSysCtrlLib.h | 6 + Chips/Hisilicon/Include/PlatformArch.h | 2 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + Chips/Hisilicon/Library/I2CLib/I2CLib.c | 54 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- .../Drivers/GetInfoFromBmc/GetInfoFromBmc.depex | Bin 0 -> 2 bytes .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 0 -> 19552 bytes .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf | 26 + .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex | Bin 0 -> 2 bytes .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 0 -> 25696 bytes .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf | 28 + .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 0 -> 22528 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf | 32 + .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 0 -> 23136 bytes .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex | Bin 0 -> 2 bytes .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf | 27 + .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex | Bin 0 -> 2 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 0 -> 15968 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf | 27 + .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf | 29 + .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf | 28 + .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf | 27 + .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf | 27 + .../Binary/D05/Drivers/OhciDxe/NativeOhci.efi | Bin 0 -> 48000 bytes .../Binary/D05/Drivers/OhciDxe/OhciDxe.inf | 26 + .../ReportPciePlugDidVidToBmc.depex | Bin 0 -> 2 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 0 -> 21536 bytes .../ReportPciePlugDidVidToBmc.inf | 25 + .../Binary/D05/Drivers/SFC/SFCDriver.depex | Bin 0 -> 2 bytes .../Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi | Bin 0 -> 262144 bytes .../Binary/D05/Drivers/SFC/SfcDxeDriver.inf | 29 + .../Binary/D05/Drivers/Sas/SasDriverDxe.efi | Bin 0 -> 210400 bytes .../Binary/D05/Drivers/Sas/SasDxeDriver.inf | 28 + .../D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 0 -> 35904 bytes .../Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf | 32 + .../TransferSmbiosInfo/TransSmbiosInfo.depex | Bin 0 -> 2 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 0 -> 16576 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf | 26 + Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi | Bin 0 -> 141344 bytes Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf | 32 + .../D05/Library/FdtUpdateLib/FdtUpdateLib.inf | 51 + .../D05/Library/FdtUpdateLib/FdtUpdateLib.lib | Bin 0 -> 108418 bytes .../Library/OemAddressMapD05/OemAddressMapD05.inf | 44 + .../Library/OemAddressMapD05/OemAddressMapD05.lib | Bin 0 -> 42136 bytes .../Binary/D05/MemoryInitPei/MemoryInit.efi | Bin 0 -> 268416 bytes .../Binary/D05/MemoryInitPei/MemoryInitPeim.inf | 33 + Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv | Bin 0 -> 262144 bytes Platforms/Hisilicon/Binary/D05/bl1.bin | Bin 0 -> 12296 bytes Platforms/Hisilicon/Binary/D05/fip.bin | Bin 0 -> 41493 bytes .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 2 +- .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 118 +- Platforms/Hisilicon/D02/Pv660D02.dsc | 10 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- Platforms/Hisilicon/D03/D03.dsc | 12 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 18 +- .../OemNicConfig2PHi1610/OemNicConfig2P.inf | 1 + .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 2 +- .../D03/Library/PlatformPciLib/PlatformPciLib.c | 33 +- .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 118 +- Platforms/Hisilicon/D05/D05.dsc | 672 +++++++++++ Platforms/Hisilicon/D05/D05.fdf | 354 ++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 106 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 55 + .../Library/OemMemConfigLibD05/BoardFeatureD05.c | 58 + .../OemMemConfigLibD05/OemMemConfigLibD05.c | 65 ++ .../OemMemConfigLibD05/OemMemConfigLibD05.inf | 44 + .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 226 ++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 + .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 127 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 56 + .../Hisilicon/D05/Library/OemNicLib/OemNicLib.c | 66 ++ .../Hisilicon/D05/Library/OemNicLib/OemNicLib.inf | 39 + .../D05/Library/PlatformPciLib/PlatformPciLib.c | 270 +++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 +++ 126 files changed, 9518 insertions(+), 165 deletions(-) create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.lib create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/NativeOhci.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.lib create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.lib create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInit.efi create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv create mode 100644 Platforms/Hisilicon/Binary/D05/bl1.bin create mode 100644 Platforms/Hisilicon/Binary/D05/fip.bin create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.c create mode 100644 Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf -- 1.9.1

8 years, 2 months

[PATCH] D02/D03: WA to fix timer interrupt issue

by Heyi Guo

8 years, 2 months

[PATCH] platforms.config: Add Hisilicon d05 platform

by Heyi Guo

Signed-off-by: Heyi Guo <heyi.guo(a)linaro.org> --- platforms.config | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/platforms.config b/platforms.config index ece954f..eb15141 100644 --- a/platforms.config +++ b/platforms.config @@ -226,6 +226,13 @@ ARCH=AARCH64 UEFI_BIN=D03.fd UEFI_IMAGE_DIR=D03 +[d05] +LONGNAME=HiSilicon D05 +DSC=OpenPlatformPkg/Platforms/Hisilicon/D05/D05.dsc +ARCH=AARCH64 +UEFI_BIN=D05.fd +UEFI_IMAGE_DIR=D05 + [armada70x0] LONGNAME=Marvell Armada 70x0 DSC=OpenPlatformPkg/Platforms/Marvell/Armada/Armada70x0.dsc -- 2.9.3

8 years, 2 months

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