CoreSight November 2018

coresight@lists.linaro.org

9 participants
15 discussions

by Mike Leach

Patch release incorporating build dependency updates from pull request #14 Minor change to auto-fdo document. No functionality changes. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

6 years

[PATCH v1 0/5] perf cs-etm: Correct packets handling

by Leo Yan

perf cs-etm module converts decoder elements to packets and then we have more context crossing packets to generate synthenize samples, finally perf tool can faciliate samples for statistics and report the results. This patch series is to address several issues found related with packets handling and samples generation when worked firstly on branch sample flags support for Arm CoreSight trace data, so this patch series also is dependency for another patch series for sample flags. The first two patches are mainly to fix issues in cs_etm__flush(): Patch 0001 corrects packets swapping in cs_etm__flush() and this can fix the wrong branch sample caused by the missed packets swapping; patch 0002 is to fix the wrong samples generation with stale packets at the end of every trace buffer. Patch 0003 is used to support NO_SYNC packet, otherwise the trace decoding cannot reflect the tracing discontinuity caused by NO_SYNC packet. Patch 0004/0005 has been published in the patch series 'perf cs-etm: Add support for sample flags' before but at this time I move them into this patch series due these two patches are more relative with packets handling. Patch 0004 is used to generate branch sample for exception packets; and patch 0005 is to track the exception number. This patch series is applied on the acme's perf core branch [1] with the latest commit f1d23afaf677 ("perf bpf: Reduce the hardcoded .max_entries for pid_maps") and has one prerequisite from Rob's patch 'perf: Support for Arm A32/T32 instruction sets in CoreSight trace' [2]. With applying the dependency patch, this patch series has been tested for branch samples dumping with below command on Juno board: # perf script -F,-time,+ip,+sym,+dso,+addr,+symoff -k vmlinux [1] https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/log/?h=perf/… [2] http://archive.armlinux.org.uk/lurker/message/20181109.091126.9d69489d.en.h… Leo Yan (5): perf cs-etm: Correct packets swapping in cs_etm__flush() perf cs-etm: Avoid stale branch samples when flush packet perf cs-etm: Support for NO_SYNC packet perf cs-etm: Generate branch sample for exception packet perf cs-etm: Track exception number tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 91 ++++++++++++++++++++++--- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 11 +-- tools/perf/util/cs-etm.c | 65 +++++++++++++++--- 3 files changed, 146 insertions(+), 21 deletions(-) -- 2.7.4

6 years

[PATCH v2 0/2] perf cs-etm: Add support for sample flags

by Leo Yan

This patch seris adds support for sample flags so can facilitate perf to print sample flags for branch instruction. The patch 0001 is to set branch instruction flags in packet, this patch has the core code in this series to set flags according to the decoding element type, and also based on the elements including instruction type, subtype and condition flag to help making decision to set flags value. The patch 0002 is to support sample flags by copying the flags value from packet structure to sample structure, and it includes three fixing up for TRACE_ON/TRACE_OFF and exception packets. The patch series is based on OpenCSD v0.10.0 and Rob's patch 'perf: Support for Arm A32/T32 instruction sets in CoreSight trace' also is prerequisite to support A32/T32 ISAs. This patch series is applied on the acme's perf core branch [1] with the latest commit f1d23afaf677 ("perf bpf: Reduce the hardcoded .max_entries for pid_maps") and has two prerequisites: 1) It's dependent on Rob's patch 'perf: Support for Arm A32/T32 instruction sets in CoreSight trace' [2]; 2) It's dependent on another patch series 'perf cs-etm: Correct packets handling' [3]. After applying the dependency patches and this patch series, we can verify sample flags with below command: # perf script -F,-time,+flags,+ip,+sym,+dso,+addr,+symoff -k vmlinux Changes from v1: * Moved exception packets handling patches into patch series 'perf cs-etm: Correct packets handling'. * Added sample flags fixing up for TRACE_OFF packet. * Created a new function which is used to maintain flags fixing up. [1] https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/log/?h=perf/… [2] http://archive.armlinux.org.uk/lurker/message/20181109.091126.9d69489d.en.h… [3] http://archive.armlinux.org.uk/lurker/message/20181111.045938.782b378b.en.h… Leo Yan (2): perf cs-etm: Set branch instruction flags in packet perf cs-etm: Add support sample flags tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 168 ++++++++++++++++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 43 +++++- 3 files changed, 210 insertions(+), 2 deletions(-) -- 2.7.4

6 years

[RFC PATCH v2 0/3] Update AMBA driver for enhanced component ID spec

by Mike Leach

The latest ARM CoreSight specification updates the component identification requirements for all components attached to an AMBA bus. (ARM IHI 0029E) This specification defines bits 11:8 in the ComponentID (CID) value as the device class. Identification requirements now depend on this class. Class 0xF: Traditional components identified by Peripheral ID (PID) only. Class 0x9: CoreSight components may be identified by a Universal Component Identifier (UCI) consisting of the PID plus CoreSight DevType and DevArch values. Current and future ARM CoreSight IP will now use the same PID for components on the same function - e.g. the ETM, CTI, PMU and Debug elements associated with a core. The first core to use this UCI method is the A35, which currently has binding entries in the ETMv4 driver. This patchset prepares for the addition of the upcoming CTI driver, which will need to correctly bind with A35 and future hardware, while overcoming the limitation of binding by PID alone, which cannot now work. The patchset updates the current AMBA Identification mechanism, which was already differentiating between 0xF and 0x9 CIDs, to add additional UCI compliant tests for the for the 0x9 device class. Additional UCI structures are provided and added to the ETMv4 driver as appropriate. An additional test patch is provided to test the mechanism on the DB410C 96boards platform. This is not intended to be upstreamed. Changes since v1: 1) simplification of amba_lookup function & other minor fixes per suzuki suggestions. 2) remove spurious whitespace changes. 3) extended devarch and devarch mask values in etmv4 UCI to include architect. Mike Leach (3): drivers: amba: Updates to component identification for driver matching. coresight: etmv4: Update ID register table to add UCI support amba: coresight: Driver test for new CoreSight UCI matching arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++ drivers/amba/bus.c | 60 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-etm4x.c | 21 ++++++- include/linux/amba/bus.h | 32 ++++++++++ 4 files changed, 112 insertions(+), 10 deletions(-) -- 2.19.1

6 years

[RFC PATCH 0/3] Update AMBA driver for enhanced component ID spec

by Mike Leach

The latest ARM CoreSight specification updates the component identification requirements for all components attached to an AMBA bus. (ARM IHI 0029E) This specification defines bits 11:8 in the ComponentID (CID) value as the device class. Identification requirements now depend on this class. Class 0xF: Traditional components identified by Peripheral ID (PID) only. Class 0x9: CoreSight components may be identified by a Universal Component Identifier (UCI) consisting of the PID plus CoreSight DevType and DevArch values. Current and future ARM CoreSight IP will now use the same PID for components on the same function - e.g. the ETM, CTI, PMU and Debug elements associated with a core. The first core to use this UCI method is the A35, which currently has binding entries in the ETMv4 driver. This patchset prepares for the addition of the upcoming CTI driver, which will need to correctly bind with A35 and future hardware, while overcoming the limitation of binding by PID alone, which cannot now work. The patchset updates the current AMBA Identification mechanism, which was already differentiating between 0xF and 0x9 CIDs, to add additional UCI compliant tests for the for the 0x9 device class. Additional UCI structures are provided and added to the ETMv4 driver as appropriate. An additional test patch is provided to test the mechanism on the DB410C 96boards platform. This is not intended to be upstreamed. Mike Leach (3): drivers: amba: Updates to component identification for driver matching. coresight: etmv4: Update ID register table to add UCI support amba: coresight: Driver test for new CoreSight UCI matching arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++ drivers/amba/bus.c | 59 +++++++++++++++++-- drivers/hwtracing/coresight/coresight-etm4x.c | 27 +++++++-- include/linux/amba/bus.h | 33 +++++++++++ 4 files changed, 119 insertions(+), 9 deletions(-) -- 2.19.1

6 years, 1 month

[PATCH 4.19 112/205] perf cs-etm: Correct CPU mode for samples

by Greg Kroah-Hartman

4.19-stable review patch. If anyone has any objections, please let me know. ------------------ From: Leo Yan <leo.yan(a)linaro.org> commit d6c9c05fe1eb4b213b183d8a1e79416256dc833a upstream. Since commit edeb0c90df35 ("perf tools: Stop fallbacking to kallsyms for vdso symbols lookup"), the kernel address cannot be properly parsed to kernel symbol with command 'perf script -k vmlinux'. The reason is CoreSight samples is always to set CPU mode as PERF_RECORD_MISC_USER, thus it fails to find corresponding map/dso in below flows: process_sample_event() `-> machine__resolve() `-> thread__find_map(thread, sample->cpumode, sample->ip, al); In this flow it needs to pass argument 'sample->cpumode' to tell what's the CPU mode, before it always passed PERF_RECORD_MISC_USER but without any failure until the commit edeb0c90df35 ("perf tools: Stop fallbacking to kallsyms for vdso symbols lookup") has been merged. The reason is even with the wrong CPU mode the function thread__find_map() firstly fails to find map but it will rollback to find kernel map for vdso symbols lookup. In the latest code it has removed the fallback code, thus if CPU mode is PERF_RECORD_MISC_USER then it cannot find map anymore with kernel address. This patch is to correct samples CPU mode setting, it creates a new helper function cs_etm__cpu_mode() to tell what's the CPU mode based on the address with the info from machine structure; this patch has a bit extension to check not only kernel and user mode, but also check for host/guest and hypervisor mode. Finally this patch uses the function in instruction and branch samples and also apply in cs_etm__mem_access() for a minor polishing. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> Cc: Adrian Hunter <adrian.hunter(a)intel.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: David Miller <davem(a)davemloft.net> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: stable(a)kernel.org # v4.19 Link: http://lkml.kernel.org/r/1540883908-17018-1-git-send-email-leo.yan@linaro.o… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> --- tools/perf/util/cs-etm.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -244,6 +244,27 @@ static void cs_etm__free(struct perf_ses zfree(&aux); } +static u8 cs_etm__cpu_mode(struct cs_etm_queue *etmq, u64 address) +{ + struct machine *machine; + + machine = etmq->etm->machine; + + if (address >= etmq->etm->kernel_start) { + if (machine__is_host(machine)) + return PERF_RECORD_MISC_KERNEL; + else + return PERF_RECORD_MISC_GUEST_KERNEL; + } else { + if (machine__is_host(machine)) + return PERF_RECORD_MISC_USER; + else if (perf_guest) + return PERF_RECORD_MISC_GUEST_USER; + else + return PERF_RECORD_MISC_HYPERVISOR; + } +} + static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u64 address, size_t size, u8 *buffer) { @@ -258,10 +279,7 @@ static u32 cs_etm__mem_access(struct cs_ return -1; machine = etmq->etm->machine; - if (address >= etmq->etm->kernel_start) - cpumode = PERF_RECORD_MISC_KERNEL; - else - cpumode = PERF_RECORD_MISC_USER; + cpumode = cs_etm__cpu_mode(etmq, address); thread = etmq->thread; if (!thread) { @@ -653,7 +671,7 @@ static int cs_etm__synth_instruction_sam struct perf_sample sample = {.ip = 0,}; event->sample.header.type = PERF_RECORD_SAMPLE; - event->sample.header.misc = PERF_RECORD_MISC_USER; + event->sample.header.misc = cs_etm__cpu_mode(etmq, addr); event->sample.header.size = sizeof(struct perf_event_header); sample.ip = addr; @@ -665,7 +683,7 @@ static int cs_etm__synth_instruction_sam sample.cpu = etmq->packet->cpu; sample.flags = 0; sample.insn_len = 1; - sample.cpumode = event->header.misc; + sample.cpumode = event->sample.header.misc; if (etm->synth_opts.last_branch) { cs_etm__copy_last_branch_rb(etmq); @@ -706,12 +724,15 @@ static int cs_etm__synth_branch_sample(s u64 nr; struct branch_entry entries; } dummy_bs; + u64 ip; + + ip = cs_etm__last_executed_instr(etmq->prev_packet); event->sample.header.type = PERF_RECORD_SAMPLE; - event->sample.header.misc = PERF_RECORD_MISC_USER; + event->sample.header.misc = cs_etm__cpu_mode(etmq, ip); event->sample.header.size = sizeof(struct perf_event_header); - sample.ip = cs_etm__last_executed_instr(etmq->prev_packet); + sample.ip = ip; sample.pid = etmq->pid; sample.tid = etmq->tid; sample.addr = cs_etm__first_executed_instr(etmq->packet); @@ -720,7 +741,7 @@ static int cs_etm__synth_branch_sample(s sample.period = 1; sample.cpu = etmq->packet->cpu; sample.flags = 0; - sample.cpumode = PERF_RECORD_MISC_USER; + sample.cpumode = event->sample.header.misc; /* * perf report cannot handle events without a branch stack

6 years, 1 month

Patch "perf cs-etm: Correct CPU mode for samples" has been added to the 4.19-stable tree

by gregkh＠linuxfoundation.org

This is a note to let you know that I've just added the patch titled perf cs-etm: Correct CPU mode for samples to the 4.19-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum… The filename of the patch is: perf-cs-etm-correct-cpu-mode-for-samples.patch and it can be found in the queue-4.19 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable(a)vger.kernel.org> know about it. >From d6c9c05fe1eb4b213b183d8a1e79416256dc833a Mon Sep 17 00:00:00 2001 From: Leo Yan <leo.yan(a)linaro.org> Date: Tue, 30 Oct 2018 15:18:28 +0800 Subject: perf cs-etm: Correct CPU mode for samples From: Leo Yan <leo.yan(a)linaro.org> commit d6c9c05fe1eb4b213b183d8a1e79416256dc833a upstream. Since commit edeb0c90df35 ("perf tools: Stop fallbacking to kallsyms for vdso symbols lookup"), the kernel address cannot be properly parsed to kernel symbol with command 'perf script -k vmlinux'. The reason is CoreSight samples is always to set CPU mode as PERF_RECORD_MISC_USER, thus it fails to find corresponding map/dso in below flows: process_sample_event() `-> machine__resolve() `-> thread__find_map(thread, sample->cpumode, sample->ip, al); In this flow it needs to pass argument 'sample->cpumode' to tell what's the CPU mode, before it always passed PERF_RECORD_MISC_USER but without any failure until the commit edeb0c90df35 ("perf tools: Stop fallbacking to kallsyms for vdso symbols lookup") has been merged. The reason is even with the wrong CPU mode the function thread__find_map() firstly fails to find map but it will rollback to find kernel map for vdso symbols lookup. In the latest code it has removed the fallback code, thus if CPU mode is PERF_RECORD_MISC_USER then it cannot find map anymore with kernel address. This patch is to correct samples CPU mode setting, it creates a new helper function cs_etm__cpu_mode() to tell what's the CPU mode based on the address with the info from machine structure; this patch has a bit extension to check not only kernel and user mode, but also check for host/guest and hypervisor mode. Finally this patch uses the function in instruction and branch samples and also apply in cs_etm__mem_access() for a minor polishing. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> Cc: Adrian Hunter <adrian.hunter(a)intel.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: David Miller <davem(a)davemloft.net> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: stable(a)kernel.org # v4.19 Link: http://lkml.kernel.org/r/1540883908-17018-1-git-send-email-leo.yan@linaro.o… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> --- tools/perf/util/cs-etm.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -244,6 +244,27 @@ static void cs_etm__free(struct perf_ses zfree(&aux); } +static u8 cs_etm__cpu_mode(struct cs_etm_queue *etmq, u64 address) +{ + struct machine *machine; + + machine = etmq->etm->machine; + + if (address >= etmq->etm->kernel_start) { + if (machine__is_host(machine)) + return PERF_RECORD_MISC_KERNEL; + else + return PERF_RECORD_MISC_GUEST_KERNEL; + } else { + if (machine__is_host(machine)) + return PERF_RECORD_MISC_USER; + else if (perf_guest) + return PERF_RECORD_MISC_GUEST_USER; + else + return PERF_RECORD_MISC_HYPERVISOR; + } +} + static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u64 address, size_t size, u8 *buffer) { @@ -258,10 +279,7 @@ static u32 cs_etm__mem_access(struct cs_ return -1; machine = etmq->etm->machine; - if (address >= etmq->etm->kernel_start) - cpumode = PERF_RECORD_MISC_KERNEL; - else - cpumode = PERF_RECORD_MISC_USER; + cpumode = cs_etm__cpu_mode(etmq, address); thread = etmq->thread; if (!thread) { @@ -653,7 +671,7 @@ static int cs_etm__synth_instruction_sam struct perf_sample sample = {.ip = 0,}; event->sample.header.type = PERF_RECORD_SAMPLE; - event->sample.header.misc = PERF_RECORD_MISC_USER; + event->sample.header.misc = cs_etm__cpu_mode(etmq, addr); event->sample.header.size = sizeof(struct perf_event_header); sample.ip = addr; @@ -665,7 +683,7 @@ static int cs_etm__synth_instruction_sam sample.cpu = etmq->packet->cpu; sample.flags = 0; sample.insn_len = 1; - sample.cpumode = event->header.misc; + sample.cpumode = event->sample.header.misc; if (etm->synth_opts.last_branch) { cs_etm__copy_last_branch_rb(etmq); @@ -706,12 +724,15 @@ static int cs_etm__synth_branch_sample(s u64 nr; struct branch_entry entries; } dummy_bs; + u64 ip; + + ip = cs_etm__last_executed_instr(etmq->prev_packet); event->sample.header.type = PERF_RECORD_SAMPLE; - event->sample.header.misc = PERF_RECORD_MISC_USER; + event->sample.header.misc = cs_etm__cpu_mode(etmq, ip); event->sample.header.size = sizeof(struct perf_event_header); - sample.ip = cs_etm__last_executed_instr(etmq->prev_packet); + sample.ip = ip; sample.pid = etmq->pid; sample.tid = etmq->tid; sample.addr = cs_etm__first_executed_instr(etmq->packet); @@ -720,7 +741,7 @@ static int cs_etm__synth_branch_sample(s sample.period = 1; sample.cpu = etmq->packet->cpu; sample.flags = 0; - sample.cpumode = PERF_RECORD_MISC_USER; + sample.cpumode = event->sample.header.misc; /* * perf report cannot handle events without a branch stack Patches currently in stable-queue which might be from leo.yan(a)linaro.org are queue-4.19/perf-cs-etm-correct-cpu-mode-for-samples.patch queue-4.19/perf-intel-pt-bts-calculate-cpumode-for-synthesized-samples.patch queue-4.19/perf-intel-pt-insert-callchain-context-into-synthesized-callchains.patch

6 years, 1 month

[PATCH 0/3] perf tools: Add support for ETMv3/PTM1.1 decoding

by Mathieu Poirier

This set adds support for ETMv3/PTM1.1 trace decoding. The work has been tested on TC2 and ST-Microelectronics' mp157c-ev1 board and applies cleanly on 4.20-rc2 and Acme's perf/core branch [1]. *** Before this set *** $ perf report --stdio # To display the perf.data header info, please use --header/--header-only options. # DCD_ETMV4_0020 : 0x0003 (OCSD_ERR_NOT_INIT) [Component not initialised.]; No decoder configuration information DCD_ETMV4_0022 : 0x0003 (OCSD_ERR_NOT_INIT) [Component not initialised.]; No decoder configuration information DCD_ETMV4_0024 : 0x0003 (OCSD_ERR_NOT_INIT) [Component not initialised.]; No decoder configuration information DCD_ETMV4_0020 : 0x0003 (OCSD_ERR_NOT_INIT) [Component not initialised.]; No decoder configuration information DCD_ETMV4_0022 : 0x0003 (OCSD_ERR_NOT_INIT) [Component not initialised.]; No decoder configuration information DCD_ETMV4_0024 : 0x0003 (OCSD_ERR_NOT_INIT) [Component not initialised.]; No decoder configuration information Warning: AUX data lost 2 times out of 2! Error: The perf.data file has no samples! *** After this set *** [...] # Samples: 12K of event 'branches' # Event count (approx.): 12049 # # Children Self Command Shared Object Symbol # ........ ........ ....... ................ ....................... # 28.18% 28.18% uname libc-2.19.so [.] strcmp 9.13% 9.13% uname libc-2.19.so [.] strcpy 7.87% 7.87% uname libc-2.19.so [.] strnlen 5.58% 5.58% uname libc-2.19.so [.] strlen 2.24% 2.24% uname libc-2.19.so [.] __rawmemchr 1.91% 1.91% uname ld-2.19.so [.] 0x000000000001156a 1.49% 1.49% uname libc-2.19.so [.] __argz_stringify 1.46% 1.46% uname libc-2.19.so [.] malloc 0.96% 0.96% uname libc-2.19.so [.] 0x0000000000054770 0.91% 0.91% uname libc-2.19.so [.] 0x000000000002430a 0.85% 0.85% uname ld-2.19.so [.] 0x0000000000007244 0.83% 0.83% uname libc-2.19.so [.] __stpcpy [...] Regards, Mathieu [1]. "6909b0a13389 perf stat: Use perf_evsel__is_clocki() for clock events" Mathieu Poirier (3): perf tools: Add configuration for ETMv3 trace protocol perf tools: Add support for ETMv3 trace decoding perf tools: Add support for PTMv1.1 decoding tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 31 +++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 9 +++ tools/perf/util/cs-etm.c | 73 ++++++++++++++++++++----- 3 files changed, 99 insertions(+), 14 deletions(-) -- 2.7.4

6 years, 1 month

[PATCH v2 0/4] coresight: Fix miscellaneous problems with CLAIM tags

by Mathieu Poirier

This set addresses problems observed with the CLAIM tag feature. The first patch adds support for CLAIM tags to the ETB10 drivers. The remaining 3 patches deal with properly handling the tags on ETF and ETM3x devices. Regards, Mathieu Changes since V1: * Added Suzuki's review tags to patch 1 and 2. * Addressed ordering issued in ETM3x enable/disable functions (Leo Yan) Mathieu Poirier (4): coresight: etb10: Add support for CLAIM tag coresight: etf: Release CLAIM tag after disabling the HW coresight: etm3x: Deal with CLAIM tag before and after accessing HW coresight: etm3x: Release CLAIM tag when operated from perf drivers/hwtracing/coresight/coresight-etb10.c | 23 +++++++++++++++++------ drivers/hwtracing/coresight/coresight-etm3x.c | 17 +++++++++-------- drivers/hwtracing/coresight/coresight-tmc-etf.c | 2 +- 3 files changed, 27 insertions(+), 15 deletions(-) -- 2.7.4

6 years, 1 month

[PATCH v5] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

by Robert Walker

This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2 or 4 byte instruction size, so the conversion between addresses and instruction counts requires extra information from the trace decoder, requiring version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker <robert.walker(a)arm.com> --- Changes since v4: Formatting of comment block tools/build/feature/test-libopencsd.c | 8 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 10 ++++ tools/perf/util/cs-etm.c | 70 +++++++++++-------------- 4 files changed, 78 insertions(+), 39 deletions(-) diff --git a/tools/build/feature/test-libopencsd.c b/tools/build/feature/test-libopencsd.c index 5ff1246..d68eb4f 100644 --- a/tools/build/feature/test-libopencsd.c +++ b/tools/build/feature/test-libopencsd.c @@ -1,6 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 #include <opencsd/c_api/opencsd_c_api.h> +/* + * Check OpenCSD library version is sufficient to provide required features + */ +#define OCSD_MIN_VER ((0 << 16) | (10 << 8) | (0)) +#if !defined(OCSD_VER_NUM) || (OCSD_VER_NUM < OCSD_MIN_VER) +#error "OpenCSD >= 0.10.0 is required" +#endif + int main(void) { (void)ocsd_get_version(); diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 938def6..5efb616 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -263,9 +263,12 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder) decoder->tail = 0; decoder->packet_count = 0; for (i = 0; i < MAX_BUFFER; i++) { + decoder->packet_buffer[i].isa = CS_ETM_ISA_UNKNOWN; decoder->packet_buffer[i].start_addr = CS_ETM_INVAL_ADDR; decoder->packet_buffer[i].end_addr = CS_ETM_INVAL_ADDR; + decoder->packet_buffer[i].instr_count = 0; decoder->packet_buffer[i].last_instr_taken_branch = false; + decoder->packet_buffer[i].last_instr_size = 0; decoder->packet_buffer[i].exc = false; decoder->packet_buffer[i].exc_ret = false; decoder->packet_buffer[i].cpu = INT_MIN; @@ -294,11 +297,15 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_count++; decoder->packet_buffer[et].sample_type = sample_type; + decoder->packet_buffer[et].isa = CS_ETM_ISA_UNKNOWN; decoder->packet_buffer[et].exc = false; decoder->packet_buffer[et].exc_ret = false; decoder->packet_buffer[et].cpu = *((int *)inode->priv); decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR; decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR; + decoder->packet_buffer[et].instr_count = 0; + decoder->packet_buffer[et].last_instr_taken_branch = false; + decoder->packet_buffer[et].last_instr_size = 0; if (decoder->packet_count == MAX_BUFFER - 1) return OCSD_RESP_WAIT; @@ -321,8 +328,28 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder, packet = &decoder->packet_buffer[decoder->tail]; + switch (elem->isa) { + case ocsd_isa_aarch64: + packet->isa = CS_ETM_ISA_A64; + break; + case ocsd_isa_arm: + packet->isa = CS_ETM_ISA_A32; + break; + case ocsd_isa_thumb2: + packet->isa = CS_ETM_ISA_T32; + break; + case ocsd_isa_tee: + case ocsd_isa_jazelle: + case ocsd_isa_custom: + case ocsd_isa_unknown: + default: + packet->isa = CS_ETM_ISA_UNKNOWN; + } + packet->start_addr = elem->st_addr; packet->end_addr = elem->en_addr; + packet->instr_count = elem->num_instr_range; + switch (elem->last_i_type) { case OCSD_INSTR_BR: case OCSD_INSTR_BR_INDIRECT: @@ -336,6 +363,8 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder, break; } + packet->last_instr_size = elem->last_instr_sz; + return ret; } diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index 612b575..9351bd1 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -28,11 +28,21 @@ enum cs_etm_sample_type { CS_ETM_TRACE_ON = 1 << 1, }; +enum cs_etm_isa { + CS_ETM_ISA_UNKNOWN, + CS_ETM_ISA_A64, + CS_ETM_ISA_A32, + CS_ETM_ISA_T32, +}; + struct cs_etm_packet { enum cs_etm_sample_type sample_type; + enum cs_etm_isa isa; u64 start_addr; u64 end_addr; + u32 instr_count; u8 last_instr_taken_branch; + u8 last_instr_size; u8 exc; u8 exc_ret; int cpu; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 73430b7..48ad217 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -31,14 +31,6 @@ #define MAX_TIMESTAMP (~0ULL) -/* - * A64 instructions are always 4 bytes - * - * Only A64 is supported, so can use this constant for converting between - * addresses and instruction counts, calculting offsets etc - */ -#define A64_INSTR_SIZE 4 - struct cs_etm_auxtrace { struct auxtrace auxtrace; struct auxtrace_queues queues; @@ -510,21 +502,17 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq) etmq->last_branch_rb->nr = 0; } -static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet) -{ - /* Returns 0 for the CS_ETM_TRACE_ON packet */ - if (packet->sample_type == CS_ETM_TRACE_ON) - return 0; +static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq, + u64 addr) { + u8 instrBytes[2]; + cs_etm__mem_access(etmq, addr, ARRAY_SIZE(instrBytes), instrBytes); /* - * The packet records the execution range with an exclusive end address - * - * A64 instructions are constant size, so the last executed - * instruction is A64_INSTR_SIZE before the end address - * Will need to do instruction level decode for T32 instructions as - * they can be variable size (not yet supported). + * T32 instruction size is indicated by bits[15:11] of the first + * 16-bit word of the instruction: 0b11101, 0b11110 and 0b11111 + * denote a 32-bit instruction. */ - return packet->end_addr - A64_INSTR_SIZE; + return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2; } static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet) @@ -536,27 +524,32 @@ static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet) return packet->start_addr; } -static inline u64 cs_etm__instr_count(const struct cs_etm_packet *packet) +static inline +u64 cs_etm__last_executed_instr(const struct cs_etm_packet *packet) { - /* - * Only A64 instructions are currently supported, so can get - * instruction count by dividing. - * Will need to do instruction level decode for T32 instructions as - * they can be variable size (not yet supported). - */ - return (packet->end_addr - packet->start_addr) / A64_INSTR_SIZE; + /* Returns 0 for the CS_ETM_TRACE_ON packet */ + if (packet->sample_type == CS_ETM_TRACE_ON) + return 0; + + return packet->end_addr - packet->last_instr_size; } -static inline u64 cs_etm__instr_addr(const struct cs_etm_packet *packet, +static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq, + const struct cs_etm_packet *packet, u64 offset) { - /* - * Only A64 instructions are currently supported, so can get - * instruction address by muliplying. - * Will need to do instruction level decode for T32 instructions as - * they can be variable size (not yet supported). - */ - return packet->start_addr + offset * A64_INSTR_SIZE; + if (packet->isa == CS_ETM_ISA_T32) { + u64 addr = packet->start_addr; + + while (offset > 0) { + addr += cs_etm__t32_instr_size(etmq, addr); + offset--; + } + return addr; + } + + /* Assume a 4 byte instruction size (A32/A64) */ + return packet->start_addr + offset * 4; } static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq) @@ -888,9 +881,8 @@ static int cs_etm__sample(struct cs_etm_queue *etmq) struct cs_etm_auxtrace *etm = etmq->etm; struct cs_etm_packet *tmp; int ret; - u64 instrs_executed; + u64 instrs_executed = etmq->packet->instr_count; - instrs_executed = cs_etm__instr_count(etmq->packet); etmq->period_instructions += instrs_executed; /* @@ -920,7 +912,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq) * executed, but PC has not advanced to next instruction) */ u64 offset = (instrs_executed - instrs_over - 1); - u64 addr = cs_etm__instr_addr(etmq->packet, offset); + u64 addr = cs_etm__instr_addr(etmq, etmq->packet, offset); ret = cs_etm__synth_instruction_sample( etmq, addr, etm->instructions_sample_period); -- 2.7.4

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CoreSight November 2018