The latest ARM CoreSight specification updates the component identification requirements for all components attached to an AMBA bus. (ARM IHI 0029E)
This specification defines bits 11:8 in the ComponentID (CID) value as the device class. Identification requirements now depend on this class. Class 0xF: Traditional components identified by Peripheral ID (PID) only. Class 0x9: CoreSight components may be identified by a Universal Component Identifier (UCI) consisting of the PID plus CoreSight DevType and DevArch values.
Current and future ARM CoreSight IP will now use the same PID for components on the same function - e.g. the ETM, CTI, PMU and Debug elements associated with a core. The first core to use this UCI method is the A35, which currently has binding entries in the ETMv4 driver.
This patchset prepares for the addition of the upcoming CTI driver, which will need to correctly bind with A35 and future hardware, while overcoming the limitation of binding by PID alone, which cannot now work.
The patchset updates the current AMBA Identification mechanism, which was already differentiating between 0xF and 0x9 CIDs, to add additional UCI compliant tests for the for the 0x9 device class.
Additional UCI structures are provided and added to the ETMv4 driver as appropriate.
An additional test patch is provided to test the mechanism on the DB410C 96boards platform. This is not intended to be upstreamed.
Changes since v1: 1) simplification of amba_lookup function & other minor fixes per suzuki suggestions. 2) remove spurious whitespace changes. 3) extended devarch and devarch mask values in etmv4 UCI to include architect.
Mike Leach (3): drivers: amba: Updates to component identification for driver matching. coresight: etmv4: Update ID register table to add UCI support amba: coresight: Driver test for new CoreSight UCI matching
arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++ drivers/amba/bus.c | 60 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-etm4x.c | 21 ++++++- include/linux/amba/bus.h | 32 ++++++++++ 4 files changed, 112 insertions(+), 10 deletions(-)
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org --- drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@
#define to_amba_driver(d) container_of(d, struct amba_driver, drv)
-static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci; + + uci = table->data; + + /* no table data - return match on periphid */ + if (!uci) + return 1; + + if (uci->devarch) { + ret = (dev->uci.devtype == uci->devtype) && + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + } else { + /* devtype only if devarch set to 0 */ + ret = dev->uci.devtype == uci->devtype; + } + return ret; +}
+static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) { - ret = (dev->periphid & table->mask) == table->id; - if (ret) - break; + if (((dev->periphid & table->mask) == table->id) && + ((dev->cid != CORESIGHT_CID) || + (amba_cs_uci_id_match(table, dev)))) + return table; table++; } - - return ret ? table : NULL; + return NULL; }
static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +420,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
+ if (cid == CORESIGHT_CID) { + /* set the base to the start of the last 4k block */ + void __iomem *csbase = tmp + size - 4096; + + dev->uci.devarch = + readl(csbase + UCI_REG_DEVARCH_OFFSET); + dev->uci.devtype = + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; + } + amba_put_disable_pclk(dev);
- if (cid == AMBA_CID || cid == CORESIGHT_CID) + if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid; + dev->cid = cid; + }
if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..ff0ce0587ee9 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d
+/* + * CoreSight Architecture specification updates the ID specification + * for components on the AMBA bus. (ARM IHI 0029E) + * + * Bits 11:8 of the CID are the device class. + * + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support + * at present. + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. + * + * Remaining CID bits stay as 0xb105-00d + */ + +/* + * Class 0x9 components use additional values to form a Unique Component + * Identifier (UCI), where peripheral ID values are identical for different + * components. Passed to the amba bus code from the component driver via + * the amba_id->data pointer. + */ +struct amba_cs_uci_id { + unsigned int devarch; + unsigned int devarch_mask; + unsigned int devtype; +}; + +#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC + struct clk;
struct amba_device { @@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid; + unsigned int cid; + struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; };
Hi Mike,
On 28/11/2018 10:14, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org
drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0;
- struct amba_cs_uci_id *uci;
- uci = table->data;
- /* no table data - return match on periphid */
- if (!uci)
return 1;- if (uci->devarch) {
minor nit: It would be good to check the devarch_mask instead, as we will be covered if at all there is an expected devarch == 0. But the mask can never be 0, if we have something to check.
ret = (dev->uci.devtype == uci->devtype) &&((dev->uci.devarch & uci->devarch_mask) == uci->devarch);- } else {
/* devtype only if devarch set to 0 */ret = dev->uci.devtype == uci->devtype;- }
- return ret;
+} +static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) {
ret = (dev->periphid & table->mask) == table->id;if (ret)break;
if (((dev->periphid & table->mask) == table->id) &&((dev->cid != CORESIGHT_CID) ||(amba_cs_uci_id_match(table, dev))))return table;
- return ret ? table : NULL;
- return NULL; }
static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +420,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
if (cid == CORESIGHT_CID) {/* set the base to the start of the last 4k block */void __iomem *csbase = tmp + size - 4096;dev->uci.devarch =readl(csbase + UCI_REG_DEVARCH_OFFSET);dev->uci.devtype =readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff;}- amba_put_disable_pclk(dev);
if (cid == AMBA_CID || cid == CORESIGHT_CID)
if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid;dev->cid = cid;}if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..ff0ce0587ee9 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d +/*
- CoreSight Architecture specification updates the ID specification
- for components on the AMBA bus. (ARM IHI 0029E)
- Bits 11:8 of the CID are the device class.
I think this should be Bits 15:12 ?
- Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above)
- Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
- Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
- at present.
- Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
- Remaining CID bits stay as 0xb105-00d
- */
+/*
- Class 0x9 components use additional values to form a Unique Component
- Identifier (UCI), where peripheral ID values are identical for different
- components. Passed to the amba bus code from the component driver via
- the amba_id->data pointer.
- */
+struct amba_cs_uci_id {
- unsigned int devarch;
- unsigned int devarch_mask;
- unsigned int devtype;
+};
+#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC
- struct clk;
struct amba_device { @@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid;
- unsigned int cid;
- struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; };
Rest looks fine. With the above addressed,
Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com
On 28/11/2018 10:44, Suzuki K Poulose wrote:
Hi Mike,
On 28/11/2018 10:14, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org
drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci;
+ uci = table->data;
+ /* no table data - return match on periphid */ + if (!uci) + return 1;
Additionally, I see that the DEVARCH defines bit 20 to specify if the register is valid or not. So, do you think we should check if the device has the devarch set and the driver has not provided a matching UCI data and WARN us to detect such problems in the future ?
i.e,
if (!uci) { WARN(dev->uci.devarch & UCI_DEVARCH_PRESENT, "Missing UCI match data for PID: %08x, devarch: %08x\n", dev->periphid, dev->uci.devarch); return 1; }
Cheers Suzuki
HI Suzuki On Wed, 28 Nov 2018 at 10:55, Suzuki K Poulose suzuki.poulose@arm.com wrote:
On 28/11/2018 10:44, Suzuki K Poulose wrote:
Hi Mike,
On 28/11/2018 10:14, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org
drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0;
- struct amba_cs_uci_id *uci;
- uci = table->data;
- /* no table data - return match on periphid */
- if (!uci)
return 1;Additionally, I see that the DEVARCH defines bit 20 to specify if the register is valid or not. So, do you think we should check if the device has the devarch set and the driver has not provided a matching UCI data and WARN us to detect such problems in the future ?
i.e,
if (!uci) { WARN(dev->uci.devarch & UCI_DEVARCH_PRESENT, "Missing UCI match data for PID: %08x, devarch: %08x\n", dev->periphid, dev->uci.devarch); return 1; }
I hadn't considered this, but I am trying to get this patch set not to break existing values. There are currently SoCs that have CS devices that all uniquely identify themselves using the CID / PID values, which also implement DEVARCH. (e.g. DB410 Dragonboard has DEVARCH in the ETMv4, but also has unique PID for the ETMs - so has but does not need UCI for driver binding)
I'd rather avoid a slew of new warnings on stuff that currently works and allow UCI to work when required on newer silicon.
Cheers
Mike
Cheers Suzuki
Hi Suzuki
On Wed, 28 Nov 2018 at 10:44, Suzuki K Poulose suzuki.poulose@arm.com wrote:
Hi Mike,
On 28/11/2018 10:14, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org
drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@
#define to_amba_driver(d) container_of(d, struct amba_driver, drv)
-static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0;
struct amba_cs_uci_id *uci;uci = table->data;/* no table data - return match on periphid */if (!uci)return 1;if (uci->devarch) {minor nit: It would be good to check the devarch_mask instead, as we will be covered if at all there is an expected devarch == 0. But the mask can never be 0, if we have something to check.
There is an expected devarch == 0 - it is defined in the spec as when devarch is not implemented - hence the explicit test here. If there is no devarch - then we can match on devtype alone.
ret = (dev->uci.devtype == uci->devtype) &&((dev->uci.devarch & uci->devarch_mask) == uci->devarch);} else {/* devtype only if devarch set to 0 */ret = dev->uci.devtype == uci->devtype;}return ret;+}
+static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) {
ret = (dev->periphid & table->mask) == table->id;if (ret)break;
if (((dev->periphid & table->mask) == table->id) &&((dev->cid != CORESIGHT_CID) ||(amba_cs_uci_id_match(table, dev))))return table; table++; }
return ret ? table : NULL;
return NULL;}
static int amba_match(struct device *dev, struct device_driver *drv)
@@ -399,10 +420,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
if (cid == CORESIGHT_CID) {/* set the base to the start of the last 4k block */void __iomem *csbase = tmp + size - 4096;dev->uci.devarch =readl(csbase + UCI_REG_DEVARCH_OFFSET);dev->uci.devtype =readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff;}amba_put_disable_pclk(dev);
if (cid == AMBA_CID || cid == CORESIGHT_CID)
if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid;dev->cid = cid;} if (!dev->periphid) ret = -ENODEV;diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..ff0ce0587ee9 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d
+/*
- CoreSight Architecture specification updates the ID specification
- for components on the AMBA bus. (ARM IHI 0029E)
- Bits 11:8 of the CID are the device class.
I think this should be Bits 15:12 ?
It should.
Thanks
Mike
- Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above)
- Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
- Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
- at present.
- Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
- Remaining CID bits stay as 0xb105-00d
- */
+/*
- Class 0x9 components use additional values to form a Unique Component
- Identifier (UCI), where peripheral ID values are identical for different
- components. Passed to the amba bus code from the component driver via
- the amba_id->data pointer.
- */
+struct amba_cs_uci_id {
unsigned int devarch;unsigned int devarch_mask;unsigned int devtype;+};
+#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC
struct clk;
struct amba_device {
@@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid;
unsigned int cid;struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override;Rest looks fine. With the above addressed,
Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com
Hi Suzuki, On Wed, 28 Nov 2018 at 14:54, Mike Leach mike.leach@linaro.org wrote:
Hi Suzuki
On Wed, 28 Nov 2018 at 10:44, Suzuki K Poulose suzuki.poulose@arm.com wrote:
Hi Mike,
On 28/11/2018 10:14, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org
drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@
#define to_amba_driver(d) container_of(d, struct amba_driver, drv)
-static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0;
struct amba_cs_uci_id *uci;uci = table->data;/* no table data - return match on periphid */if (!uci)return 1;if (uci->devarch) {minor nit: It would be good to check the devarch_mask instead, as we will be covered if at all there is an expected devarch == 0. But the mask can never be 0, if we have something to check.
There is an expected devarch == 0 - it is defined in the spec as when devarch is not implemented - hence the explicit test here. If there is no devarch - then we can match on devtype alone.
Actually - forget what I just wrote. If device devarch value == 0. then the CS driver can set the table to devarch = 0, devmask = 0xffffffff and we get rid of the if/else clause completely.
Mike
ret = (dev->uci.devtype == uci->devtype) &&((dev->uci.devarch & uci->devarch_mask) == uci->devarch);} else {/* devtype only if devarch set to 0 */ret = dev->uci.devtype == uci->devtype;}return ret;+}
+static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) {
ret = (dev->periphid & table->mask) == table->id;if (ret)break;
if (((dev->periphid & table->mask) == table->id) &&((dev->cid != CORESIGHT_CID) ||(amba_cs_uci_id_match(table, dev))))return table; table++; }
return ret ? table : NULL;
return NULL;}
static int amba_match(struct device *dev, struct device_driver *drv)
@@ -399,10 +420,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
if (cid == CORESIGHT_CID) {/* set the base to the start of the last 4k block */void __iomem *csbase = tmp + size - 4096;dev->uci.devarch =readl(csbase + UCI_REG_DEVARCH_OFFSET);dev->uci.devtype =readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff;}amba_put_disable_pclk(dev);
if (cid == AMBA_CID || cid == CORESIGHT_CID)
if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid;dev->cid = cid;} if (!dev->periphid) ret = -ENODEV;diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..ff0ce0587ee9 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d
+/*
- CoreSight Architecture specification updates the ID specification
- for components on the AMBA bus. (ARM IHI 0029E)
- Bits 11:8 of the CID are the device class.
I think this should be Bits 15:12 ?
It should.
Thanks
Mike
- Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above)
- Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
- Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
- at present.
- Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
- Remaining CID bits stay as 0xb105-00d
- */
+/*
- Class 0x9 components use additional values to form a Unique Component
- Identifier (UCI), where peripheral ID values are identical for different
- components. Passed to the amba bus code from the component driver via
- the amba_id->data pointer.
- */
+struct amba_cs_uci_id {
unsigned int devarch;unsigned int devarch_mask;unsigned int devtype;+};
+#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC
struct clk;
struct amba_device {
@@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid;
unsigned int cid;struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override;Rest looks fine. With the above addressed,
Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code.
Signed-off-by: Mike Leach mike.leach@linaro.org --- drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..2fb8054e43ab 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1073,12 +1073,28 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) .mask = 0x000fffff, \ }
+static struct amba_cs_uci_id uci_id_etm4[] = { + { + /* ETMv4 UCI data */ + .devarch = 0x47704a13, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000013, + } +}; + +#define ETM4x_AMBA_UCI_ID(pid) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = uci_id_etm4, \ + } + static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ {}, };
This patch adds in logging and modifications to amba driver, etmv4 driver and DB410C device tree to allow testing of the new UCI component matching algorithm used for certain class of components on an AMBA bus.
Test only - not intended for upstream.
Signed-off-by: Mike Leach mike.leach@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++ drivers/amba/bus.c | 13 ++++++++++++- drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++- 3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a1..c8b503a63b2c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1368,6 +1368,15 @@ }; };
+ /* add an as yet unsupported CTI for UCI test - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 387ee8f7720b..ccc2bb4a98b8 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -32,19 +32,30 @@ amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; struct amba_cs_uci_id *uci; + struct device *adev; /* device for test logging */
uci = table->data; + adev = &dev->dev;
/* no table data - return match on periphid */ - if (!uci) + if (!uci) { + dev_info(adev, "uci_match: no UCI, use periphID\n"); return 1; + }
if (uci->devarch) { ret = (dev->uci.devtype == uci->devtype) && ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + dev_info(adev, "device: devtype[%x]; devarch[%x];\n", + dev->uci.devtype, dev->uci.devarch); + dev_info(adev, "uci_match: devtype[%x]; devarch[%x]; (%s)\n", + uci->devtype, uci->devarch, + ret ? "match" : "no match"); } else { /* devtype only if devarch set to 0 */ ret = dev->uci.devtype == uci->devtype; + dev_info(adev, "uci_match: devtype-only[%x]; (%s)\n", + uci->devtype, ret ? "match" : "no match"); } return ret; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 2fb8054e43ab..4dfc41c37447 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1090,11 +1090,12 @@ static struct amba_cs_uci_id uci_id_etm4[] = { }
static const struct amba_id etm4_ids[] = { - ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ + ETM4x_AMBA_UCI_ID(0x000bb95d), /* C-A53 - UCI optional for test */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9a8), /* CTI PID A53 - test fail UCI match */ {}, };
-
Mike Leach -
Suzuki K Poulose