CoreSight

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2670 discussions

[PATCH v2 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support

by James Clark

Fix a few issues with per-thread mode: - With TRBE, thread migrations hit a queue without a decoder assert - On nVHE, everything looks like guest trace instead of host - Tracing multiple threads didn't really work After adding a tests for those, it turns out there were some snapshot bugs not picked up by the other snapshot tests. That showed that the different snapshot searches for Intel BTS and Arm SPE were inconsistent and I think all tracers can benefit from using the same pointer fixup logic, so that gets refactored into the common auxtrace.c. Then SPE can just share the Intel BTS search as it was obviously copied from it originally. IntelPT keeps the more advanced duplicate data search, but in the future that could probably be made the common one and all tracers would benefit from using it (except maybe BTS if it always has a very small buffer, but I doubt the overhead of the duplicate search would be an issue). For now this is more of a refactor rather than behavioral change so don't do that yet. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v2: - Remove stale "may be reset to -1 in per-thread mode" comment - Set CPU when queueing auxtrace fragments otherwise auxtrace_queues__add_event() overwrites the queue's CPU - Link to v1: https://patch.msgid.link/20260811-james-cs-unformatted-per-thread-fix-v1-0-… --- James Clark (14): perf cs-etm: Fix nVHE per-thread decoding perf cs-etm: Warn for invalid timestamp option perf cs-etm: Turn on context packet timestamps in per-thread mode perf cs-etm: Use per-CPU queues for per-thread mode perf cs-etm: Increase default timestamp generation period perf auxtrace: Turn Intel BTS snapshot search into a generic one perf arm-spe: Use generic snapshot search perf auxtrace: intel-pt: Use new snapshot_has_wrapped callback perf cs-etm: Queue partial AUX records perf cs-etm: Don't print missing buffers in snapshot mode perf auxtrace: cs-etm: Capture wrapped snapshots perf test: Allow infinite named_thread loops perf test: Add test for per-thread mode perf cs-etm: Test multiple per-thread threads Documentation/userspace-api/perf_ring_buffer.rst | 6 +- tools/perf/Documentation/perf-test.txt | 2 +- tools/perf/arch/arm/util/cs-etm.c | 30 ++++- tools/perf/arch/arm64/util/arm-spe.c | 147 +-------------------- tools/perf/arch/x86/util/intel-bts.c | 115 +--------------- tools/perf/arch/x86/util/intel-pt.c | 58 +++----- .../perf/tests/shell/coresight/per-thread-multi.sh | 78 +++++++++++ tools/perf/tests/shell/coresight/per-thread.sh | 48 +++++++ .../perf/tests/shell/coresight/raw_dump_stress.sh | 5 - tools/perf/tests/workloads/named_threads.c | 7 +- tools/perf/util/auxtrace.c | 136 +++++++++++++++++-- tools/perf/util/auxtrace.h | 20 ++- tools/perf/util/cs-etm.c | 101 ++++++++++---- 13 files changed, 384 insertions(+), 369 deletions(-) --- base-commit: 9453bc6a69ef43755f1c28d5688cacdd69fa16bd change-id: 20260605-james-cs-unformatted-per-thread-fix-50e723aa7f0e Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 1 day

Re: [PATCH 1/2] coresight: etm4x: Report whether the PMU counts external output 1

by Leo Yan

Hi Amir, Thanks for the patch. I have a few initial comments below. We may have further feedback after our internal review. On Wed, Sep 30, 2026 at 11:37:43PM -0700, Amir Ayupov wrote: [...] > #define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > #define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > +/* ETM external output 1 is countable by the PMU as TRCEXTOUT1 */ > +#define CS_CFG_MATCH_CAP_PMU_EXTOUT1 0x0004 Do we need to tie this capability to TRCEXTOUT1? For example, Neoverse V2 exposes TRCEXTOUT0 through TRCEXTOUT3 as PMU events. > /* flags defining device instance matching - used in config match desc data. */ > #define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */ > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > index e1a59b4345052..2847d2d7f7bed 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > @@ -174,9 +174,14 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, > > int etm4_cscfg_register(struct coresight_device *csdev) > { > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct cscfg_csdev_feat_ops ops; > + u32 match_flags = CS_CFG_ETM4_MATCH_FLAGS; > > ops.load_feat = &etm4_cfg_load_feature; > > - return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); > + if (drvdata->pmu_extout1) > + match_flags |= CS_CFG_MATCH_CAP_PMU_EXTOUT1; > + > + return cscfg_register_csdev(csdev, match_flags, &ops); The current matching logic succeeds if a device and feature share any flag bit. If the feature sets both CS_CFG_MATCH_CLASS_SRC_ETM4 and CS_CFG_MATCH_CAP_PMU_EXTOUT1, it will still load on an ETM4 device that lacks the capability. Could we check the capability separately when loading the feature, perhaps in cscfg_load_feat_csdev(), and skip it on unsupported devices? > +static bool etm4_pmu_has_extout1(struct etmv4_drvdata *drvdata) > +{ > + int pmuver = read_pmuver(); > + > + if (!is_midr_in_range_list(etm4_pmu_extout1_cpus)) > + return false; Based on specific CPU variant, we should already have identified TRCEXTOUT has supported. So either we only base on MIDR list or we can figure out a reliable way to detect the feature dynamically. > + > + /* PMCEID0_EL0[63:32] describe events 0x4000-0x401f from PMUv3p1 */ > + if (!pmuv3_implemented(pmuver) || pmuver < ID_AA64DFR0_EL1_PMUVer_V3P1) > + return false; > + if (!(read_pmceid0() & BIT_ULL(32 + ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 - > + ARMV8_PMUV3_EXT_COMMON_EVENT_BASE))) > + return false; > + > + /* nr_event is TRCIDR0.NUMEVENT, the number of events minus one */ > + return drvdata->nr_event >= 1; > +} [...] > @@ -1116,6 +1116,13 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > > if (err) > cscfg_config_desc_put(config_desc); > + } else { > + /* > + * The configuration is active but was not loaded on this > + * device, for example because the device lacks a capability > + * its features require. Fail rather than trace without it. > + */ > + err = -EINVAL; > } This fixes a pre-existing issue. It is worther to put it in a separate patch with fixes tag: An early return would also avoid the normal enable path's indentation: if (!config_csdev_active) return -EINVAL; err = cscfg_csdev_enable_config(config_csdev_active, preset); ... Thanks, Leo

1 week, 2 days

Re: [PATCH 2/2] perf: arm_spe: Prefer large AUX mappings

by Leo Yan

On Thu, Oct 01, 2026 at 08:16:09AM +0100, Will Deacon wrote: > On Wed, Sep 30, 2026 at 05:43:11PM +0100, Leo Yan wrote: > > How about adding a field to struct pmu to specify a preferred maximum > > page order for the AUX buffer? The perf core could try that order first > > and fall back to smaller orders if the allocation fails. > > I'm not sure that's thr right place for it, really. The driver has no > clue about whether it makes sense to use large contiguous mappings or > not, so I'd have thought that decision should be driven from userspace > (e.g. like MADV_HUGEPAGE) because it really depends on the user's > preference and isn't a fixed property of the hardware. Here MADV_HUGEPAGE cannot directly apply on this case: perf allocates the AUX pages during mmap, while TRBE accesses them through a separate kernel vmap() mapping. MADV_HUGEPAGE is applied after mmap, but a preference (or flag) would need to be specified before the AUX mmap. > > For example, the Neoverse V2 TRM documents: > > > > L1 Trace Buffer Extension (TRBE) TLB: 1 entry > > Wow, they really pulled out the stops for that implementation. I bet > we're supposed to be grateful for that entry! Yeah, Neoverse V3 was improved to have two entries. Even so, I was told it still suffers from TLB misses, so still needs a large mapping granule. > > Given the single L1 TRBE TLB entry, the TRBE driver could prefer > > PMD_ORDER (2 MiB with 4 KiB pages) to reduce TLB pressure. This reflects > > the hardware characteristic. > > > > This could be a trade-off instead of using PERF_PMU_CAP_AUX_PREFER_LARGE, > > avoiding large contiguous allocations that could reintroduce the Android > > OOM issue. I did a quick test with this approach and the results look > > positive. > > I really don't want the driver to second-guess userspace based on whatever > information it happens to have hard-coded about the specific CPU it's > running on. The kernel already takes the PERF_PMU_CAP_AUX_PREFER_LARGE flag from a PMU; a preferred maximum order would let the driver give it a bounded value. I do not intend to hard-code or guess a preference for a particular CPU variant. We can map TRBE or SPE buffer at PMD granularity. On a 4 KiB-page system, PMD_ORDER is order 9, or 2 MiB. Requesting a larger contiguous chunk cannot increase the mapping granule, so I would cap the preference there. It remains a preference: perf can fall back to smaller orders when allocation fails. Exposing the preference to userspace also seems problematic. Users generally lack the hardware details needed to choose an appropriate value. Even if tools provide a default, the same policy would need to be duplicated across perf, simpleperf, and proprietary tools. I don't think userspace tools are the right place for this policy. Thanks, Leo

1 week, 4 days

[PATCH 0/2] coresight: Retry failed HW_ID writes

by James Clark

Extracted from the last two commits from [1] as they were only conceptually related to that patchset, not functionally. This can be safely applied to the driver separately. [1] https://lore.kernel.org/linux-perf-users/20260821-james-cs-hw_id-output-fai… Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (2): perf/core: Return errors from perf_report_aux_output_id() coresight: Retry failed HW_ID writes drivers/hwtracing/coresight/coresight-etm-perf.c | 50 +++++++++++++++--------- include/linux/perf_event.h | 2 +- kernel/events/core.c | 6 ++- 3 files changed, 36 insertions(+), 22 deletions(-) --- base-commit: 75ba5c486ea071d44d3f61318c88a7793bc768d4 change-id: 20261001-james-cs-retry-hw_id-8f1ec3cf2db3 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 4 days

Re: [PATCH 5/5] ARM: dts: qcom: apq8064: Drop PCLK from static replicator

by Leo Yan

On Fri, Oct 02, 2026 at 07:05:14PM +0300, Dmitry Baryshkov wrote: > On Fri, Oct 02, 2026 at 04:33:28PM +0100, Leo Yan wrote: > > On Fri, Oct 02, 2026 at 06:21:36PM +0300, Dmitry Baryshkov wrote: > > > On Fri, Oct 02, 2026 at 04:07:24PM +0100, Leo Yan wrote: > > > > The APQ8064 static replicator has no registers to program, so it > > > > does not need an APB clock. Remove its RPM_QDSS_CLK reference. > > > > Other programmable CoreSight devices keep their clock references. > > > > > > QDSS clock is not actually the APB one, it's required for the coresight > > > (or to access some of the regs) if I remember correctly. > > > > If so, it might be atclk for clocking the module rather than the > > register interface. Could you confirm this? > > > > The replicator is just a middle component on the data path. I read > > that it shares the same clock with other CoreSight components, so it > > should still be safe to remove the clock from the replicator node, > > as other components on the path will ensure that the clock is enabled. > > Unfortunately it might be hard to find info for this platform nowadays. How about rename RPM_QDSS_CLK on the static replicator as "atclk", the optional clock name supported by its binding. replicator { compatible = "arm,coresight-static-replicator"; clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; + clock-names = "atclk"; I would leave the AMBA CoreSight nodes in the same dtsi unchanged for now. They need an apb_pclk lookup for register access, and so far we have no evidence to justify adding the same RPM clock again as atclk. Please let me know if this works for you. Thanks, Leo

1 week, 4 days

[PATCH v3 0/4] perf: cs-etm: HW_ID improvements

by James Clark

The driver might not always be able to write HW_IDs, but we don't need them for unformatted mode anyway, so fix that in commit ("perf cs-etm: Synthesize missing HW_ID mappings for raw trace"). Include some other minor improvements encountered on the way to appease Sashiko, like properly freeing queues and ("perf: cs-etm: Respect --no-itrace option") makes debugging broken Coresight perf.data files easier. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v3: - Remove old b4 prerequisite metadata that's no longer relevant. - Link to v2: https://patch.msgid.link/20261002-james-cs-hw_id-output-failure-v2-0-7a194a… Changes in v2: - Drop driver changes and move to https://lore.kernel.org/linux-perf-users/20261001-james-cs-retry-hw_id-v1-0… - Don't process any HW_IDs for unformatted queues, just create decoders unconditionally with trace ID 1. - Use zfree() instead of etmq->decoder = NULL - Remove dependency on "[PATCH v2 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support", it wasn't functionally dependant, just touching some of the same lines. - Link to v1: https://patch.msgid.link/20260821-james-cs-hw_id-output-failure-v1-0-9d532d… --- James Clark (3): perf: cs-etm: Don't add global v0 HW_IDs to unformatted queues perf cs-etm: Free partially created queues perf: cs-etm: Respect --no-itrace option Leo Yan (1): perf cs-etm: Synthesize missing HW_ID mappings for raw trace tools/perf/util/auxtrace.c | 2 +- tools/perf/util/auxtrace.h | 1 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 12 +- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 2 +- tools/perf/util/cs-etm.c | 184 +++++++++++++++--------- 5 files changed, 123 insertions(+), 78 deletions(-) --- base-commit: 705da5b15ab89ba97b11eedbe507c2fd83d31cb9 change-id: 20260706-james-cs-hw_id-output-failure-1d06d042ef96 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 5 days

[PATCH RESEND v13 00/14] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - curr_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v12 to v13: - add r-b tags - Link to v12: https://lore.kernel.org/r/20260924-separate_etm_cfg_v2-v12-0-a2b41d2f7c2b@a… from v11 to v12: - rename active_config to curr_config. - rename config to sysfs_config. - remove redundant config argument in etmX_args. - add read-back and copy from curr_config to sysfs_config TRCSEQSTR (seq_state). - add r-b and t-b tags. - Link to v11: https://lore.kernel.org/r/20260915-separate_etm_cfg_v2-v11-0-d2b258d51747@a… from v10 to v11: - replace direct register read from etm3 sysfs with IPI. - fix issue cntr_val and others field which required to be shown after sysfs session disable. - prohibit the write for some etm3 sysfs while sysfs session is enabled. - drop locktype change in etm3 - Link to v10: https://lore.kernel.org/r/20260911-separate_etm_cfg_v2-v10-0-1b715d95927a@a… from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (14): coresight: etm4x: read-back TRCSEQSTR at disabling and prohibit modifying seq_state while enabling. coresight: etm4x: prohibit modifying cntr_val while session is enabled coresight: etm3x: prohibit modifying cntr_val and reset while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm4x: rename local config as curr_config referring drvdata->curr_config coresight: etm4x: rename drvdata->config to sysfs_config coresight: etm3x: introduce struct etm_caps coresight: etm3x: rename local config as curr_config referring drvdata->curr_config coresight: etm3x: rename drvdata->config to sysfs_config drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 + drivers/hwtracing/coresight/coresight-etm.h | 48 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 196 +++-- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 461 +++++----- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 567 ++++++------ .../hwtracing/coresight/coresight-etm4x-sysfs.c | 961 +++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 199 +++-- 9 files changed, 1340 insertions(+), 1146 deletions(-) --- base-commit: a3281934612608db9e1d24aaf913c846e913de89 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

2 weeks

[PATCH v13 00/14] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

2 weeks

Re: [PATCH 5/5] ARM: dts: qcom: apq8064: Drop PCLK from static replicator

by Leo Yan

On Fri, Oct 02, 2026 at 06:21:36PM +0300, Dmitry Baryshkov wrote: > On Fri, Oct 02, 2026 at 04:07:24PM +0100, Leo Yan wrote: > > The APQ8064 static replicator has no registers to program, so it > > does not need an APB clock. Remove its RPM_QDSS_CLK reference. > > Other programmable CoreSight devices keep their clock references. > > QDSS clock is not actually the APB one, it's required for the coresight > (or to access some of the regs) if I remember correctly. If so, it might be atclk for clocking the module rather than the register interface. Could you confirm this? The replicator is just a middle component on the data path. I read that it shares the same clock with other CoreSight components, so it should still be safe to remove the clock from the replicator node, as other components on the path will ensure that the clock is enabled. Thanks, Leo

2 weeks

[PATCH 0/5] arm: coresight: Clean up funnel and replicator clocks

by Leo Yan

This series documents optional atclk for static CoreSight links and removes unused clock references from several device trees. It also describes the programmable Zynq-7000 funnel as dynamic. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (5): dt-bindings: arm: coresight: Limit static replicator to atclk dt-bindings: arm: coresight: Allow atclk for static funnel arm64: dts: hisilicon: Drop PCLK from static CoreSight links ARM: dts: zynq: Use dynamic CoreSight funnel and trim clocks ARM: dts: qcom: apq8064: Drop PCLK from static replicator .../bindings/arm/arm,coresight-static-funnel.yaml | 6 ++++++ .../arm/arm,coresight-static-replicator.yaml | 11 ++-------- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 3 --- arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 24 ++++++++++------------ .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 4 ---- .../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 2 -- 6 files changed, 19 insertions(+), 31 deletions(-) --- base-commit: 551c722f40809618230001baccf219193e22fc5a change-id: 20261001-arm_coresight_hi3660_remove_dynamic_funnel_clocks-d277556abe8d Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 weeks

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