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This patchset builds upon Yicong's previous patches [1].
Patch 2 introducing fix race issues found by using TMC-ETR.
Patch 1 & 3 introducing two cleanups found when debugging the issues.
[1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@…
---
Changes in v4:
- a) Add comment at the context of set etr to sysfs mode.
- b) Move the check on drvdata->read to the start of enable etr.
- c) Add checks to prevent multiple sysfs processes from simultaneously
competing to enable ETR.
- d) Fix the issue with the guard used.
Link: https://lore.kernel.org/linux-arm-kernel/20250818080600.418425-1-hejunhao3@…
---
Changes in v3:
- Patches 1: Additional comment for tmc_drvdata::etr_mode. Update
comment for tmc_drvdata::reading with Jonathan's Tag.
- Patches 2: Replace scoped_guard with guard with Jonathan's Tag.
- Patches 2: Fix spinlock to raw_spinlock, and refactor this code based
on Leo's suggested solution.
- Patches 3: change the size's type to ssize_t and use max_t to simplify
the code with Leo's Tag.
Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@…
Changes in v2:
- Updated the commit of patch2.
- Rebase to v6.16-rc1
Junhao He (1):
coresight: tmc: refactor the tmc-etr mode setting to avoid race
conditions
Yicong Yang (2):
coresight: tmc: Add missing doc including reading and etr_mode of
struct tmc_drvdata
coresight: tmc: Decouple the perf buffer allocation from sysfs mode
.../hwtracing/coresight/coresight-tmc-etr.c | 136 +++++++++---------
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 66 insertions(+), 72 deletions(-)
--
2.33.0
On Mon, 03 Nov 2025 15:06:20 +0800, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.
>
> Changes in V4:
> 1. dtsi file has been renamed from qcs8300.dtsi -> monaco.dtsi
> Link to V3 - https://lore.kernel.org/all/20251013-enable-ctcu-for-qcs8300-v3-0-611e6e0d3…
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: add CTCU device for monaco
https://git.kernel.org/coresight/c/51cd1fb70e08
Best regards,
--
Suzuki K Poulose <suzuki.poulose(a)arm.com>
Hi,
On Fri, Dec 19, 2025 at 10:39:49AM +0800, Ma Ke wrote:
[...]
> From the discussion, I note two possible fix directions:
>
> 1. Release the initial reference in etm_setup_aux() (current v2 patch)
> 2. Modify the behavior of coresight_get_sink_by_id() itself so it
> doesn't increase the reference count.
The option 2 is the right way to go.
> To ensure the correctness of the v3 patch, I'd like to confirm which
> patch is preferred. If option 2 is the consensus, I'm happy to modify
> the implementation of coresight_get_sink_by_id() as suggested.
It is good to use a separate patch to fix
coresight_find_device_by_fwnode() mentioned by James:
diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
index 0db64c5f4995..2b34f818ba88 100644
--- a/drivers/hwtracing/coresight/coresight-platform.c
+++ b/drivers/hwtracing/coresight/coresight-platform.c
@@ -107,14 +107,16 @@ coresight_find_device_by_fwnode(struct fwnode_handle *fwnode)
* platform bus.
*/
dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
- if (dev)
- return dev;
/*
* We have a configurable component - circle through the AMBA bus
* looking for the device that matches the endpoint node.
*/
- return bus_find_device_by_fwnode(&amba_bustype, fwnode);
+ if (!dev)
+ dev = bus_find_device_by_fwnode(&amba_bustype, fwnode);
+
+ put_device(dev);
+ return dev;
}
/*
@@ -274,7 +276,6 @@ static int of_coresight_parse_endpoint(struct device *dev,
of_node_put(rparent);
of_node_put(rep);
- put_device(rdev);
return ret;
}
Thanks for working on this.
On 19/12/2025 09:08, Jie Gan wrote:
>
>
> On 11/3/2025 3:06 PM, Jie Gan wrote:
>> The CTCU device for monaco shares the same configurations as SA8775p. Add
>> a fallback to enable the CTCU for monaco to utilize the compitable of the
>> SA8775p.
>>
>
> Gentle reminder.
I was under the assumption that this was going via msm tree ? Sorry, I
misunderstood. I can pull this in for v6.20
Suzuki
>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org>
>> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
>> Reviewed-by: Bjorn Andersson <andersson(a)kernel.org>
>> Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +
>> ++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-
>> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-
>> ctcu.yaml
>> index c969c16c21ef..460f38ddbd73 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> @@ -26,8 +26,13 @@ description: |
>> properties:
>> compatible:
>> - enum:
>> - - qcom,sa8775p-ctcu
>> + oneOf:
>> + - items:
>> + - enum:
>> + - qcom,qcs8300-ctcu
>> + - const: qcom,sa8775p-ctcu
>> + - enum:
>> + - qcom,sa8775p-ctcu
>> reg:
>> maxItems: 1
>>
>