CoreSight

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Re: [PATCH v3 0/7] Provides support for Trigger Generation Unit

by Mike Leach

Hi, On Fri, 21 Mar 2025 at 03:26, songchai <quic_songchai(a)quicinc.com> wrote: > > > On 3/7/2025 12:57 AM, Mike Leach wrote: > > Hi, > > > > On Thu, 27 Feb 2025 at 09:27, songchai <quic_songchai(a)quicinc.com> wrote: > >> Provide support for the TGU (Trigger Generation Unit), which can be > >> utilized to sense a plurality of signals and create a trigger into > >> the CTI or generate interrupts to processors once the input signal > >> meets the conditions. We can treat the TGU’s workflow as a flowsheet, > >> it has some “steps” regions for customization. In each step region, > >> we can set the signals that we want with priority in priority_group, set > >> the conditions in each step via condition_decode, and set the resultant > >> action by condition_select. Meanwhile, some TGUs (not all) also provide > >> timer/counter functionality. Based on the characteristics described > >> above, we consider the TGU as a helper in the CoreSight subsystem. > >> Its master device is the TPDM, which can transmit signals from other > >> subsystems, and we reuse the existing ports mechanism to link the TPDM to > >> the connected TGU. > >> > > I do not believe that his component is part of the Coresight subsystem. > > > > 1) It inputs multiple signals from the SoC to process and create an > > trigger event - however, it can do this irrespective of CoreSight > > trace being operational, especially where generating interrupts for > > processors, or triggers for other non-coresight components. It would > > appear that the TPDM can send output to more than just the TDPA which > > generates coresight trace packets - a previously undisclosed feature. > > TGU is a part the QPMDA(Qualcomm Performance Monitoring and > > Diagnostics Architecture ) library, and the signals it perceives are > from TPDM and connected > > through hardware. So it depends on the coresight-tpdm, and will not > work if the coresight > > tpdm is not operational. > As I understand it from reading many of the patches for this and other of the components, the QPMDA is a proprietary network of monitoring components across your SoCs, that can have an endpoint that generates CoreSight trace (from the TPDA). The nature of this network has not been specified - but it does seem that the TDPM can output to more than one device - perhaps some sort of internal bus runs between all the QPMDA devices. Is it possible that the TDPM can be programmed to output to the TGU, without trace being generated from the TPDA? If you enable just the TPDM and TGU, can you program the TGU to output triggers to CPU and other none-coresight devices, as implied in the binding descriptions? > > > > 2) The ports mechanism is a generic device tree mechanism, not > > something unique to the Coresight subsystem. > > Sure, Mike. As i mentioned above, the signals reach the TGU through > hardware.So the port > > mechanism here is not for the data transmission, but to confirm the > relationship of the TGU > > as a TPDM helper. > > > > > 3) The CTI trigger connection will be defined in devicetree under the > > CTI component, as this is the interface between this component and > > coresight. > > The TGU is utilized to sense a plurality of signals and create a trigger > into the CTI. > > It should be a trigger in for the targeting CTI. Could we configure the > targeting CTI's trigger_in > > and trigger_out instead of configuring in the devicetree? > You would need to make additional device tree entries in the relevant CTI for the input trigger from the TGU for the CTI driver to correctly display the source of the trigger. > > > > As such this seems more like a general performance and debug > > component, with optional inputs to the coresight trigger mechanisms, > > rather than being a coresight component itself. Other SoCs have > > non-coresight component inputs to CTIs. For example the PL011 serial > > device on Juno has a signal into one of the system CTIs. > > In addition to above, the TGU also have the coresight management > registers in its register region > > which is a character of coresight component. > These registers are not exposed in sysfs by your driver, nor are the values known, so it is difficult to know if they correctly follow the CoreSight 3.0 Architecture specification - ARM IHI 0029F; which defines the identification and discovery requirements that all CoreSight components must follow. These appear to be missing from your other devices listed in the coresight driver area - something we appear to have overlooked in previous driver reviews. The CTI / ETM and other ARM component coresight drivers all have a sysfs "mgmt" section that exposes these management registers. As I mentioned in my comments to the bindings in patch 1 - the Coresight visible component architecture and ID registers should be used to discover and identify the capabilities of components, such as in this case the number of steps/timers/triggers/priorities - and not need these values to be defined in the device tree. In this way, we remove the possibility of errors in a device tree leading to driver failure. Regards Mike > Based on these clarification, could we consider it as a coresight > component？ > > > >> Here is a detailed example to explain how to use the TGU: > >> > >> In this example, the TGU is configured to use 2 conditions, 2 steps, and > >> the timer. The goal is to look for one of two patterns which are generated > >> from TPDM, giving priority to one, and then generate a trigger once the > >> timer reaches a certain value. In other words, two conditions are used > >> for the first step to look for the two patterns, where the one with the > >> highest priority is used in the first condition. Then, in the second step, > >> the timer is enabled and set to be compared to the given value at each > >> clock cycle. These steps are better shown below. > >> > >> > >> |-----------------| > >> | | > >> | TPDM | > >> | | > >> |-----------------| > >> | > >> | > >> --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------ > >> | | | > >> | | |--------------------| | > >> | |---- ---> | | Go to next steps | | > >> | | | |--- ---> | Enable timer | | > >> | | v | | | | > >> | | |-----------------| | |--------------------| | > >> | | | | Yes | | | > >> | | | inputs==0xB | ----->| | <-------- | > >> | | | | | | No | | > >> | No | |-----------------| | v | | > >> | | | | |-----------------| | | > >> | | | | | | | | > >> | | | | | timer>=3 |-- | > >> | | v | | | | > >> | | |-----------------| | |-----------------| | > >> | | | | Yes | | | > >> | |--- | inputs==0xA | ----->| | Yes | > >> | | | | | > >> | |-----------------| v | > >> | |-----------------| | > >> | | | | > >> | | Trigger | | > >> | | | | > >> | |-----------------| | > >> | TGU | | > >> |--- --- --- --- --- --- --- --- --- --- --- --- --- --- |--- --- -- | > >> | > >> v > >> |-----------------| > >> |The controllers | > >> |which will use | > >> |triggers further | > >> |-----------------| > >> > >> steps: > >> 1. Reset TGU /*it will disable tgu and reset dataset*/ > >> - echo 1 > /sys/bus/coresight/devices/<tgu-name>/reset_tgu > >> > >> 2. Set the pattern match for priority0 to 0xA = 0b1010 and for > >> priority 1 to 0xB = 0b1011. > >> - echo 0x11113232 > /sys/bus/coresight/devices/<tgu-name>/step0_priority0/reg0 > >> - echo 0x11113233 > /sys/bus/coresight/devices/<tgu-name>/step0_priority1/reg0 > >> > >> Note: > >> Bit distribution diagram for each priority register > >> |-------------------------------------------------------------------| > >> | Bits | Field Nam | Description | > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 29:28 | SEL_BIT7_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 25:24 | SEL_BIT6_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 21:20 | SEL_BIT5_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 17:16 | SEL_BIT4_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 13:12 | SEL_BIT3_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 9:8 | SEL_BIT2_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 5:4 | SEL_BIT1_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 1:0 | SEL_BIT0_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> These bits are used to identify the signals we want to sense, with > >> a maximum signal number of 140. For example, to sense the signal > >> 0xA (binary 1010), we set the value of bits 0 to 13 to 3232, which > >> represents 1010. The remaining bits are set to 1, as we want to use > >> AND gate to summarize all the signals we want to sense here. For > >> rising or falling edge detection of any input to the priority, set > >> the remaining bits to 0 to use an OR gate. > >> > >> 3. look for the pattern for priority_i i=0,1. > >> - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg0 > >> - echo 0x30 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg1 > >> > >> |-------------------------------------------------------------------------------| > >> | Bits | Field Nam | Description | > >> |-------------------------------------------------------------------------------| > >> | | |For each decoded condition, this | > >> | 24 | NOT |inverts the output. If the condition | > >> | | |decodes to true, and the NOT field | > >> | | |is '1', then the output is NOT true. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | 21 | BC0_COMP_ACTIVE |comparator will be actively included in| > >> | | |the decoding of this particular | > >> | | |condition. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | | |comparator will need to be 1 to affect | > >> | 20 | BC0_COMP_HIGH |the decoding of this condition. | > >> | | |Conversely, a '0' here requires a '0' | > >> | | |from the comparator | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | 17 | |comparator will be actively included in| > >> | | TC0_COMP_ACTIVE |the decoding of this particular | > >> | | |condition. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | | |comparator will need to be 1 to affect | > >> | 16 | TC0_COMP_HIGH |the decoding of this particular | > >> | | |condition.Conversely, a 0 here | > >> | | |requires a '0' from the comparator | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |OR logic will be actively | > >> | 4n+3 | Priority_n_OR_ACTIVE|included in the decoding of | > >> | | (n=0,1,2,3) |this particular condition. | > >> | | | | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |will need to be '1' to affect the | > >> | 4n+2 | Priority_n_OR_HIGH |decoding of this particular | > >> | | (n=0,1,2,3) |condition. Conversely, a '0' here | > >> | | |requires a '0' from Priority_n OR logic| > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |AND logic will be actively | > >> | 4n+1 |Priority_n_AND_ACTIVE|included in the decoding of this | > >> | | (n=0,1,2,3) |particular condition. | > >> | | | | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |AND logic will need to be '1' to | > >> | 4n | Priority_n_AND_HIGH |affect the decoding of this | > >> | | (n=0,1,2,3) |particular condition. Conversely, | > >> | | |a '0' here requires a '0' from | > >> | | |Priority_n AND logic. | > >> |-------------------------------------------------------------------------------| > >> Since we use `priority_0` and `priority_1` with an AND output in step 2, we set `0x3` > >> and `0x30` here to activate them. > >> > >> 4. Set NEXT_STEP = 1 and TC0_ENABLE = 1 so that when the conditions > >> are met then the next step will be step 1 and the timer will be enabled. > >> - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg0 > >> - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg1 > >> > >> |-----------------------------------------------------------------------------| > >> | Bits | Field Nam | Description | > >> |-----------------------------------------------------------------------------| > >> | | |This field defines the next step the | > >> | 18:17 | NEXT_STEP |TGU will 'goto' for the associated | > >> | | |Condition and Step. | > >> |-----------------------------------------------------------------------------| > >> | | |For each possible output trigger | > >> | 13 | TRIGGER |available, set a '1' if you want | > >> | | |the trigger to go active for the | > >> | | |associated condition and Step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause BC0 to increment if the| > >> | 9 | BC0_INC |associated Condition is decoded for | > >> | | |this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause BC0 to decrement if the| > >> | 8 | BC0_DEC |associated Condition is decoded for | > >> | | |this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will clear BC0 count value to 0 if| > >> | 7 | BC0_CLEAR |the associated Condition is decoded | > >> | | |for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause TC0 to increment until | > >> | 3 | TC0_ENABLE |paused or cleared if the associated | > >> | | |Condition is decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause TC0 to pause until | > >> | 2 | TC0_PAUSE |enabled if the associated Condition | > >> | | |is decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will clear TC0 count value to 0 | > >> | 1 | TC0_CLEAR |if the associated Condition is | > >> | | |decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will set the done signal to the | > >> | 0 | DONE |TGU FSM if the associated Condition | > >> | | |is decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> Based on the distribution diagram, we set `0x20008` for `priority0` and `priority1` to > >> achieve "jump to step 1 and enable TC0" once the signal is sensed. > >> > >> 5. activate the timer comparison for this step. > >> - echo 0x30000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_decode/reg0 > >> > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | 17 | |comparator will be actively included in| > >> | | TC0_COMP_ACTIVE |the decoding of this particular | > >> | | |condition. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | | |comparator will need to be 1 to affect | > >> | 16 | TC0_COMP_HIGH |the decoding of this particular | > >> | | |condition.Conversely, a 0 here | > >> | | |requires a '0' from the comparator | > >> |-------------------------------------------------------------------------------| > >> Accroding to the decode distribution diagram , we give 0x30000 here to set 16th&17th bit > >> to enable timer comparison. > >> > >> 6. Set the NEXT_STEP = 0 and TC0_PAUSE = 1 and TC0_CLEAR = 1 once the timer > >> has reached the given value. > >> - echo 0x6 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/reg0 > >> > >> 7. Enable Trigger 0 for TGU when the condition 0 is met in step1, > >> i.e. when the timer reaches 3. > >> - echo 0x2000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/default > >> > >> Note: > >> 1. 'default' register allows for establishing the resultant action for > >> the default condition > >> > >> 2. Trigger:For each possible output trigger available from > >> the Design document, there are three triggers: interrupts, CTI, > >> and Cross-TGU mapping.All three triggers can occur, but > >> the choice of which trigger to use depends on the user's > >> needs. > >> > >> 8. Compare the timer to 3 in step 1. > >> - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step1_timer/reg0 > >> > >> 9. enale tgu > >> - echo 1 > /sys/bus/coresight/devices/<tgu-name>/enable_tgu > >> > > If this is version 3 - where is the list of differences from versions 1 - 2? > My bad. Will add the previous change log in the next version. > > > >> Songwei Chai (7): > >> dt-bindings: arm: Add support for Coresight TGU trace > >> coresight: Add coresight TGU driver > >> coresight-tgu: Add signal priority support > >> coresight-tgu: Add TGU decode support > >> coresight-tgu: add support to configure next action > >> coresight-tgu: add timer/counter functionality for TGU > >> coresight-tgu: add reset node to initialize > >> > >> .../testing/sysfs-bus-coresight-devices-tgu | 51 ++ > >> .../bindings/arm/qcom,coresight-tgu.yaml | 135 ++++ > >> drivers/hwtracing/coresight/Kconfig | 11 + > >> drivers/hwtracing/coresight/Makefile | 1 + > >> drivers/hwtracing/coresight/coresight-tgu.c | 669 ++++++++++++++++++ > >> drivers/hwtracing/coresight/coresight-tgu.h | 242 +++++++ > >> 6 files changed, 1109 insertions(+) > >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > >> create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > >> create mode 100644 drivers/hwtracing/coresight/coresight-tgu.c > >> create mode 100644 drivers/hwtracing/coresight/coresight-tgu.h > >> > > Regards > > > > > > Mike > > > > -- > > Mike Leach > > Principal Engineer, ARM Ltd. > > Manchester Design Centre. UK -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 weeks, 5 days

Re: [GIT PULL] coresight: Updates for v6.15

by Suzuki K Poulose

On 20/03/2025 13:52, Greg KH wrote: > On Mon, Mar 17, 2025 at 01:51:10PM +0000, Suzuki K Poulose wrote: >> Hi Greg, >> >> Please find the updates for coresight/hwtracing subsystem targeting v6.15. >> >> Kindly pull, >> Suzuki >> >> The following changes since commit 0ad2507d5d93f39619fc42372c347d6006b64319: >> >> Linux 6.14-rc3 (2025-02-16 14:02:44 -0800) >> >> are available in the Git repository at: >> >> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.15 > > Pulled and pushed out, thanks. > > greg k-h Thank you Greg !

3 weeks, 6 days

[PATCH v2 0/8] coresight: Clear self hosted claim tag on probe

by James Clark

I've gotten stuck a few times with unusable Coresight after a warm boot due to lingering claim tags, especially when testing the Coresight panic patchsets. This change does some tidy ups, adds some debug messages and clears the self hosted claim tag on probe. The last two commits are unrelated tidyups but they touch some of the same functions so to avoid extra conflicts I'm including them here. This gets as far as fixing the claim tag issue, but there is some other state not being cleared on probe that results in the following error. This can be fixed up as a later change: coresight tmc_etf0: timeout while waiting for TMC to be Ready coresight tmc_etf0: Failed to enable : TMC is not ready Changes in v2: * Revert most of the interface changes, just call coresight_clear_self_claim_tag() directly. This is possible because we're not doing the read first, so it has fewer knock on effects. * Split out the change to add struct cs_access to etm3x * Add another warning for racing with external debugger -- 2.34.1 --- James Clark (8): coresight: Rename coresight_{set,clear}_claim_tags() coresight: Convert tag clear function to take a struct cs_access coresight: Only check bottom two claim bits coresight: Add claim tag warnings and debug messages coresight: etm3x: Convert raw base pointer to struct coresight access coresight: Clear self hosted claim tag on probe coresight: Remove inlines from static function definitions coresight: Remove extern from function declarations drivers/hwtracing/coresight/coresight-catu.c | 12 +-- drivers/hwtracing/coresight/coresight-core.c | 85 ++++++++++++++-------- drivers/hwtracing/coresight/coresight-cti-core.c | 2 + drivers/hwtracing/coresight/coresight-etb10.c | 4 +- drivers/hwtracing/coresight/coresight-etm.h | 6 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 28 +++---- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 ++- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 1 + drivers/hwtracing/coresight/coresight-platform.c | 26 +++---- drivers/hwtracing/coresight/coresight-priv.h | 20 ++--- drivers/hwtracing/coresight/coresight-replicator.c | 3 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- .../coresight/coresight-syscfg-configfs.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 9 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 16 ++-- drivers/hwtracing/coresight/coresight-trbe.c | 18 ++--- include/linux/coresight.h | 40 +++++----- 19 files changed, 166 insertions(+), 134 deletions(-) --- base-commit: 5442d22da7dbff3ba8c6720fc6f23ea4934d402d change-id: 20250317-james-coresight-claim-tags-ae1461f1f5e0 Best regards, -- James Clark <james.clark(a)linaro.org>

4 weeks

[PATCH] arm: coresight: Finish removal of Coresight support in arch/arm/kernel

by James Clark

Commit 184901a06a36 ("ARM: removing support for etb/etm in "arch/arm/kernel/"") removed asm/hardware/coresight.h which is included by this file. Therefore this is dead code so delete it. Signed-off-by: James Clark <james.clark(a)linaro.org> --- arch/arm/include/asm/cti.h | 160 ------------------------------------- 1 file changed, 160 deletions(-) delete mode 100644 arch/arm/include/asm/cti.h diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h deleted file mode 100644 index f8500e5d6ea8..000000000000 --- a/arch/arm/include/asm/cti.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASMARM_CTI_H -#define __ASMARM_CTI_H - -#include <asm/io.h> -#include <asm/hardware/coresight.h> - -/* The registers' definition is from section 3.2 of - * Embedded Cross Trigger Revision: r0p0 - */ -#define CTICONTROL 0x000 -#define CTISTATUS 0x004 -#define CTILOCK 0x008 -#define CTIPROTECTION 0x00C -#define CTIINTACK 0x010 -#define CTIAPPSET 0x014 -#define CTIAPPCLEAR 0x018 -#define CTIAPPPULSE 0x01c -#define CTIINEN 0x020 -#define CTIOUTEN 0x0A0 -#define CTITRIGINSTATUS 0x130 -#define CTITRIGOUTSTATUS 0x134 -#define CTICHINSTATUS 0x138 -#define CTICHOUTSTATUS 0x13c -#define CTIPERIPHID0 0xFE0 -#define CTIPERIPHID1 0xFE4 -#define CTIPERIPHID2 0xFE8 -#define CTIPERIPHID3 0xFEC -#define CTIPCELLID0 0xFF0 -#define CTIPCELLID1 0xFF4 -#define CTIPCELLID2 0xFF8 -#define CTIPCELLID3 0xFFC - -/* The below are from section 3.6.4 of - * CoreSight v1.0 Architecture Specification - */ -#define LOCKACCESS 0xFB0 -#define LOCKSTATUS 0xFB4 - -/** - * struct cti - cross trigger interface struct - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out_for_irq: triger out number which will cause - * the @irq happen - * - * cti struct used to operate cti registers. - */ -struct cti { - void __iomem *base; - int irq; - int trig_out_for_irq; -}; - -/** - * cti_init - initialize the cti instance - * @cti: cti instance - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out: triger out number which will cause - * the @irq happen - * - * called by machine code to pass the board dependent - * @base, @irq and @trig_out to cti. - */ -static inline void cti_init(struct cti *cti, - void __iomem *base, int irq, int trig_out) -{ - cti->base = base; - cti->irq = irq; - cti->trig_out_for_irq = trig_out; -} - -/** - * cti_map_trigger - use the @chan to map @trig_in to @trig_out - * @cti: cti instance - * @trig_in: trigger in number - * @trig_out: trigger out number - * @channel: channel number - * - * This function maps one trigger in of @trig_in to one trigger - * out of @trig_out using the channel @chan. - */ -static inline void cti_map_trigger(struct cti *cti, - int trig_in, int trig_out, int chan) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINEN + trig_in * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIINEN + trig_in * 4); - - val = __raw_readl(base + CTIOUTEN + trig_out * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIOUTEN + trig_out * 4); -} - -/** - * cti_enable - enable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_enable(struct cti *cti) -{ - __raw_writel(0x1, cti->base + CTICONTROL); -} - -/** - * cti_disable - disable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_disable(struct cti *cti) -{ - __raw_writel(0, cti->base + CTICONTROL); -} - -/** - * cti_irq_ack - clear the cti irq - * @cti: cti instance - * - * clear the cti irq - */ -static inline void cti_irq_ack(struct cti *cti) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINTACK); - val |= BIT(cti->trig_out_for_irq); - __raw_writel(val, base + CTIINTACK); -} - -/** - * cti_unlock - unlock cti module - * @cti: cti instance - * - * unlock the cti module, or else any writes to the cti - * module is not allowed. - */ -static inline void cti_unlock(struct cti *cti) -{ - __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); -} - -/** - * cti_lock - lock cti module - * @cti: cti instance - * - * lock the cti module, so any writes to the cti - * module will be not allowed. - */ -static inline void cti_lock(struct cti *cti) -{ - __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); -} -#endif -- 2.34.1

4 weeks, 1 day

[PATCH 0/7] coresight: Clear self hosted claim tag on probe

by James Clark

I've gotten stuck a few times with unusable Coresight after a warm boot due to lingering claim tags, especially when testing the Coresight panic patchsets. This change does some tidy ups, adds some debug messages and clears the self hosted claim tag on probe. The last two commits are unrelated tidyups but they touch some of the same functions so to avoid extra conflicts I'm including them here. This gets as far as fixing the claim tag issue, but there is some other state not being cleared on probe that results in the following error. This can be fixed up as a later change: coresight tmc_etf0: timeout while waiting for TMC to be Ready coresight tmc_etf0: Failed to enable : TMC is not ready James Clark (7): coresight: Rename coresight_{set,clear}_claim_tags() coresight: Convert disclaim functions to take a struct cs_access coresight: Only check bottom two claim bits coresight: Add claim tag warnings and debug messages coresight: Clear self hosted claim tag on probe coresight: Remove inlines from static function definitions coresight: Remove extern from function declarations drivers/hwtracing/coresight/coresight-catu.c | 14 +- drivers/hwtracing/coresight/coresight-core.c | 132 +++++++++++------- .../hwtracing/coresight/coresight-cti-core.c | 8 +- drivers/hwtracing/coresight/coresight-etb10.c | 6 +- drivers/hwtracing/coresight/coresight-etm.h | 6 +- .../coresight/coresight-etm3x-core.c | 32 ++--- .../coresight/coresight-etm3x-sysfs.c | 8 +- .../coresight/coresight-etm4x-core.c | 12 +- .../coresight/coresight-etm4x-sysfs.c | 4 +- .../hwtracing/coresight/coresight-funnel.c | 4 +- .../hwtracing/coresight/coresight-platform.c | 26 ++-- drivers/hwtracing/coresight/coresight-priv.h | 20 +-- .../coresight/coresight-replicator.c | 7 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- .../coresight/coresight-syscfg-configfs.c | 2 +- .../hwtracing/coresight/coresight-tmc-core.c | 9 +- .../hwtracing/coresight/coresight-tmc-etf.c | 8 +- .../hwtracing/coresight/coresight-tmc-etr.c | 20 ++- drivers/hwtracing/coresight/coresight-trbe.c | 18 +-- include/linux/coresight.h | 32 ++--- 20 files changed, 209 insertions(+), 165 deletions(-) -- 2.34.1

4 weeks, 1 day

[GIT PULL] coresight: Updates for v6.15

by Suzuki K Poulose

Hi Greg, Please find the updates for coresight/hwtracing subsystem targeting v6.15. Kindly pull, Suzuki The following changes since commit 0ad2507d5d93f39619fc42372c347d6006b64319: Linux 6.14-rc3 (2025-02-16 14:02:44 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.15 for you to fetch changes up to 5442d22da7dbff3ba8c6720fc6f23ea4934d402d: Coresight: Fix a NULL vs IS_ERR() bug in probe (2025-03-14 12:43:53 +0000) ---------------------------------------------------------------- coresight: updates for Linux v6.15 CoreSight self-hosted tracing driver subsystem update for Linux v6.15. The update includes: - CoreSight trace capture for Panic/Watchdog timeouts - Fixes to ETM4x driver to synchronize register reads as required by the TRM - Support for Qualcomm CoreSight TMC Control Unit driver - Conversion of device locks to raw_spinlock for components that are used by the Perf mode. - Miscellaneous fixes for the subsystem Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Christophe JAILLET (1): coresight: configfs: Constify struct config_item_type Dan Carpenter (1): Coresight: Fix a NULL vs IS_ERR() bug in probe Ilkka Koskinen (1): coresight: catu: Fix number of pages while using 64k pages James Clark (2): Coresight: Use coresight_etm_get_trace_id() in traceid_show() coresight: docs: Remove target sink from examples Jie Gan (9): Coresight: Add support for new APB clock name Coresight: Add trace_id function to retrieving the trace ID Coresight: Introduce a new struct coresight_path Coresight: Allocate trace ID after building the path Coresight: Change to read the trace ID from coresight_path Coresight: Change functions to accept the coresight_path dt-bindings: arm: Add Coresight TMC Control Unit hardware Coresight: Add Coresight TMC Control Unit driver coresight: add verification process for coresight_etm_get_trace_id Krzysztof Kozlowski (5): coresight: catu: Constify amba_id table coresight: tpda: Constify amba_id table coresight: tpdm: Constify amba_id table dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg' dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg' Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM Wolfram Sang (1): coresight: etm4x: don't include '<linux/pm_wakeup.h>' directly Yeoreum Yun (9): coresight: change coresight_device lock type to raw_spinlock_t coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t coresight: change coresight_trace_id_map's lock type to raw_spinlock_t coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t coresight-funnel: change funnel_drvdata spinlock's type to raw_spinlock_t coresight-replicator: change replicator_drvdata spinlock's type to raw_spinlock_t coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t coresight/ultrasoc: change smb_drv_data spinlock's type to raw_spinlock_t Yuanfang Zhang (1): coresight-etm4x: add isb() before reading the TRCSTATR .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 15 + .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 26 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++ .../bindings/arm/qcom,coresight-tpda.yaml | 3 +- .../bindings/arm/qcom,coresight-tpdm.yaml | 3 +- Documentation/trace/coresight/coresight.rst | 41 +-- Documentation/trace/coresight/panic.rst | 362 +++++++++++++++++++++ Documentation/userspace-api/perf_ring_buffer.rst | 4 +- drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 4 +- drivers/hwtracing/coresight/coresight-catu.c | 4 +- .../hwtracing/coresight/coresight-cfg-preload.c | 2 + .../hwtracing/coresight/coresight-cfg-preload.h | 2 + drivers/hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++ drivers/hwtracing/coresight/coresight-config.c | 8 +- drivers/hwtracing/coresight/coresight-config.h | 2 +- drivers/hwtracing/coresight/coresight-core.c | 192 +++++++++-- drivers/hwtracing/coresight/coresight-ctcu-core.c | 326 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-ctcu.h | 39 +++ drivers/hwtracing/coresight/coresight-cti-core.c | 44 +-- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 76 ++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- drivers/hwtracing/coresight/coresight-dummy.c | 15 +- drivers/hwtracing/coresight/coresight-etb10.c | 26 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 27 +- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 +- drivers/hwtracing/coresight/coresight-etm.h | 1 - drivers/hwtracing/coresight/coresight-etm3x-core.c | 55 +--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 3 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 122 +++---- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 254 +++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +- drivers/hwtracing/coresight/coresight-funnel.c | 12 +- drivers/hwtracing/coresight/coresight-priv.h | 14 +- drivers/hwtracing/coresight/coresight-replicator.c | 12 +- drivers/hwtracing/coresight/coresight-stm.c | 13 +- .../coresight/coresight-syscfg-configfs.c | 12 +- drivers/hwtracing/coresight/coresight-syscfg.c | 26 +- drivers/hwtracing/coresight/coresight-sysfs.c | 17 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 327 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 140 ++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 224 +++++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 106 +++++- drivers/hwtracing/coresight/coresight-tpda.c | 20 +- drivers/hwtracing/coresight/coresight-tpdm.c | 124 ++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 33 +- drivers/hwtracing/coresight/coresight-trace-id.c | 22 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 12 +- drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- include/linux/coresight.h | 47 ++- 50 files changed, 2452 insertions(+), 553 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-core.c create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h

1 month

[PATCH v2] coresight: Fixes device's owner field for registered using coresight_init_driver()

by Junhao He

1 month

[PATCH] coresight: Fixes device's owner field for registered using coresight_init_driver()

by Junhao He

The coresight_init_driver() of the coresight-core module is called from the sub coresgiht device (such as tmc/stm/funnle/...) module. It calls amba_driver_register() and Platform_driver_register(), which are macro functions that use the coresight-core's module to initialize the caller's owner field. Therefore, when the sub coresight device calls coresight_init_driver(), an incorrect THIS_MODULE value is captured. The sub coesgiht modules can be removed while their callbacks are running, resulting in a general protection failure. Add module parameter to coresight_init_driver() so can be called with the module of the callback. Fixes: 075b7cd7ad7d ("coresight: Add helpers registering/removing both AMBA and platform drivers") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> --- drivers/hwtracing/coresight/coresight-catu.c | 2 +- drivers/hwtracing/coresight/coresight-core.c | 6 +++--- drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 ++- drivers/hwtracing/coresight/coresight-funnel.c | 3 ++- drivers/hwtracing/coresight/coresight-replicator.c | 3 ++- drivers/hwtracing/coresight/coresight-stm.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 2 +- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- include/linux/coresight.h | 2 +- 9 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index bfea880d6dfb..337668f9cfd4 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -702,7 +702,7 @@ static int __init catu_init(void) { int ret; - ret = coresight_init_driver("catu", &catu_driver, &catu_platform_driver); + ret = coresight_init_driver("catu", &catu_driver, &catu_platform_driver, THIS_MODULE); tmc_etr_set_catu_ops(&etr_catu_buf_ops); return ret; } diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 9fc6f6b863e0..c546a417836c 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1399,17 +1399,17 @@ module_init(coresight_init); module_exit(coresight_exit); int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, - struct platform_driver *pdev_drv) + struct platform_driver *pdev_drv, struct module *owner) { int ret; - ret = amba_driver_register(amba_drv); + ret = __amba_driver_register(amba_drv, owner); if (ret) { pr_err("%s: error registering AMBA driver\n", drv); return ret; } - ret = platform_driver_register(pdev_drv); + ret = __platform_driver_register(pdev_drv, owner); if (!ret) return 0; diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 75962dae9aa1..cc599c5ef4b2 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -774,7 +774,8 @@ static struct platform_driver debug_platform_driver = { static int __init debug_init(void) { - return coresight_init_driver("debug", &debug_driver, &debug_platform_driver); + return coresight_init_driver("debug", &debug_driver, &debug_platform_driver, + THIS_MODULE); } static void __exit debug_exit(void) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 5a819c8970fb..8f451b051ddc 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -433,7 +433,8 @@ static struct amba_driver dynamic_funnel_driver = { static int __init funnel_init(void) { - return coresight_init_driver("funnel", &dynamic_funnel_driver, &funnel_driver); + return coresight_init_driver("funnel", &dynamic_funnel_driver, &funnel_driver, + THIS_MODULE); } static void __exit funnel_exit(void) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 3e55be9c8418..f7607c72857c 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -438,7 +438,8 @@ static struct amba_driver dynamic_replicator_driver = { static int __init replicator_init(void) { - return coresight_init_driver("replicator", &dynamic_replicator_driver, &replicator_driver); + return coresight_init_driver("replicator", &dynamic_replicator_driver, &replicator_driver, + THIS_MODULE); } static void __exit replicator_exit(void) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 117dbb484543..403eea8f95d4 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -1046,7 +1046,7 @@ static struct platform_driver stm_platform_driver = { static int __init stm_init(void) { - return coresight_init_driver("stm", &stm_driver, &stm_platform_driver); + return coresight_init_driver("stm", &stm_driver, &stm_platform_driver, THIS_MODULE); } static void __exit stm_exit(void) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index b54562f392f3..e31e36635394 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -742,7 +742,7 @@ static struct platform_driver tmc_platform_driver = { static int __init tmc_init(void) { - return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver); + return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver, THIS_MODULE); } static void __exit tmc_exit(void) diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index b048e146fbb1..f9ecd05cbe5c 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -318,7 +318,7 @@ static struct platform_driver tpiu_platform_driver = { static int __init tpiu_init(void) { - return coresight_init_driver("tpiu", &tpiu_driver, &tpiu_platform_driver); + return coresight_init_driver("tpiu", &tpiu_driver, &tpiu_platform_driver, THIS_MODULE); } static void __exit tpiu_exit(void) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f09ace92176e..e6c26952ddc2 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -660,7 +660,7 @@ coresight_find_output_type(struct coresight_platform_data *pdata, union coresight_dev_subtype subtype); int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, - struct platform_driver *pdev_drv); + struct platform_driver *pdev_drv, struct module *owner); void coresight_remove_driver(struct amba_driver *amba_drv, struct platform_driver *pdev_drv); -- 2.33.0

1 month

[PATCH v4] coresight: Add a KUnit test for coresight_find_default_sink()

by James Clark

Add a test to confirm that default sink selection skips over an ETF and returns an ETR even if it's further away. This also makes it easier to add new unit tests in the future. Reviewed-by: Leo Yan <leo.yan(a)arm.com> Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v4: - Rename etm to src now that it's not CORESIGHT_DEV_SUBTYPE_SOURCE_PROC - Remove the now empty src_ops too - Fix a rebase mistake in the Makefile that removed CTCU - Link to v3: https://lore.kernel.org/r/20250312-james-cs-kunit-test-v3-1-dcfb69730161@li… Changes in v3: - Use CORESIGHT_DEV_SUBTYPE_SOURCE_BUS type instead of the default (CORESIGHT_DEV_SUBTYPE_SOURCE_PROC) so that the test still works even when TRBE sinks are registered. This also removes the need for the fake CPU ID callback. - Link to v2: https://lore.kernel.org/r/20250305-james-cs-kunit-test-v2-1-83ba682b976c@li… Changes in v2: - Let devm free everything rather than doing individual kfrees: "Like with managed drivers, KUnit-managed fake devices are automatically cleaned up when the test finishes, but can be manually cleaned up early with kunit_device_unregister()." - Link to v1: https://lore.kernel.org/r/20250225164639.522741-1-james.clark@linaro.org --- drivers/hwtracing/coresight/Kconfig | 9 +++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 1 + .../hwtracing/coresight/coresight-kunit-tests.c | 74 ++++++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ecd7086a5b83..f064e3d172b3 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -259,4 +259,13 @@ config CORESIGHT_DUMMY To compile this driver as a module, choose M here: the module will be called coresight-dummy. + +config CORESIGHT_KUNIT_TESTS + tristate "Enable Coresight unit tests" + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable Coresight unit tests. Only useful for development and not + intended for production. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 8e62c3150aeb..4e6ea5b05b01 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o coresight-ctcu-y := coresight-ctcu-core.o +obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index fb43ef6a3b1f..47af75ba7a00 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -959,6 +959,7 @@ coresight_find_default_sink(struct coresight_device *csdev) } return csdev->def_sink; } +EXPORT_SYMBOL_GPL(coresight_find_default_sink); static int coresight_remove_sink_ref(struct device *dev, void *data) { diff --git a/drivers/hwtracing/coresight/coresight-kunit-tests.c b/drivers/hwtracing/coresight/coresight-kunit-tests.c new file mode 100644 index 000000000000..c8f361767c45 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-kunit-tests.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <kunit/test.h> +#include <kunit/device.h> +#include <linux/coresight.h> + +#include "coresight-priv.h" + +static struct coresight_device *coresight_test_device(struct device *dev) +{ + struct coresight_device *csdev = devm_kcalloc(dev, 1, + sizeof(struct coresight_device), + GFP_KERNEL); + csdev->pdata = devm_kcalloc(dev, 1, + sizeof(struct coresight_platform_data), + GFP_KERNEL); + return csdev; +} + +static void test_default_sink(struct kunit *test) +{ + /* + * Source -> ETF -> ETR -> CATU + * ^ + * | default + */ + struct device *dev = kunit_device_register(test, "coresight_kunit"); + struct coresight_device *src = coresight_test_device(dev), + *etf = coresight_test_device(dev), + *etr = coresight_test_device(dev), + *catu = coresight_test_device(dev); + struct coresight_connection conn = {}; + + src->type = CORESIGHT_DEV_TYPE_SOURCE; + /* + * Don't use CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, that would always return + * a TRBE sink if one is registered. + */ + src->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_BUS; + etf->type = CORESIGHT_DEV_TYPE_LINKSINK; + etf->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + etr->type = CORESIGHT_DEV_TYPE_SINK; + etr->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; + catu->type = CORESIGHT_DEV_TYPE_HELPER; + + conn.src_dev = src; + conn.dest_dev = etf; + coresight_add_out_conn(dev, src->pdata, &conn); + + conn.src_dev = etf; + conn.dest_dev = etr; + coresight_add_out_conn(dev, etf->pdata, &conn); + + conn.src_dev = etr; + conn.dest_dev = catu; + coresight_add_out_conn(dev, etr->pdata, &conn); + + KUNIT_ASSERT_PTR_EQ(test, coresight_find_default_sink(src), etr); +} + +static struct kunit_case coresight_testcases[] = { + KUNIT_CASE(test_default_sink), + {} +}; + +static struct kunit_suite coresight_test_suite = { + .name = "coresight_test_suite", + .test_cases = coresight_testcases, +}; + +kunit_test_suites(&coresight_test_suite); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("James Clark <james.clark(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight KUnit tests"); --- base-commit: 3eadce8308bc8d808fd9e3a9d211c84215087451 change-id: 20250305-james-cs-kunit-test-3af1df2401e6 Best regards, -- James Clark <james.clark(a)linaro.org>

1 month

Re: [PATCH next] Coresight: Fix a NULL vs IS_ERR() bug in probe

by Suzuki K Poulose

On Fri, 14 Mar 2025 13:55:10 +0300, Dan Carpenter wrote: > The devm_platform_get_and_ioremap_resource() function doesn't > return NULL, it returns error pointers. Update the checking to > match. > > Applied, thanks! [1/1] Coresight: Fix a NULL vs IS_ERR() bug in probe (no commit info) Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 month

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