CoreSight

coresight@lists.linaro.org

6 participants
2800 discussions

Re: [PATCH v10 0/5] Add Qualcomm extended CTI support

by Leo Yan

On Mon, Jun 15, 2026 at 08:32:28PM +0800, Yingchao Deng wrote: > The Qualcomm extended CTI is a heavily parameterized version of ARM’s > CSCTI. It allows a debugger to send to trigger events to a processor or to > send a trigger event to one or more processors when a trigger event occurs > on another processor on the same SoC, or even between SoCs. > > Qualcomm extended CTI supports up to 128 triggers. And some of the register > offsets are changed. > > The commands to configure CTI triggers are the same as ARM's CTI. This series looks good to me and I tested: - Confirmed no any change for standard CTI; - Perf command; - Build bisection. Tested-by: Leo Yan <leo.yan(a)arm.com> Mike may also want to take a look in case there is any overlap with his claim tags init patch [1]. I don't have a strong preference on which series goes in first, as the claim tag handling in this series looks clean enough to me. @Yingchao, just a small suggestion: rc1–rc4 is usually the best window for getting patches merged. If you receive comments and are able to address them quickly, it may be worth respin patches during that period to try catching the next merge window. This is no guarantees, just thought it might be useful to share as a general tip :) [1] https://lore.kernel.org/linux-arm-kernel/20260619160148.499223-2-mike.leach…

3 weeks, 4 days

[PATCH v9 0/9] perf cs-etm: Support thread stack and callchain

by Leo Yan

This series adds thread-stack and synthesized callchain support for Arm CoreSight, which comes from older series [1] but heavily rewritten. CS ETM previously kept last-branch state in a per-trace-queue buffer. That effectively makes the state per CPU, while the call/return history belongs to a thread. This series moves branch tracking to the common thread-stack code. The series records CoreSight branches with thread_stack__event(), uses thread_stack__br_sample() for last branch entries, flushes thread stacks after decoder resets. A decoder reset between AUX trace buffers is treated as a global trace discontinuity, so all thread stacks are flushed, so avoids carrying stale call/return history across a trace discontinuity. One limitation remains for instructions emulated by the kernel. In that case the exception return address may not match the return address stored in the thread stack, because after exception return can be one instruction ahead. The stack can still recover when a later return matches an upper caller. Given emulated instructions are not the common target for performance callchain analysis. Supporting this would require extending the common thread-stack path to accept both the real target address and an adjusted address for stack matching, so this series leaves that extra complexity out. The series has been tested on Orion6 board: perf test 136 -vvv 136: CoreSight synthesized callchain: --- start --- test child forked, pid 3539 ---- end(0) ---- 136: CoreSight synthesized callchain : Ok perf script --itrace=g16i10il64 callchain_test 17468 [005] 1031003.229943: 10 instructions: aaaac32507c4 main+0x8 (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) callchain_test 17468 [005] 1031003.229943: 10 instructions: aaaac3250774 do_svc+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac3250798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) callchain_test 17468 [005] 1031003.229944: 10 instructions: ffff800080010c20 vectors+0x420 ([kernel.kallsyms]) aaaac3250784 do_svc+0x1c (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac3250798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) Note, the test fails on Juno board which is caused by many discontinuity packets (mainly caused by NO_SYNC elem). This is likely caused by the FIFO overflow on the path. [1] https://lore.kernel.org/linux-arm-kernel/20200220052701.7754-1-leo.yan@lina… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v9: - Added patch 01 to fixed thread leak during trace queue init (sashiko). - Added check in instruction and branch samples in cs_etm__add_stack_event() (sashiko). - Released frontend_thread properly in cs_etm__context() (sashiko). - Refined cs_etm__flush_all_stack() to use switch (sashiko). - Gathered James' review tags. - Rebased on the latest perf-tools-next. - Link to v8: https://lore.kernel.org/r/20260611-b4-arm_cs_callchain_support_v1-v8-0-7379… Changes in v8: - Updated test_arm_coresight_disasm.sh to pass "--itrace=b" and updated examples in arm-cs-trace-disasm.py (James). - Removed static annotation in callchain workload and renamed functions with prefix "callchain_" to reduce naming conflict (James). - For callchain test pre-condition check, removed the aarch64 check and added the root permission check (James). - Resolved the shellcheck errors (James). - Link to v7: https://lore.kernel.org/r/20260611-b4-arm_cs_callchain_support_v1-v7-0-1ba7… Changes in v7: - Rebased on the latest perf-tools-next. - Used struct_size() for allocation callchain struct (James). - Added a helper cs_etm__packet_has_taken_branch() (James). - Minor improvements for the callchain test (used record-ctl FIFO and reworked the validation callstack push / pop). - Link to v6: https://lore.kernel.org/r/20260526-b4-arm_cs_callchain_support_v1-v6-0-f9f4… Changes in v6: - Heavily rewrote the patches since restarted the work after 6 years. - Changed to use the common thread-stack for branch stack and callchain management. - Added a callchain test. - Link to v5: https://lore.kernel.org/linux-arm-kernel/20200220052701.7754-1-leo.yan@lina… Changes in v5: - Addressed Mike's suggestion for performance improvement for function cs_etm__instr_addr() for quick calculation for non T32; - Removed the patch 'perf cs-etm: Synchronize instruction sample with the thread stack' (Mike); - Fixed the issue for exception is taken for branch target address accessing, for the branch sample and stack thread handling, the related patches are 01, 02, 07; - Fixed the stack thread handling for instruction emulation and single step with patches 08, 09. - Link to v4: https://lore.kernel.org/linux-arm-kernel/20200203020716.31832-1-leo.yan@lin… --- Leo Yan (9): perf cs-etm: Fix thread leaks on trace queue init failure perf cs-etm: Filter synthesized branch samples perf cs-etm: Decode ETE exception packets perf cs-etm: Refactor instruction size handling perf cs-etm: Use thread-stack for last branch entries perf cs-etm: Flush thread stacks after decoder reset perf cs-etm: Support call indentation perf cs-etm: Synthesize callchains for instruction samples perf test: Add Arm CoreSight callchain test tools/perf/Documentation/perf-test.txt | 6 +- tools/perf/scripts/python/arm-cs-trace-disasm.py | 9 +- tools/perf/tests/builtin-test.c | 1 + tools/perf/tests/shell/coresight/callchain.sh | 172 ++++++++++ .../shell/coresight/test_arm_coresight_disasm.sh | 4 +- tools/perf/tests/tests.h | 1 + tools/perf/tests/workloads/Build | 2 + tools/perf/tests/workloads/callchain.c | 33 ++ tools/perf/util/cs-etm.c | 367 +++++++++++++-------- 9 files changed, 446 insertions(+), 149 deletions(-) --- base-commit: 44543bb53ebfecb5ce4e890053a666affab9e482 change-id: 20260521-b4-arm_cs_callchain_support_v1-2c2a70719bcc Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 month

[PATCH v8 0/8] perf cs-etm: Support thread stack and callchain

by Leo Yan

This series adds thread-stack and synthesized callchain support for Arm CoreSight, which comes from older series [1] but heavily rewritten. CS ETM previously kept last-branch state in a per-trace-queue buffer. That effectively makes the state per CPU, while the call/return history belongs to a thread. This series moves branch tracking to the common thread-stack code. The series records CoreSight branches with thread_stack__event(), uses thread_stack__br_sample() for last branch entries, flushes thread stacks after decoder resets. A decoder reset between AUX trace buffers is treated as a global trace discontinuity, so all thread stacks are flushed, so avoids carrying stale call/return history across a trace discontinuity. One limitation remains for instructions emulated by the kernel. In that case the exception return address may not match the return address stored in the thread stack, because after exception return can be one instruction ahead. The stack can still recover when a later return matches an upper caller. Given emulated instructions are not the common target for performance callchain analysis. Supporting this would require extending the common thread-stack path to accept both the real target address and an adjusted address for stack matching, so this series leaves that extra complexity out. The series has been tested on Orion6 board: perf test 136 -vvv 136: CoreSight synthesized callchain: --- start --- test child forked, pid 3539 ---- end(0) ---- 136: CoreSight synthesized callchain : Ok perf script --itrace=g16i10il64 callchain_test 17468 [005] 1031003.229943: 10 instructions: aaaac32507c4 main+0x8 (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) callchain_test 17468 [005] 1031003.229943: 10 instructions: aaaac3250774 do_svc+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac3250798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) callchain_test 17468 [005] 1031003.229944: 10 instructions: ffff800080010c20 vectors+0x420 ([kernel.kallsyms]) aaaac3250784 do_svc+0x1c (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac3250798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) Note, the test fails on Juno board which is caused by many discontinuity packets (mainly caused by NO_SYNC elem). This is likely caused by the FIFO overflow on the path. [1] https://lore.kernel.org/linux-arm-kernel/20200220052701.7754-1-leo.yan@lina… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v8: - Updated test_arm_coresight_disasm.sh to pass "--itrace=b" and updated examples in arm-cs-trace-disasm.py (James). - Removed static annotation in callchain workload and renamed functions with prefix "callchain_" to reduce naming conflict (James). - For callchain test pre-condition check, removed the aarch64 check and added the root permission check (James). - Resolved the shellcheck errors (James). - Link to v7: https://lore.kernel.org/r/20260611-b4-arm_cs_callchain_support_v1-v7-0-1ba7… Changes in v7: - Rebased on the latest perf-tools-next. - Used struct_size() for allocation callchain struct (James). - Added a helper cs_etm__packet_has_taken_branch() (James). - Minor improvements for the callchain test (used record-ctl FIFO and reworked the validation callstack push / pop). - Link to v6: https://lore.kernel.org/r/20260526-b4-arm_cs_callchain_support_v1-v6-0-f9f4… Changes in v6: - Heavily rewrote the patches since restarted the work after 6 years. - Changed to use the common thread-stack for branch stack and callchain management. - Added a callchain test. - Link to v5: https://lore.kernel.org/linux-arm-kernel/20200220052701.7754-1-leo.yan@lina… Changes in v5: - Addressed Mike's suggestion for performance improvement for function cs_etm__instr_addr() for quick calculation for non T32; - Removed the patch 'perf cs-etm: Synchronize instruction sample with the thread stack' (Mike); - Fixed the issue for exception is taken for branch target address accessing, for the branch sample and stack thread handling, the related patches are 01, 02, 07; - Fixed the stack thread handling for instruction emulation and single step with patches 08, 09. - Link to v4: https://lore.kernel.org/linux-arm-kernel/20200203020716.31832-1-leo.yan@lin… Changes in v4: - Split out separate patch set for instruction samples fixing. - Rebased on latest perf/core branch. - Link to v3: https://lore.kernel.org/linux-arm-kernel/20191005091614.11635-1-leo.yan@lin… --- Leo Yan (8): perf cs-etm: Filter synthesized branch samples perf cs-etm: Decode ETE exception packets perf cs-etm: Refactor instruction size handling perf cs-etm: Use thread-stack for last branch entries perf cs-etm: Flush thread stacks after decoder reset perf cs-etm: Support call indentation perf cs-etm: Synthesize callchains for instruction samples perf test: Add Arm CoreSight callchain test tools/perf/Documentation/perf-test.txt | 6 +- tools/perf/scripts/python/arm-cs-trace-disasm.py | 9 +- tools/perf/tests/builtin-test.c | 1 + tools/perf/tests/shell/coresight/callchain.sh | 172 ++++++++++ .../shell/coresight/test_arm_coresight_disasm.sh | 4 +- tools/perf/tests/tests.h | 1 + tools/perf/tests/workloads/Build | 2 + tools/perf/tests/workloads/callchain.c | 33 ++ tools/perf/util/cs-etm.c | 351 ++++++++++++--------- 9 files changed, 430 insertions(+), 149 deletions(-) --- base-commit: 7336514f41e75d44782fee7e0990d4195a3d3161 change-id: 20260521-b4-arm_cs_callchain_support_v1-2c2a70719bcc Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 month, 1 week

[PATCH v7 0/8] perf cs-etm: Support thread stack and callchain

by Leo Yan

This series adds thread-stack and synthesized callchain support for Arm CoreSight, which comes from older series [1] but heavily rewritten. CS ETM previously kept last-branch state in a per-trace-queue buffer. That effectively makes the state per CPU, while the call/return history belongs to a thread. This series moves branch tracking to the common thread-stack code. The series records CoreSight branches with thread_stack__event(), uses thread_stack__br_sample() for last branch entries, flushes thread stacks after decoder resets. A decoder reset between AUX trace buffers is treated as a global trace discontinuity, so all thread stacks are flushed, so avoids carrying stale call/return history across a trace discontinuity. One limitation remains for instructions emulated by the kernel. In that case the exception return address may not match the return address stored in the thread stack, because after exception return can be one instruction ahead. The stack can still recover when a later return matches an upper caller. Given emulated instructions are not the common target for performance callchain analysis. Supporting this would require extending the common thread-stack path to accept both the real target address and an adjusted address for stack matching, so this series leaves that extra complexity out. The series has been tested on Orion6 board: perf test 136 -vvv 136: CoreSight synthesized callchain: --- start --- test child forked, pid 3539 ---- end(0) ---- 136: CoreSight synthesized callchain : Ok perf script --itrace=g16i10il64 callchain_test 17468 [005] 1031003.229943: 10 instructions: aaaac32507c4 main+0x8 (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) callchain_test 17468 [005] 1031003.229943: 10 instructions: aaaac3250774 do_svc+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac3250798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) callchain_test 17468 [005] 1031003.229944: 10 instructions: ffff800080010c20 vectors+0x420 ([kernel.kallsyms]) aaaac3250784 do_svc+0x1c (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac3250798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) aaaac32507c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test) ffff90bd225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6) ffff90bd233c call_init+0x9c (inlined) ffff90bd233c __libc_start_main_impl+0x9c (inlined) aaaac3250670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test) Note, the test fails on Juno board which is caused by many discontinuity packets (mainly caused by NO_SYNC elem). This is likely caused by the FIFO overflow on the path. [1] https://lore.kernel.org/linux-arm-kernel/20200220052701.7754-1-leo.yan@lina… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v7: - Rebased on the latest perf-tools-next. - Used struct_size() for allocation callchain struct (James). - Added a helper cs_etm__packet_has_taken_branch() (James). - Minor improvements for the callchain test (used record-ctl FIFO and reworked the validation callstack push / pop). - Link to v6: https://lore.kernel.org/r/20260526-b4-arm_cs_callchain_support_v1-v6-0-f9f4… Changes in v6: - Heavily rewrote the patches since restarted the work after 6 years. - Changed to use the common thread-stack for branch stack and callchain management. - Added a callchain test. - Link to v5: https://lore.kernel.org/linux-arm-kernel/20200220052701.7754-1-leo.yan@lina… Changes in v5: - Addressed Mike's suggestion for performance improvement for function cs_etm__instr_addr() for quick calculation for non T32; - Removed the patch 'perf cs-etm: Synchronize instruction sample with the thread stack' (Mike); - Fixed the issue for exception is taken for branch target address accessing, for the branch sample and stack thread handling, the related patches are 01, 02, 07; - Fixed the stack thread handling for instruction emulation and single step with patches 08, 09. - Link to v4: https://lore.kernel.org/linux-arm-kernel/20200203020716.31832-1-leo.yan@lin… Changes in v4: - Split out separate patch set for instruction samples fixing. - Rebased on latest perf/core branch. - Link to v3: https://lore.kernel.org/linux-arm-kernel/20191005091614.11635-1-leo.yan@lin… --- Leo Yan (8): perf cs-etm: Filter synthesized branch samples perf cs-etm: Decode ETE exception packets perf cs-etm: Refactor instruction size handling perf cs-etm: Use thread-stack for last branch entries perf cs-etm: Flush thread stacks after decoder reset perf cs-etm: Support call indentation perf cs-etm: Synthesize callchains for instruction samples perf test: Add Arm CoreSight callchain test tools/perf/Documentation/perf-test.txt | 6 +- tools/perf/tests/builtin-test.c | 1 + tools/perf/tests/shell/coresight/callchain.sh | 168 ++++++++++++ tools/perf/tests/tests.h | 1 + tools/perf/tests/workloads/Build | 2 + tools/perf/tests/workloads/callchain.c | 24 ++ tools/perf/util/cs-etm.c | 351 +++++++++++++++----------- 7 files changed, 410 insertions(+), 143 deletions(-) --- base-commit: 7336514f41e75d44782fee7e0990d4195a3d3161 change-id: 20260521-b4-arm_cs_callchain_support_v1-2c2a70719bcc Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 month, 1 week

[PATCH v5 00/19] perf cs-etm: Queue context packets for frontend

by James Clark

Fix thread tracking when decoding Coresight trace and add a new test for it. The new test is added as a Perf test workload instead of a custom binary with its own build system, but this requires a new feature in Perf test to pass in control pipes which can enable and disable events. This scopes the recording to just the workload and helps to reduce the amount of data recorded in tracing tests. With this new feature we can re-write all of the Coresight tests to make use of it and remove the remaining binaries which fixes the following issues: * They didn't work in out of source builds * A lot of the tests unnecessarily required root and didn't skip without it * They were mainly qualitative tests which didn't look for specific behavior Most importantly, the long build and runtime has been reduced. On a Radxa Orion O6, unroll_loop_thread.c took 37s to compile which is longer than the entire Perf build. Now the build time is negligible and the before and after test runtimes for all the Coresight tests are: | N1SDP | Orion O6 ----------------------------------- Before | 4m 0s | 14m 49s After | 26s | 56s ----------------------------------- Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v5: - Forgot to include this change: - Test for actual length of expected raw dump (Leo) - Link to v4: https://lore.kernel.org/r/20260609-james-cs-context-tracking-fix-v4-0-44f9f… Changes in v4: - Rename workload-ctl to record-ctl and improve docs (Leo) - Use new packet argument everywhere in cs_etm__synth_instruction_sample() (Sashiko) - Test for actual length of expected raw dump (Leo) - Use -fno-inline instead of keyword (Leo) - Don't test any brace or call lines in deterministic test - Make sure context switch loop test does cleanup on failure (Sashiko) - Remove undef int overflows in workloads (Sashiko) - Link to v3: https://lore.kernel.org/r/20260603-james-cs-context-tracking-fix-v3-0-c3929… Changes in v3: - Minor sashiko comments - Close some more pipes - Fix warning messages - Error handling improvements - Pass packet into cs_etm__synth_instruction_sample() - Fixup stale comment (Leo) - Link to v2: https://lore.kernel.org/r/20260602-james-cs-context-tracking-fix-v2-0-85b5c… Changes in v2: - Add --workload-ctl option to Perf test - Re-write all the Coresight tests and speed them up - Pass packet to memory access function so frontend can use either the previous or current packet's EL - Link to v1: https://lore.kernel.org/r/20260526-james-cs-context-tracking-fix-v1-0-ebd60… --- James Clark (19): perf cs-etm: Queue context packets for frontend perf test: Add workload-ctl option perf test: Add a workload that forces context switches perf test cs-etm: Test process attribution perf test: Add deterministic workload perf test cs-etm: Replace unroll loop thread with deterministic decode test perf test cs-etm: Remove asm_pure_loop test perf test cs-etm: Replace memcpy test with raw dump stress test perf test: Add named_threads workload perf test cs-etm: Test decoding for concurrent threads test perf test cs-etm: Remove duplicate branch tests perf test cs-etm: Skip if not root perf test cs-etm: Reduce snapshot size perf test cs-etm: Speed up basic test perf test cs-etm: Remove unused Coresight workloads perf test cs-etm: Make disassembly test use kcore perf test cs-etm: Add all branch instructions to test perf test cs-etm: Speed up disassembly test perf test cs-etm: Move existing tests to coresight folder Documentation/trace/coresight/coresight-perf.rst | 78 +------ MAINTAINERS | 2 - tools/perf/Documentation/perf-test.txt | 24 ++- tools/perf/Makefile.perf | 14 +- tools/perf/scripts/python/arm-cs-trace-disasm.py | 20 +- tools/perf/tests/builtin-test.c | 187 +++++++++++++++- tools/perf/tests/shell/coresight/Makefile | 29 --- .../perf/tests/shell/coresight/Makefile.miniconfig | 14 -- tools/perf/tests/shell/coresight/asm_pure_loop.sh | 22 -- .../tests/shell/coresight/asm_pure_loop/.gitignore | 1 - .../tests/shell/coresight/asm_pure_loop/Makefile | 34 --- .../shell/coresight/asm_pure_loop/asm_pure_loop.S | 30 --- .../tests/shell/coresight/concurrent_threads.sh | 45 ++++ .../tests/shell/coresight/context_switch_thread.sh | 69 ++++++ tools/perf/tests/shell/coresight/deterministic.sh | 72 +++++++ .../tests/shell/coresight/memcpy_thread/.gitignore | 1 - .../tests/shell/coresight/memcpy_thread/Makefile | 33 --- .../shell/coresight/memcpy_thread/memcpy_thread.c | 80 ------- .../tests/shell/coresight/memcpy_thread_16k_10.sh | 22 -- .../perf/tests/shell/coresight/raw_dump_stress.sh | 65 ++++++ .../shell/{ => coresight}/test_arm_coresight.sh | 43 ++-- .../{ => coresight}/test_arm_coresight_disasm.sh | 23 +- .../tests/shell/coresight/thread_loop/.gitignore | 1 - .../tests/shell/coresight/thread_loop/Makefile | 33 --- .../shell/coresight/thread_loop/thread_loop.c | 85 -------- .../shell/coresight/thread_loop_check_tid_10.sh | 23 -- .../shell/coresight/thread_loop_check_tid_2.sh | 23 -- .../shell/coresight/unroll_loop_thread/.gitignore | 1 - .../shell/coresight/unroll_loop_thread/Makefile | 33 --- .../unroll_loop_thread/unroll_loop_thread.c | 75 ------- .../tests/shell/coresight/unroll_loop_thread_10.sh | 22 -- tools/perf/tests/shell/lib/coresight.sh | 134 ------------ tools/perf/tests/tests.h | 3 + tools/perf/tests/workloads/Build | 4 + tools/perf/tests/workloads/context_switch_loop.c | 110 ++++++++++ tools/perf/tests/workloads/deterministic.c | 39 ++++ tools/perf/tests/workloads/named_threads.c | 109 ++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 21 +- tools/perf/util/cs-etm.c | 236 ++++++++++++--------- tools/perf/util/cs-etm.h | 8 +- 40 files changed, 926 insertions(+), 942 deletions(-) --- base-commit: 351a37f2fda4db668cff8ba12f2992d73dccdaea change-id: 20260515-james-cs-context-tracking-fix-754998bae7ed Best regards, -- James Clark <james.clark(a)linaro.org>

1 month, 1 week

[PATCH v4 00/19] perf cs-etm: Queue context packets for frontend

by James Clark

Fix thread tracking when decoding Coresight trace and add a new test for it. The new test is added as a Perf test workload instead of a custom binary with its own build system, but this requires a new feature in Perf test to pass in control pipes which can enable and disable events. This scopes the recording to just the workload and helps to reduce the amount of data recorded in tracing tests. With this new feature we can re-write all of the Coresight tests to make use of it and remove the remaining binaries which fixes the following issues: * They didn't work in out of source builds * A lot of the tests unnecessarily required root and didn't skip without it * They were mainly qualitative tests which didn't look for specific behavior Most importantly, the long build and runtime has been reduced. On a Radxa Orion O6, unroll_loop_thread.c took 37s to compile which is longer than the entire Perf build. Now the build time is negligible and the before and after test runtimes for all the Coresight tests are: | N1SDP | Orion O6 ----------------------------------- Before | 4m 0s | 14m 49s After | 26s | 56s ----------------------------------- Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v4: - Rename workload-ctl to record-ctl and improve docs (Leo) - Use new packet argument everywhere in cs_etm__synth_instruction_sample() (Sashiko) - Test for actual length of expected raw dump (Leo) - Use -fno-inline instead of keyword (Leo) - Don't test any brace or call lines in deterministic test - Make sure context switch loop test does cleanup on failure (Sashiko) - Remove undef int overflows in workloads (Sashiko) - Link to v3: https://lore.kernel.org/r/20260603-james-cs-context-tracking-fix-v3-0-c3929… Changes in v3: - Minor sashiko comments - Close some more pipes - Fix warning messages - Error handling improvements - Pass packet into cs_etm__synth_instruction_sample() - Fixup stale comment (Leo) - Link to v2: https://lore.kernel.org/r/20260602-james-cs-context-tracking-fix-v2-0-85b5c… Changes in v2: - Add --workload-ctl option to Perf test - Re-write all the Coresight tests and speed them up - Pass packet to memory access function so frontend can use either the previous or current packet's EL - Link to v1: https://lore.kernel.org/r/20260526-james-cs-context-tracking-fix-v1-0-ebd60… --- James Clark (19): perf cs-etm: Queue context packets for frontend perf test: Add workload-ctl option perf test: Add a workload that forces context switches perf test cs-etm: Test process attribution perf test: Add deterministic workload perf test cs-etm: Replace unroll loop thread with deterministic decode test perf test cs-etm: Remove asm_pure_loop test perf test cs-etm: Replace memcpy test with raw dump stress test perf test: Add named_threads workload perf test cs-etm: Test decoding for concurrent threads test perf test cs-etm: Remove duplicate branch tests perf test cs-etm: Skip if not root perf test cs-etm: Reduce snapshot size perf test cs-etm: Speed up basic test perf test cs-etm: Remove unused Coresight workloads perf test cs-etm: Make disassembly test use kcore perf test cs-etm: Add all branch instructions to test perf test cs-etm: Speed up disassembly test perf test cs-etm: Move existing tests to coresight folder Documentation/trace/coresight/coresight-perf.rst | 78 +------ MAINTAINERS | 2 - tools/perf/Documentation/perf-test.txt | 24 ++- tools/perf/Makefile.perf | 14 +- tools/perf/scripts/python/arm-cs-trace-disasm.py | 20 +- tools/perf/tests/builtin-test.c | 187 +++++++++++++++- tools/perf/tests/shell/coresight/Makefile | 29 --- .../perf/tests/shell/coresight/Makefile.miniconfig | 14 -- tools/perf/tests/shell/coresight/asm_pure_loop.sh | 22 -- .../tests/shell/coresight/asm_pure_loop/.gitignore | 1 - .../tests/shell/coresight/asm_pure_loop/Makefile | 34 --- .../shell/coresight/asm_pure_loop/asm_pure_loop.S | 30 --- .../tests/shell/coresight/concurrent_threads.sh | 45 ++++ .../tests/shell/coresight/context_switch_thread.sh | 69 ++++++ tools/perf/tests/shell/coresight/deterministic.sh | 72 +++++++ .../tests/shell/coresight/memcpy_thread/.gitignore | 1 - .../tests/shell/coresight/memcpy_thread/Makefile | 33 --- .../shell/coresight/memcpy_thread/memcpy_thread.c | 80 ------- .../tests/shell/coresight/memcpy_thread_16k_10.sh | 22 -- .../perf/tests/shell/coresight/raw_dump_stress.sh | 47 ++++ .../shell/{ => coresight}/test_arm_coresight.sh | 43 ++-- .../{ => coresight}/test_arm_coresight_disasm.sh | 23 +- .../tests/shell/coresight/thread_loop/.gitignore | 1 - .../tests/shell/coresight/thread_loop/Makefile | 33 --- .../shell/coresight/thread_loop/thread_loop.c | 85 -------- .../shell/coresight/thread_loop_check_tid_10.sh | 23 -- .../shell/coresight/thread_loop_check_tid_2.sh | 23 -- .../shell/coresight/unroll_loop_thread/.gitignore | 1 - .../shell/coresight/unroll_loop_thread/Makefile | 33 --- .../unroll_loop_thread/unroll_loop_thread.c | 75 ------- .../tests/shell/coresight/unroll_loop_thread_10.sh | 22 -- tools/perf/tests/shell/lib/coresight.sh | 134 ------------ tools/perf/tests/tests.h | 3 + tools/perf/tests/workloads/Build | 4 + tools/perf/tests/workloads/context_switch_loop.c | 110 ++++++++++ tools/perf/tests/workloads/deterministic.c | 39 ++++ tools/perf/tests/workloads/named_threads.c | 109 ++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 21 +- tools/perf/util/cs-etm.c | 236 ++++++++++++--------- tools/perf/util/cs-etm.h | 8 +- 40 files changed, 908 insertions(+), 942 deletions(-) --- base-commit: 351a37f2fda4db668cff8ba12f2992d73dccdaea change-id: 20260515-james-cs-context-tracking-fix-754998bae7ed Best regards, -- James Clark <james.clark(a)linaro.org>

1 month, 1 week

Re: [PATCH v3] coresight: etm3x: Fix cntr_val_show() to match cntr_val_store() behavior

by Suzuki K Poulose

On 08/06/2026 17:55, Kuan-Wei Chiu wrote: > Hi Suzuki, > > On Fri, Apr 03, 2026 at 04:57:59PM +0800, Kuan-Wei Chiu wrote: >> Hi Suzuki, >> >> On Mon, Feb 02, 2026 at 09:33:59AM +0000, Suzuki K Poulose wrote: >>> Hello >>> >>> On 02/02/2026 05:09, Kuan-Wei Chiu wrote: >>>> On Tue, Dec 02, 2025 at 09:26:19AM +0000, James Clark wrote: >>>>> >>>>> >>>>> On 02/12/2025 8:26 am, Kuan-Wei Chiu wrote: >>>>>> The cntr_val_show() function was intended to print the values of all >>>>>> counters using a loop. However, due to a buffer overwrite issue with >>>>>> sprintf(), it effectively only displayed the value of the last counter. >>>>>> >>>>>> The companion function, cntr_val_store(), allows users to modify a >>>>>> specific counter selected by 'cntr_idx'. To maintain consistency >>>>>> between read and write operations and to align with the ETM4x driver >>>>>> behavior, modify cntr_val_show() to report only the value of the >>>>>> currently selected counter. >>>>>> >>>>>> This change removes the loop and the "counter %d:" prefix, printing >>>>>> only the hexadecimal value. It also adopts sysfs_emit() for standard >>>>>> sysfs output formatting. >>>>>> >>>>>> Fixes: a939fc5a71ad ("coresight-etm: add CoreSight ETM/PTM driver") >>>>>> Cc: stable(a)vger.kernel.org >>>>>> Signed-off-by: Kuan-Wei Chiu <visitorckw(a)gmail.com> >>>>>> --- >>>>>> Build test only. >>>>>> >>>>>> Changes in v3: >>>>>> - Switch format specifier to %#x to include the 0x prefix. >>>>>> - Add Cc stable >>>>>> >>>>>> v2: https://lore.kernel.org/lkml/20251201095228.1905489-1-visitorckw@gmail.com/ >>>>>> >>>>>> .../hwtracing/coresight/coresight-etm3x-sysfs.c | 15 ++++----------- >>>>>> 1 file changed, 4 insertions(+), 11 deletions(-) >>>>>> >>>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c >>>>>> index 762109307b86..b3c67e96a82a 100644 >>>>>> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c >>>>>> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c >>>>>> @@ -717,26 +717,19 @@ static DEVICE_ATTR_RW(cntr_rld_event); >>>>>> static ssize_t cntr_val_show(struct device *dev, >>>>>> struct device_attribute *attr, char *buf) >>>>>> { >>>>>> - int i, ret = 0; >>>>>> u32 val; >>>>>> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>>>> struct etm_config *config = &drvdata->config; >>>>>> if (!coresight_get_mode(drvdata->csdev)) { >>>>>> spin_lock(&drvdata->spinlock); >>>>>> - for (i = 0; i < drvdata->nr_cntr; i++) >>>>>> - ret += sprintf(buf, "counter %d: %x\n", >>>>>> - i, config->cntr_val[i]); >>>>>> + val = config->cntr_val[config->cntr_idx]; >>>>>> spin_unlock(&drvdata->spinlock); >>>>>> - return ret; >>>>>> - } >>>>>> - >>>>>> - for (i = 0; i < drvdata->nr_cntr; i++) { >>>>>> - val = etm_readl(drvdata, ETMCNTVRn(i)); >>>>>> - ret += sprintf(buf, "counter %d: %x\n", i, val); >>>>>> + } else { >>>>>> + val = etm_readl(drvdata, ETMCNTVRn(config->cntr_idx)); >>>>>> } >>>>>> - return ret; >>>>>> + return sysfs_emit(buf, "%#x\n", val); >>>>>> } >>>>>> static ssize_t cntr_val_store(struct device *dev, >>>>> >>>>> Reviewed-by: James Clark <james.clark(a)linaro.org> >>>>> >>>> Thanks for the review! >>>> Is there anything else I need to do for this fix to land? >>> >>> Thanks for the patch, I will queue this for the next release (v7.1). >>> >> Just a gentle ping. >> >> Since the v7.1 merge window is presumably opening in about a week, I >> noticed this patch isn't in linux-next yet and wanted to send a quick >> reminder. Thanks. >> > This patch still applies cleanly on top of linux-next. > I suspect this patch may have fallen through the cracks. > Would you still be willing to pick it up? Apologies, it did. I will pick this up, if we have sufficient fixes, I might send it as fixes for v7.2, otherwise , queue it for v7.3 Once again, apologies. Suzuki > > Regards, > Kuan-Wei

1 month, 1 week

[PATCH v6 0/8] perf cs-etm: Support thread stack and callchain

by Leo Yan

1 month, 1 week

[GIT PULL] coresight: Updates for Linux v7.2

by Suzuki K Poulose

Hi Greg Please find the updates for CoreSight self hosted tracing subsystem targeting Linux v7.2 Kindly pull, Suzuki --- The following changes since commit 7fd2df204f342fc17d1a0bfcd474b24232fb0f32: Linux 7.1-rc2 (2026-05-03 14:21:25 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v7.2 for you to fetch changes up to 98495b5a4d77dd22e106f462b76e1093a55b29a7: coresight: ultrasoc-smb: Fix OOB write in smb_sync_perf_buffer() (2026-06-04 09:56:13 +0100) ---------------------------------------------------------------- coresight: Self-hosted tracing updates for Linux v7.2 Updates for the CoreSight self hosted tracing subsystem includes: - Better power management for components based on the CPU PM, including support for components on the trace path for CPUs. Add support for save/restore for TRBE - Miscellaneous fixes to the drivers * Fix overflow when the buffer size is > 2GB for tmc-etr * Ultrasoc SMB Perf buffer OOB access Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- James Clark (1): coresight: ete: Always save state on power down Jie Gan (3): coresight: fix missing error code when trace ID is invalid coresight: Fix source not disabled on idr_alloc_u32 failure coresight: platform: defer connection counter increment until alloc succeeds Junrui Luo (1): coresight: ultrasoc-smb: Fix OOB write in smb_sync_perf_buffer() Leo Yan (28): coresight: tmc: Fix overflow when calculating is bigger than 2GiB coresight: etm4x: Correct TRCVMIDCCTLR1 save and restore coresight: Handle helper enable failure properly coresight: Extract device init into coresight_init_device() coresight: Populate CPU ID into coresight_device coresight: Remove .cpu_id() callback from source ops coresight: Take hotplug lock in enable_source_store() for Sysfs mode coresight: perf: Retrieve path and source from event data coresight: Take a reference on csdev coresight: Move per-CPU source pointer to core layer coresight: Take per-CPU source reference during AUX setup coresight: Register CPU PM notifier in core layer coresight: etm4x: Hook CPU PM callbacks coresight: etm4x: Remove redundant checks in PM save and restore coresight: syscfg: Use IRQ-safe spinlock to protect active variables coresight: Disable source helpers in coresight_disable_path() coresight: Control path with range coresight: Use helpers to fetch first and last nodes coresight: Introduce coresight_enable_source() helper coresight: Save active path for system tracers coresight: etm4x: Set active path on target CPU coresight: etm3x: Set active path on target CPU coresight: sysfs: Use source's path pointer for path control coresight: Control path during CPU idle coresight: Add PM callbacks for sink device coresight: sysfs: Increment refcount only for software source coresight: Move CPU hotplug callbacks to core layer coresight: sysfs: Validate CPU online status for per-CPU sources Runyu Xiao (1): coresight: etb10: restore atomic_t for shared reading state Yabin Cui (1): coresight: trbe: Save and restore state across CPU low power state Yingchao Deng (1): coresight: cti: Fix DT filter signals silently ignored drivers/hwtracing/coresight/coresight-catu.c | 2 +- drivers/hwtracing/coresight/coresight-core.c | 574 ++++++++++++++++++--- drivers/hwtracing/coresight/coresight-cti-core.c | 9 +- .../hwtracing/coresight/coresight-cti-platform.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 6 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 289 ++++++----- drivers/hwtracing/coresight/coresight-etm3x-core.c | 73 +-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 216 +++----- drivers/hwtracing/coresight/coresight-platform.c | 12 +- drivers/hwtracing/coresight/coresight-priv.h | 8 +- drivers/hwtracing/coresight/coresight-syscfg.c | 38 +- drivers/hwtracing/coresight/coresight-syscfg.h | 2 + drivers/hwtracing/coresight/coresight-sysfs.c | 135 ++--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 +- drivers/hwtracing/coresight/coresight-trbe.c | 61 ++- drivers/hwtracing/coresight/ultrasoc-smb.c | 1 + include/linux/coresight.h | 27 +- include/linux/cpuhotplug.h | 2 +- 18 files changed, 939 insertions(+), 521 deletions(-)

1 month, 1 week

[RFC PATCH 00/12] Add Linux RISC-V trace support via CoreSight

by Zane Leung

From: liangzhen <zhen.liang(a)spacemit.com> This series adds Linux RISC-V trace support via CoreSight, implementing RISC-V trace drivers within the CoreSight framework and integrating them with perf tools. The K3 SoC contains RISC-V Encoder, Funnel, ATB, CoreSight Funnel, and CoreSight TMC components, which can be directly leveraged through the existing CoreSight infrastructure. Linux RISC-V trace support form Anup Patel: (https://patchwork.kernel.org/project/linux-riscv/cover/20260225062448.40279…) which currently lacks ATB component support and guidance on reusing CoreSight components. The series includes: - RISC-V trace driver implementation within the CoreSight framework - RISC-V Trace Encoder, Funnel, and ATB Bridge drivers as CoreSight devices - RISC-V trace PMU record capabilities and parsing events in perf. - RISC-V Nexus Trace decoder for perf tools Any comments or suggestions are welcome. Verification on K3 SoC: To verify this patch series on K3 hardware, the following device tree are required: 1. RISC-V Trace Encoder node (8) 2. RISC-V ATB Bridge node (8) 3. RISC-V Trace Funnel node (2) 3. CoreSight Funnel configuration for RISC-V (1) 4. CoreSight TMC configuration for trace buffer (1) /{ dummy_clk: apb-pclk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-output-names = "clk14mhz"; clock-frequency = <14000000>; }; soc: soc { #address-cells = <2>; #size-cells = <2>; encoder0: encoder@d9002000 { compatible = "riscv,trace-encoder"; reg = <0x0 0xd9002000 0x0 0x1000>; cpus = <&cpu_0>; out-ports { port { cluster0_encoder0_out_port: endpoint { remote-endpoint = <&cluster0_bridge0_in_port>; }; }; }; }; bridge0: bridge@d9003000 { compatible = "riscv,trace-atbbridge"; reg = <0x0 0xd9003000 0x0 0x1000>; cpus = <&cpu_0>; out-ports { port { cluster0_bridge0_out_port: endpoint { remote-endpoint = <&cluster0_funnel_in_port0>; }; }; }; in-ports { port { cluster0_bridge0_in_port: endpoint { remote-endpoint = <&cluster0_encoder0_out_port>; }; }; }; }; ... cluster0_funnel: funnel@d9000000 { compatible = "riscv,trace-funnel"; reg = <0x0 0xd9000000 0x0 0x1000>; cpus = <&cpu_0>, <&cpu_1>, <&cpu_2>, <&cpu_3>; riscv,timestamp-present; out-ports { port { cluster0_funnel_out_port: endpoint { remote-endpoint = <&main_funnel_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; cluster0_funnel_in_port0: endpoint { remote-endpoint = <&cluster0_bridge0_out_port>; }; }; port@1 { reg = <1>; cluster0_funnel_in_port1: endpoint { remote-endpoint = <&cluster0_bridge1_out_port>; }; }; port@2 { reg = <2>; cluster0_funnel_in_port2: endpoint { remote-endpoint = <&cluster0_bridge2_out_port>; }; }; port@3 { reg = <3>; cluster0_funnel_in_port3: endpoint { remote-endpoint = <&cluster0_bridge3_out_port>; }; }; }; }; cluster1_funnel: funnel@d9010000 { compatible = "riscv,trace-funnel"; reg = <0x0 0xd9010000 0x0 0x1000>; cpus = <&cpu_4>, <&cpu_5>, <&cpu_6>, <&cpu_7>; riscv,timestamp-present; out-ports { port { cluster1_funnel_out_port: endpoint { remote-endpoint = <&main_funnel_in_port1>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; cluster1_funnel_in_port0: endpoint { remote-endpoint = <&cluster1_bridge0_out_port>; }; }; port@1 { reg = <1>; cluster1_funnel_in_port1: endpoint { remote-endpoint = <&cluster1_bridge1_out_port>; }; }; port@2 { reg = <2>; cluster1_funnel_in_port2: endpoint { remote-endpoint = <&cluster1_bridge2_out_port>; }; }; port@3 { reg = <3>; cluster1_funnel_in_port3: endpoint { remote-endpoint = <&cluster1_bridge3_out_port>; }; }; }; }; main_funnel: funnel@d9042000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0xd9042000 0x0 0x1000>; clocks = <&dummy_clk>; clock-names = "apb_pclk"; out-ports { port { main_funnel_out_port: endpoint { remote-endpoint = <&etf_in_port>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; main_funnel_in_port0: endpoint { remote-endpoint = <&cluster0_funnel_out_port>; }; }; port@1 { reg = <1>; main_funnel_in_port1: endpoint { remote-endpoint = <&cluster1_funnel_out_port>; }; }; }; }; etf: etf@d9043000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0xd9043000 0x0 0x1000>; clocks = <&dummy_clk>; clock-names = "apb_pclk"; out-ports { port { etf_out_port: endpoint { remote-endpoint = <&etr_in_port>; }; }; }; in-ports { port { etf_in_port: endpoint { remote-endpoint = <&main_funnel_out_port>; }; }; }; }; etr: etr@d9044000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0xd9044000 0x0 0x1000>; clocks = <&dummy_clk>; clock-names = "apb_pclk"; arm,scatter-gather; in-ports { port { etr_in_port: endpoint { remote-endpoint = <&etf_out_port>; }; }; }; }; }; }; Verification case: ~ # perf list pmu rvtrace// [Kernel PMU event] ~ # perf record -e rvtrace/@tmc_etr0/ --per-thread uname Linux [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.191 MB perf.data ] ~ # perf script uname 137 [003] 1 branches: ffffffff80931470 rvtrace_poll_bit+0x38 ([kernel.kallsyms]) => ffffffff80931492 rvtrace_poll_bit+0x5a ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff809328a6 encoder_enable_hw+0x252 ([kernel.kallsyms]) => ffffffff809328ba encoder_enable_hw+0x266 ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff80932c4a encoder_enable+0x82 ([kernel.kallsyms]) => ffffffff80932c36 encoder_enable+0x6e ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff80928198 etm_event_start+0xf0 ([kernel.kallsyms]) => ffffffff809281aa etm_event_start+0x102 ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff809281e6 etm_event_start+0x13e ([kernel.kallsyms]) => ffffffff8092755e coresight_get_sink_id+0x16 ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff8092820e etm_event_start+0x166 ([kernel.kallsyms]) => ffffffff80928226 etm_event_start+0x17e ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff801c3bb4 perf_report_aux_output_id+0x0 ([kernel.kallsyms]) => ffffffff801c3bd6 perf_report_aux_output_id+0x22 ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff801c3c5a perf_report_aux_output_id+0xa6 ([kernel.kallsyms]) => ffffffff801c3bf0 perf_report_aux_output_id+0x3c ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff801c3c40 perf_report_aux_output_id+0x8c ([kernel.kallsyms]) => ffffffff801c3aea __perf_event_header__init_id+0x2a ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff801c3b42 __perf_event_header__init_id+0x82 ([kernel.kallsyms]) => ffffffff801c3b4a __perf_event_header__init_id+0x8a ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff801c3bb0 __perf_event_header__init_id+0xf0 ([kernel.kallsyms]) => ffffffff801c3b58 __perf_event_header__init_id+0x98 ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff8004c658 __task_pid_nr_ns+0x0 ([kernel.kallsyms]) => ffffffff8004c696 __task_pid_nr_ns+0x3e ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff8004c71e __task_pid_nr_ns+0xc6 ([kernel.kallsyms]) => ffffffff8004c6a4 __task_pid_nr_ns+0x4c ([kernel.kallsyms]) uname 137 [003] 1 branches: ffffffff8004c6e4 __task_pid_nr_ns+0x8c ([kernel.kallsyms]) => ffffffff8004c6e4 __task_pid_nr_ns+0x8c ([kernel.kallsyms]) ... liangzhen (12): coresight: Add RISC-V support to CoreSight tracing coresight: Initial implementation of RISC-V trace driver coresight: Add RISC-V Trace Encoder driver coresight: Add RISC-V Trace Funnel driver coresight: Add RISC-V Trace ATB Bridge driver coresight rvtrace: Add timestamp component support for encoder and funnel coresight: Add RISC-V PMU name support perf tools: riscv: making rvtrace PMU listable perf tools: Add RISC-V trace PMU record capabilities perf tools: Add Nexus RISC-V Trace decoder perf symbols: Add RISC-V PLT entry sizes perf tools: Integrate RISC-V trace decoder into auxtrace drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/coresight/Kconfig | 46 +- drivers/hwtracing/coresight/Makefile | 6 + drivers/hwtracing/coresight/coresight-core.c | 8 + .../hwtracing/coresight/coresight-etm-perf.c | 1 - .../hwtracing/coresight/coresight-etm-perf.h | 21 + .../hwtracing/coresight/coresight-platform.c | 1 - .../hwtracing/coresight/coresight-tmc-etf.c | 4 + .../hwtracing/coresight/coresight-tmc-etr.c | 4 + .../hwtracing/coresight/rvtrace-atbbridge.c | 239 +++ drivers/hwtracing/coresight/rvtrace-core.c | 135 ++ .../coresight/rvtrace-encoder-core.c | 562 +++++++ .../coresight/rvtrace-encoder-sysfs.c | 363 +++++ drivers/hwtracing/coresight/rvtrace-encoder.h | 151 ++ drivers/hwtracing/coresight/rvtrace-funnel.c | 337 ++++ drivers/hwtracing/coresight/rvtrace-funnel.h | 39 + .../hwtracing/coresight/rvtrace-timestamp.c | 278 ++++ .../hwtracing/coresight/rvtrace-timestamp.h | 64 + include/linux/coresight-pmu.h | 4 + include/linux/rvtrace.h | 116 ++ tools/arch/riscv/include/asm/insn.h | 645 ++++++++ tools/perf/arch/riscv/util/Build | 2 + tools/perf/arch/riscv/util/auxtrace.c | 490 ++++++ tools/perf/arch/riscv/util/pmu.c | 20 + tools/perf/util/Build | 3 + tools/perf/util/auxtrace.c | 4 + tools/perf/util/auxtrace.h | 1 + tools/perf/util/nexus-rv-decoder/Build | 1 + .../util/nexus-rv-decoder/nexus-rv-decoder.c | 1364 +++++++++++++++++ .../util/nexus-rv-decoder/nexus-rv-decoder.h | 139 ++ .../perf/util/nexus-rv-decoder/nexus-rv-msg.h | 190 +++ tools/perf/util/rvtrace-decoder.c | 1039 +++++++++++++ tools/perf/util/rvtrace.h | 40 + tools/perf/util/symbol-elf.c | 4 + 34 files changed, 6320 insertions(+), 3 deletions(-) create mode 100644 drivers/hwtracing/coresight/rvtrace-atbbridge.c create mode 100644 drivers/hwtracing/coresight/rvtrace-core.c create mode 100644 drivers/hwtracing/coresight/rvtrace-encoder-core.c create mode 100644 drivers/hwtracing/coresight/rvtrace-encoder-sysfs.c create mode 100644 drivers/hwtracing/coresight/rvtrace-encoder.h create mode 100644 drivers/hwtracing/coresight/rvtrace-funnel.c create mode 100644 drivers/hwtracing/coresight/rvtrace-funnel.h create mode 100644 drivers/hwtracing/coresight/rvtrace-timestamp.c create mode 100644 drivers/hwtracing/coresight/rvtrace-timestamp.h create mode 100644 include/linux/rvtrace.h create mode 100644 tools/arch/riscv/include/asm/insn.h create mode 100644 tools/perf/arch/riscv/util/auxtrace.c create mode 100644 tools/perf/arch/riscv/util/pmu.c create mode 100644 tools/perf/util/nexus-rv-decoder/Build create mode 100644 tools/perf/util/nexus-rv-decoder/nexus-rv-decoder.c create mode 100644 tools/perf/util/nexus-rv-decoder/nexus-rv-decoder.h create mode 100644 tools/perf/util/nexus-rv-decoder/nexus-rv-msg.h create mode 100644 tools/perf/util/rvtrace-decoder.c create mode 100644 tools/perf/util/rvtrace.h -- 2.34.1

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