CoreSight

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2708 discussions

[PATCH v2 00/14] perf cs-etm: Fix bogus branch samples on exceptions

by Leo Yan

CoreSight currently models exception entry by changing the preceding instruction range into a taken branch. This can give an IRQ the source PC of an instruction that already retired and overwrite a real branch immediately before the exception. For an untaken B.LS followed by an IRQ, perf script currently reports: hw int 4000f8 => ffff800080010c80 b.ls #0x400118 ... iret ffff800080012284 => 4000fc eret The hardware trace supplies 0x4000fc as the preferred return address. For an IRQ, this is the architectural resume PC (Arm ARM, R_VBQMV). B.LS has retired, and the saved PC identifies the boundary before the following MOV. Using this PC as the IRQ source reflects the architectural state at exception entry: hw int 4000fc => ffff800080010c80 movz x2, #0x1796 ... iret ffff800080012284 => 4000fc eret The IRQ sample represents the transfer from this architectural execution position to the handler. The series synthesizes exception entries from exception packets, preserving the preceding branch and its outcome. The supporting changes: - Let decoders supply sample.ret_addr so later instruction fetching cannot change thread-stack return addresses. Apply this to Intel PT asynchronous samples as well. - Prepare packet ISA and instruction-size handling and share sample synthesis helpers. Mark untaken branches and break history when instruction memory is unavailable. - Add a thread-stack regression test and four AArch64 CoreSight tests. IRQs and page faults must resume at the entry PC; SVC and emulated MRS must resume four bytes later. Based on the AI search and test on my x86 machine, this matches perf's Intel PT handling of IRQs. Intel PT records the next instruction's IP in the FUP packet, and Perf uses that IP as the interrupt sample's source. This series is verified on Orion6 board with "perf test coresight". Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Rework the fix around exception packets to preserve both exception entries and preceding branches. - Add explicit return addresses and the Intel PT asynchronous-branch fix. - Split out packet/synthesis preparation, record not-taken branches and handle unreadable instruction memory. - Add thread-stack regression coverage and four CoreSight tests. - Link to v1: https://lore.kernel.org/r/20260713-perf_cs_etm_fix_non_taken-v1-0-4561607fc… --- Leo Yan (14): perf sample: Allow decoders to supply branch return addresses perf intel-pt: Preserve return addresses for asynchronous branches perf cs-etm: Break branch history when instruction memory is unavailable perf cs-etm: Centralize packet ISA initialization perf cs-etm: Use the recorded instruction size for A32 and A64 perf cs-etm: Mark branches that were not taken perf cs-etm: Factor out final instruction sample synthesis perf cs-etm: Centralize branch sample synthesis checks perf cs-etm: Classify exception calls using the exception packet perf cs-etm: Synthesize exception entries separately from branches perf tests: Check CoreSight IRQ entry and exit perf tests: Check CoreSight syscall entry and exit perf tests: Check CoreSight abort entry and exit perf tests: Check CoreSight emulated instruction entry and exit tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 3 + .../perf/tests/shell/coresight/abort_entry_exit.sh | 21 ++ tools/perf/tests/shell/coresight/irq_entry_exit.sh | 37 ++++ .../tests/shell/coresight/syscall_entry_exit.sh | 21 ++ .../perf/tests/shell/coresight/trap_entry_exit.sh | 24 +++ tools/perf/tests/shell/lib/coresight_exception.sh | 165 +++++++++++++++ tools/perf/tests/tests.h | 3 + tools/perf/tests/thread-stack.c | 106 ++++++++++ tools/perf/tests/workloads/Build | 4 + tools/perf/tests/workloads/branch_not_taken_loop.c | 33 +++ tools/perf/tests/workloads/page_fault_loop.c | 37 ++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 106 +++++++--- tools/perf/util/cs-etm.c | 222 ++++++++++----------- tools/perf/util/cs-etm.h | 2 + tools/perf/util/intel-pt.c | 7 + tools/perf/util/sample.c | 1 + tools/perf/util/sample.h | 5 + tools/perf/util/thread-stack.c | 5 +- 19 files changed, 656 insertions(+), 147 deletions(-) --- base-commit: edd8a9fe2eca009599e013a29c421c7a6b5ad1b9 change-id: 20260713-perf_cs_etm_fix_non_taken-5b4d7f73f41e Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 week, 1 day

[PATCH v4 00/10] coresight: Prevent per-thread events from sharing a sink

by James Clark

Concurrent per-thread events results in a WARN on N1SDP which leads to the realization that per-thread events shouldn't have been sharing sinks in the first place. This slips through because different per-thread events will have the same PID if owned by the same process, and we only check the PID and nothing else. That results in unexpected WARNs because it looks like we assumed it couldn't happen (although exclusive PMU rules allow it). But even if it was supported it would result in trace from the wrong thread in another event's per-thread buffer, so we should disallow it. Fix it by determining if sharing can happen at setup time. Then remove everywhere the same PID checking logic was copy pasted in each sink. The first three patches fix configuration initialization, AUX cleanup and topology locking. The remaining patches enforce the sharing rules and simplify the sink drivers. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v4: - Count CPU sources in the registered topology and retain each sink's sharing classification until its last AUX session ends. - Serialize AUX topology access and provide locked and locking path release functions. - Reject unexpected path setup errors while retaining silent skips for missing ETMs and unreachable sinks. - Prevent all problematic sharing cases at aux setup rather than at runtime. (Leo) - Drop "coresight: tmc-etr: Don't stop Perf cleanup for active sysfs reads". It was a pre-existing bug and is even more unrelated now with the new model. - Remove workqueue rather than fix the lifecycle, its no longer needed. (Leo) - Add a getter for the config manager, cscfg_get_state(). (Leo) - Link to v3: https://lore.kernel.org/r/20260728-james-cs-multiple-per-threads-v3-0-6aee7… Changes in v3: - Storing and accessing event owners at runtime causes problems due to various scenarios of: events (and sibling events) exiting, children inheriting event FDs, PID reuse, CPU affine events that also have a target process set but different inherit settings. Fix it by creating a session ID in etm_setup_aux() and holding the references in it for the duration of the whole session. (Leo) - Make the ETR buffer allocator consistent with sink sharing rules by not doing numeric PID comparisons there either. - Fix up some Sashiko reports that it sees after interacting with cscfg and taking extra references to tasks and PIDs. - Link to v2: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v2-0-10ac7… Changes in v2: - Fix inherited events by following event->parent - Link to v1: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v1-0-d384e… --- James Clark (10): coresight: configfs: Don't assume active until cscfg_mgr is set coresight: etm-perf: Remove workqueue for freeing AUX data coresight: etm-perf: Serialize AUX topology access coresight: etm-perf: Reject event if building path fails coresight: etm-perf: Prevent sink sharing at setup time coresight: tmc-etr: Reflect new sharing rules in allocator coresight: tmc-etr: Remove sharing guards from ETR coresight: tmc-etf: Remove sharing guards from ETF coresight: etb10: Remove sharing guards from ETB10 coresight: ultrasoc-smb: Remove sharing guards from SMB drivers/hwtracing/coresight/coresight-core.c | 104 +++++++++++++++-- drivers/hwtracing/coresight/coresight-etb10.c | 28 +---- drivers/hwtracing/coresight/coresight-etm-perf.c | 119 ++++++++++--------- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 - drivers/hwtracing/coresight/coresight-priv.h | 4 +- drivers/hwtracing/coresight/coresight-syscfg.c | 11 +- drivers/hwtracing/coresight/coresight-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 22 +--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 142 +++++++---------------- drivers/hwtracing/coresight/coresight-tmc.h | 16 +-- drivers/hwtracing/coresight/coresight-trace-id.c | 97 ++++++++++++++-- drivers/hwtracing/coresight/coresight-trace-id.h | 26 +++-- drivers/hwtracing/coresight/ultrasoc-smb.c | 20 +--- drivers/hwtracing/coresight/ultrasoc-smb.h | 3 - include/linux/coresight.h | 26 ++++- 16 files changed, 346 insertions(+), 284 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20260708-james-cs-multiple-per-threads-ed1d25ed1734 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 2 days

[PATCH] coresight: handle runtime PM resume failures

by Yuanfang Zhang

When a CoreSight component's parent power domain, such as a CPU cluster genpd, fails to power on, runtime resume returns a negative error. Several call sites ignored that error and continued to access registers on an unpowered device, risking an external abort. Replace the remaining pm_runtime_get_sync() calls with pm_runtime_resume_and_get(), which restores the runtime PM usage count when resume fails. Abort before accessing hardware and propagate the error to the caller. In coresight_get_ref(), unwind the module and device references. In debug_enable_func(), roll back the CPUs that resumed successfully before the failure. Finally, release the mode acquired by stm_enable() if its runtime resume fails. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- This patch converts the remaining CoreSight pm_runtime_get_sync() users to pm_runtime_resume_and_get(), propagates resume failures before hardware access, and completes the related module, device, CPU and mode unwind paths. --- drivers/hwtracing/coresight/coresight-core.c | 13 ++++++++++--- drivers/hwtracing/coresight/coresight-cpu-debug.c | 10 +++++----- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 5 ++++- drivers/hwtracing/coresight/coresight-funnel.c | 5 ++++- drivers/hwtracing/coresight/coresight-stm.c | 7 ++++++- drivers/hwtracing/coresight/coresight-sysfs.c | 11 +++++++++-- 8 files changed, 54 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 928488a216d4eafa3cdb5f882ae5f44ddaff0448..ff93a017dbe22b01236ac2e5021da9b82890e72c 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -822,14 +822,16 @@ struct coresight_device *coresight_get_sink_by_id(u32 id) * * @csdev: The coresight device to get a reference on. * - * Return true in successful case and power up the device. - * Return false when failed to get reference of module. + * Return true on success and power up the device. + * Return false if a reference cannot be obtained or the device cannot be + * powered up. */ static bool coresight_get_ref(struct coresight_device *csdev) { struct device *dev = &csdev->dev; struct device *parent = csdev->dev.parent; struct device_driver *drv; + int ret; /* Make sure csdev can't go away */ get_device(dev); @@ -843,9 +845,14 @@ static bool coresight_get_ref(struct coresight_device *csdev) goto err_module; /* Make sure the device is powered on */ - pm_runtime_get_sync(parent); + ret = pm_runtime_resume_and_get(parent); + if (ret < 0) + goto err_pm; + return true; +err_pm: + module_put(drv->owner); err_module: put_device(parent); put_device(dev); diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 3a806c1d50eafb4249ab516ef846e437831b9681..39602d610e5b22ec4f165dbb126a7c06aea08eb0 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -429,19 +429,19 @@ static int debug_enable_func(void) if (!drvdata) continue; - ret = pm_runtime_get_sync(drvdata->dev); + ret = pm_runtime_resume_and_get(drvdata->dev); if (ret < 0) goto err; - else - cpumask_set_cpu(cpu, &mask); + + cpumask_set_cpu(cpu, &mask); } return 0; err: /* - * If pm_runtime_get_sync() has failed, need rollback on - * all the other CPUs that have been enabled before that. + * If runtime resume has failed, roll back all the other CPUs + * that have been enabled before that. */ for_each_cpu(cpu, &mask) { drvdata = per_cpu(debug_drvdata, cpu); diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 3fe2c916d228808233ef19e9213a0cc0ce3cf297..6886b8713368058b9cf33ab7fafb5f87e23c1ec9 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -167,8 +167,11 @@ static ssize_t coresight_cti_reg_show(struct device *dev, struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); u32 val = 0; + int ret; - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) val = cti_read_single_reg(drvdata, cti_attr->off); @@ -185,11 +188,14 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); unsigned long val = 0; + int ret; if (kstrtoul(buf, 0, &val)) return -EINVAL; - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) cti_write_single_reg(drvdata, cti_attr->off, val); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index b3c67e96a82a4995515457d1ac0a5b183b162f0f..b34e282ec4a5f37f7de1d2ff118042b47368acd7 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -47,8 +47,11 @@ static ssize_t etmsr_show(struct device *dev, { unsigned long flags, val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + int ret; - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->csa.base); @@ -933,13 +936,16 @@ static ssize_t seq_curr_state_show(struct device *dev, unsigned long val, flags; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config; + int ret; if (!coresight_get_mode(drvdata->csdev)) { val = config->seq_curr_state; goto out; } - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->csa.base); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc6cdd3ae29d502a2e67f07400de957b6dc71af6..55e05c20b302d4bf55c4df30c9ee6d6a1b5f1031 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2457,10 +2457,13 @@ static ssize_t coresight_etm4x_reg_show(struct device *dev, { u32 val, offset; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + int ret; offset = coresight_etm4x_attr_to_offset(d_attr); - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; val = etmv4_cross_read(drvdata, offset); pm_runtime_put_sync(dev->parent); diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 0abc11f0690c5272ebd55df9e98544e3b401cfe6..5824a1e4d046a3caf5b32ed1d8526b8bd7e9ca76 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -190,9 +190,12 @@ static ssize_t funnel_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf) { u32 val; + int ret; struct funnel_drvdata *drvdata = dev_get_drvdata(dev->parent); - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; val = get_funnel_ctrl_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 4e860519a73f6fff640090cf58298b89a31e6359..b9f15990ed994ea827c8e237d764e74d8d231ddd 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -196,6 +196,7 @@ static int stm_enable(struct coresight_device *csdev, struct perf_event *event, __maybe_unused struct coresight_path *path) { struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; if (mode != CS_MODE_SYSFS) return -EINVAL; @@ -205,7 +206,11 @@ static int stm_enable(struct coresight_device *csdev, struct perf_event *event, return -EBUSY; } - pm_runtime_get_sync(csdev->dev.parent); + ret = pm_runtime_resume_and_get(csdev->dev.parent); + if (ret < 0) { + coresight_set_mode(csdev, CS_MODE_DISABLED); + return ret; + } spin_lock(&drvdata->spinlock); stm_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 4b010f8bc4c08da31b3d295be6c37b6d941629d2..5849dfbd9d0bd3ad10734919f78bc39cc968539c 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -17,8 +17,12 @@ ssize_t coresight_simple_show_pair(struct device *_dev, struct coresight_device *csdev = container_of(_dev, struct coresight_device, dev); struct cs_pair_attribute *cs_attr = container_of(attr, struct cs_pair_attribute, attr); u64 val; + int ret; + + ret = pm_runtime_resume_and_get(_dev->parent); + if (ret < 0) + return ret; - pm_runtime_get_sync(_dev->parent); val = csdev_access_relaxed_read_pair(&csdev->access, cs_attr->lo_off, cs_attr->hi_off); pm_runtime_put_sync(_dev->parent); return sysfs_emit(buf, "0x%llx\n", val); @@ -31,8 +35,11 @@ ssize_t coresight_simple_show32(struct device *_dev, struct coresight_device *csdev = container_of(_dev, struct coresight_device, dev); struct cs_off_attribute *cs_attr = container_of(attr, struct cs_off_attribute, attr); u64 val; + int ret; - pm_runtime_get_sync(_dev->parent); + ret = pm_runtime_resume_and_get(_dev->parent); + if (ret < 0) + return ret; val = csdev_access_relaxed_read32(&csdev->access, cs_attr->off); pm_runtime_put_sync(_dev->parent); return sysfs_emit(buf, "0x%llx\n", val); --- base-commit: 08df884136f1c1197bab2a27814404fd329d9aac change-id: 20260911-b4-coresight-runtime-pm-failures-70f250927aeb Best regards, -- Yuanfang Zhang <yuanfang(a)qti.qualcomm.com>

1 week, 3 days

[PATCH 0/2] coresight: Retry failed HW_ID writes

by James Clark

Extracted from the last two commits from [1] as they were only conceptually related to that patchset, not functionally. This can be safely applied to the driver separately. [1] https://lore.kernel.org/linux-perf-users/20260821-james-cs-hw_id-output-fai… Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (2): perf/core: Return errors from perf_report_aux_output_id() coresight: Retry failed HW_ID writes drivers/hwtracing/coresight/coresight-etm-perf.c | 50 +++++++++++++++--------- include/linux/perf_event.h | 2 +- kernel/events/core.c | 6 ++- 3 files changed, 36 insertions(+), 22 deletions(-) --- base-commit: 75ba5c486ea071d44d3f61318c88a7793bc768d4 change-id: 20261001-james-cs-retry-hw_id-8f1ec3cf2db3 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 3 days

Re: [PATCH v2] perf: arm_spe: Support heterogeneous ACPI systems

by Jeremy Linton

Hi, This largely looks reasonable, some comments inline. On 10/20/26 9:03 PM, Johnny.Fan wrote: > From: "Johnny.Fan" <Johnny.Fan(a)cixtech.com> > > On heterogeneous ACPI systems, not all CPUs implement SPE, and the > ones that do may use different PPIs. The MADT describes this per > GICC entry: a CPU without SPE reports a zero SPE overflow interrupt, > and the PPTT hetero id identifies CPUs of the same implementation. > > The current code registers a single platform device and gives up if > the GICC entries disagree on either the hetero id or the interrupt, > so SPE is unavailable on such systems even though the firmware > describes it. > > Group the CPUs by (hetero id, SPE interrupt) and register one > platform device per group. A GSI may be shared between groups with > non-overlapping CPU masks, so only unregister the GSI mapping when > no other group uses the same interrupt, as the mapping is not > reference counted. > > These synthetic devices have no fwnode, so the firmware-described > IRQ affinity cannot tell which CPUs implement the feature. Pass the > CPU mask as platform data and have the drivers prefer it over the > IRQ affinity when present. > > Apply the same treatment to TRBE, which shares this registration > code. TRBE must also pass a stable copy of the mask to > request_percpu_irq_affinity(), since supported_cpus is pruned as > CPUs are probed. > > Tested on a CIX sky1 SoC with heterogeneous SPE support. > > Signed-off-by: Johnny.Fan <Johnny.Fan(a)cixtech.com> > Reviewed-by: Fugang Duan <fugang.duan(a)cixtech.com> > --- > drivers/hwtracing/coresight/coresight-trbe.c | 22 +- > drivers/perf/arm_pmu_acpi.c | 211 ++++++++++++------- It makes sense to split the device creation portion in arm_pmu_acpi.c into its own patch separate from the consumption IMHO. > drivers/perf/arm_spe_pmu.c | 10 +- > include/linux/perf/arm_pmu.h | 10 + > 4 files changed, 176 insertions(+), 77 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index c7cbca45f2de..0c4bc8fbcaf3 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -158,6 +158,7 @@ struct trbe_drvdata { > struct hlist_node hotplug_node; > int irq; > cpumask_t supported_cpus; > + cpumask_t irq_affinity; > enum cpuhp_state trbe_online; > struct platform_device *pdev; > }; > @@ -1533,6 +1534,8 @@ static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata) > static int arm_trbe_probe_irq(struct platform_device *pdev, > struct trbe_drvdata *drvdata) > { > + const struct arm_pmu_acpi_dev_data *acpi_data = > + dev_get_platdata(&pdev->dev); > const struct cpumask *affinity; > int ret; > > @@ -1547,14 +1550,27 @@ static int arm_trbe_probe_irq(struct platform_device *pdev, > return -EINVAL; > } > > - cpumask_copy(&drvdata->supported_cpus, affinity); > + /* > + * The ACPI path has no fwnode describing which CPUs implement TRBE, > + * so it passes the mask explicitly. DT devices still use the > + * firmware-described IRQ affinity. > + */ > + cpumask_copy(&drvdata->supported_cpus, > + acpi_data ? &acpi_data->cpus : affinity); > + > + /* > + * supported_cpus gets pruned as CPUs are probed, so keep a stable > + * copy for the IRQ action. > + */ > + cpumask_copy(&drvdata->irq_affinity, &drvdata->supported_cpus); > > drvdata->handle = alloc_percpu(struct perf_output_handle *); > if (!drvdata->handle) > return -ENOMEM; > > - ret = request_percpu_irq_affinity(drvdata->irq, arm_trbe_irq_handler, DRVNAME, > - affinity, drvdata->handle); > + ret = request_percpu_irq_affinity(drvdata->irq, arm_trbe_irq_handler, > + DRVNAME, &drvdata->irq_affinity, > + drvdata->handle); > if (ret) { > free_percpu(drvdata->handle); > return ret; > diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c > index ca6bf8f86cfe..fdf39673648f 100644 > --- a/drivers/perf/arm_pmu_acpi.c > +++ b/drivers/perf/arm_pmu_acpi.c > @@ -12,6 +12,8 @@ > #include <linux/irqdesc.h> > #include <linux/percpu.h> > #include <linux/perf/arm_pmu.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > > #include <asm/cpu.h> > #include <asm/cputype.h> > @@ -68,91 +70,165 @@ static void arm_pmu_acpi_unregister_irq(int cpu) > acpi_unregister_gsi(gsi); > } > > -static int __maybe_unused > -arm_acpi_register_pmu_device(struct platform_device *pdev, u8 len, > - u16 (*parse_gsi)(struct acpi_madt_generic_interrupt *)) > +struct arm_pmu_acpi_group { > + int hetid; > + u16 gsi; > + struct cpumask cpus; > +}; > + > +static int arm_acpi_find_group(struct arm_pmu_acpi_group *groups, int nr_groups, > + int hetid, u16 gsi) > { > - int cpu, this_hetid, hetid, irq, ret; > - u16 this_gsi = 0, gsi = 0; > + int i; > > - /* > - * Ensure that platform device must have IORESOURCE_IRQ > - * resource to hold gsi interrupt. > - */ > - if (pdev->num_resources != 1) > - return -ENXIO; > + for (i = 0; i < nr_groups; i++) { > + if (groups[i].hetid == hetid && groups[i].gsi == gsi) > + return i; > + } > + > + return -1; > +} > + > +static bool arm_acpi_gsi_is_shared(struct arm_pmu_acpi_group *groups, > + int nr_groups, int idx) > +{ > + int i; > + > + for (i = 0; i < nr_groups; i++) { > + if (i != idx && groups[i].gsi == groups[idx].gsi) > + return true; > + } > + > + return false; > +} > + > +static int arm_acpi_register_group(struct arm_pmu_acpi_group *group, > + const char *name, bool gsi_shared) > +{ > + struct arm_pmu_acpi_dev_data data = { }; > + struct platform_device *pdev; > + struct resource res; > + int irq, ret; > + > + irq = acpi_register_gsi(NULL, group->gsi, ACPI_LEVEL_SENSITIVE, > + ACPI_ACTIVE_HIGH); > + if (irq < 0) > + return irq; > + > + pdev = platform_device_alloc(name, PLATFORM_DEVID_AUTO); > + if (!pdev) { > + ret = -ENOMEM; > + goto err_unreg; > + } > > - if (pdev->resource[0].flags != IORESOURCE_IRQ) > - return -ENXIO; > + res = DEFINE_RES_IRQ(irq); > + data.cpus = group->cpus; > > + ret = platform_device_add_resources(pdev, &res, 1); > + if (ret) > + goto err_put; > + > + ret = platform_device_add_data(pdev, &data, sizeof(data)); > + if (ret) > + goto err_put; > + > + ret = platform_device_add(pdev); > + if (!ret) > + return 0; > + > +err_put: > + platform_device_put(pdev); > +err_unreg: > /* > - * Sanity check all the GICC tables for the same interrupt > - * number. For now, only support homogeneous ACPI machines. > + * The GSI mapping is not reference counted, so only drop it if no > + * other group shares it. > */ > + if (!gsi_shared) > + acpi_unregister_gsi(group->gsi); This is a bit odd, if whatever fails, and gets here happens on all the paths associated with the shared GSI, then that GSI is never unregistered and the resource is leaked. > + > + return ret; > +} > + > +static int __maybe_unused > +arm_acpi_register_pmu_devices(const char *name, u8 len, > + u16 (*parse_gsi)(struct acpi_madt_generic_interrupt *)) > +{ > + struct arm_pmu_acpi_group *groups; > + int cpu, i, nr_cpus = 0, nr_groups = 0, nr_devices = 0; > + int last_err = 0, ret; > + > for_each_possible_cpu(cpu) { > struct acpi_madt_generic_interrupt *gicc; > > gicc = acpi_cpu_get_madt_gicc(cpu); > if (gicc->header.length < len) > - return gsi ? -ENXIO : 0; > - > - this_gsi = parse_gsi(gicc); > - this_hetid = find_acpi_cpu_topology_hetero_id(cpu); > - if (!gsi) { > - hetid = this_hetid; > - gsi = this_gsi; > - } else if (hetid != this_hetid || gsi != this_gsi) { > - pr_warn("ACPI: %s: must be homogeneous\n", pdev->name); > - return -ENXIO; > - } > + continue; This continue seems like a mistake, if the firmware has provided unreliable tables we should abort all device creation, even if that means some subset of the SPE devices which appear to be correct aren't created. > + if (parse_gsi(gicc)) > + nr_cpus++; > } > > - if (!this_gsi) > + if (!nr_cpus) > return 0; > > - irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); > - if (irq < 0) { > - pr_warn("ACPI: %s Unable to register interrupt: %d\n", pdev->name, gsi); > - return -ENXIO; > - } > + groups = kcalloc(nr_cpus, sizeof(*groups), GFP_KERNEL); And this seemed a bit chunky because in theory this could be NR_CPUS, which made me initially say, skip counting the cores and just allocate the max, then I realized its close to having kcalloc() failures if there are a lot of cores in the machine since this allocation becomes multiple MB. I think we are creating a future headache and need something smarter than counting the number of cores with valid SPE/TRBE interrupts. > + if (!groups) > + return -ENOMEM; > > - pdev->resource[0].start = irq; > - ret = platform_device_register(pdev); > - if (ret) > - acpi_unregister_gsi(gsi); > + for_each_possible_cpu(cpu) { > + struct acpi_madt_generic_interrupt *gicc; > + int hetid; > + u16 gsi; > > - return ret; > -} > + gicc = acpi_cpu_get_madt_gicc(cpu); > + if (gicc->header.length < len) > + continue; same continue issue here as above> > -#if IS_ENABLED(CONFIG_ARM_SPE_PMU) > -static struct resource spe_resources[] = { > - { > - /* irq */ > - .flags = IORESOURCE_IRQ, > + gsi = parse_gsi(gicc); > + if (!gsi) > + continue; > + > + hetid = find_acpi_cpu_topology_hetero_id(cpu); If groups were say a linked list (or something else dynamic) you could just use the failure case here to allocate the next entry and simply skip the first loop iteration above counting cpus. > + i = arm_acpi_find_group(groups, nr_groups, hetid, gsi); > + if (i < 0) { > + i = nr_groups++; > + groups[i].hetid = hetid; > + groups[i].gsi = gsi; > + } > + > + cpumask_set_cpu(cpu, &groups[i].cpus); > } > -}; > > -static struct platform_device spe_dev = { > - .name = ARMV8_SPE_PDEV_NAME, > - .id = -1, > - .resource = spe_resources, > - .num_resources = ARRAY_SIZE(spe_resources) > -}; > + for (i = 0; i < nr_groups; i++) { > + ret = arm_acpi_register_group(&groups[i], name, > + arm_acpi_gsi_is_shared(groups, > + nr_groups, i)); > + if (ret) { > + pr_warn("ACPI: %s: %*pbl: add device failed (%d)\n", > + name, cpumask_pr_args(&groups[i].cpus), ret); > + last_err = ret; > + } else { > + nr_devices++; > + } > + } > + > + kfree(groups); > + > + return nr_devices ? 0 : last_err; > +} > > +#if IS_ENABLED(CONFIG_ARM_SPE_PMU) > static u16 arm_spe_parse_gsi(struct acpi_madt_generic_interrupt *gicc) > { > return gicc->spe_interrupt; > } > > -/* > - * For lack of a better place, hook the normal PMU MADT walk > - * and create a SPE device if we detect a recent MADT with > - * a homogeneous PPI mapping. > - */ > static void arm_spe_acpi_register_device(void) > { > - int ret = arm_acpi_register_pmu_device(&spe_dev, ACPI_MADT_GICC_SPE, > - arm_spe_parse_gsi); > + int ret; > + > + ret = arm_acpi_register_pmu_devices(ARMV8_SPE_PDEV_NAME, > + ACPI_MADT_GICC_SPE, > + arm_spe_parse_gsi); > if (ret) > pr_warn("ACPI: SPE: Unable to register device\n"); > } > @@ -163,20 +239,6 @@ static inline void arm_spe_acpi_register_device(void) > #endif /* CONFIG_ARM_SPE_PMU */ > > #if IS_ENABLED(CONFIG_CORESIGHT_TRBE) > -static struct resource trbe_resources[] = { > - { > - /* irq */ > - .flags = IORESOURCE_IRQ, > - } > -}; > - > -static struct platform_device trbe_dev = { > - .name = ARMV8_TRBE_PDEV_NAME, > - .id = -1, > - .resource = trbe_resources, > - .num_resources = ARRAY_SIZE(trbe_resources) > -}; > - > static u16 arm_trbe_parse_gsi(struct acpi_madt_generic_interrupt *gicc) > { > return gicc->trbe_interrupt; > @@ -184,8 +246,11 @@ static u16 arm_trbe_parse_gsi(struct acpi_madt_generic_interrupt *gicc) > > static void arm_trbe_acpi_register_device(void) > { > - int ret = arm_acpi_register_pmu_device(&trbe_dev, ACPI_MADT_GICC_TRBE, > - arm_trbe_parse_gsi); > + int ret; > + > + ret = arm_acpi_register_pmu_devices(ARMV8_TRBE_PDEV_NAME, > + ACPI_MADT_GICC_TRBE, > + arm_trbe_parse_gsi); > if (ret) > pr_warn("ACPI: TRBE: Unable to register device\n"); > } > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index b70f3fedf028..712b7f187301 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -1330,6 +1330,8 @@ static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu) > static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu) > { > struct platform_device *pdev = spe_pmu->pdev; > + const struct arm_pmu_acpi_dev_data *acpi_data = > + dev_get_platdata(&pdev->dev); > const struct cpumask *affinity; > int irq; > > @@ -1342,7 +1344,13 @@ static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu) > return -EINVAL; > } > > - cpumask_copy(&spe_pmu->supported_cpus, affinity); > + /* > + * The ACPI path has no fwnode describing which CPUs implement SPE, > + * so it passes the mask explicitly. DT devices still use the > + * firmware-described IRQ affinity. > + */ > + cpumask_copy(&spe_pmu->supported_cpus, > + acpi_data ? &acpi_data->cpus : affinity); > > spe_pmu->irq = irq; > return 0; > diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h > index 02d2c7f45b52..7f1c03c55025 100644 > --- a/include/linux/perf/arm_pmu.h > +++ b/include/linux/perf/arm_pmu.h > @@ -8,6 +8,7 @@ > #ifndef __ARM_PMU_H__ > #define __ARM_PMU_H__ > > +#include <linux/cpumask.h> > #include <linux/interrupt.h> > #include <linux/perf_event.h> > #include <linux/platform_device.h> > @@ -199,6 +200,15 @@ void armpmu_free_irq(struct arm_pmu * __percpu *armpmu, int irq, int cpu); > #define ARMV8_SPE_PDEV_NAME "arm,spe-v1" > #define ARMV8_TRBE_PDEV_NAME "arm,trbe" > > +/* > + * Per-device CPU mask passed by the ACPI MADT walk. The synthetic > + * platform devices have no fwnode, so the IRQ affinity cannot describe > + * which CPUs actually implement the feature. > + */ > +struct arm_pmu_acpi_dev_data { > + struct cpumask cpus; > +}; > + > /* Why does everything I do descend into this? */ > #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ > (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi Thanks for working on this. Jeremy

1 week, 3 days

Re: [PATCH v2 2/4] coresight: syscfg: Match feature capabilities separately from device class

by Leo Yan

On Mon, Oct 12, 2026 at 04:05:21PM -0700, Amir Ayupov wrote: [...] > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -30,6 +30,12 @@ > #define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > #define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ It is good to introduce a marco: #define CS_CFG_MATCH_CLASS_MASK GENMASK_U32(7, 0) > +/* > + * flags defining device capabilities a feature can require. A feature loads on > + * a device that matches one of its classes and has all of its capabilities. > + */ > +#define CS_CFG_MATCH_CAP_MASK 0x0000ff00 To make the mask explicitly 32-bit unsigned: #define CS_CFG_MATCH_CAP_MASK GENMASK_U32(15, 8) > + > /* flags defining device instance matching - used in config match desc data. */ > #define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */ Not an issue with this patch, but CS_CFG_MATCH_INST_ANY appears to be unused and could be removed in a separate cleanup patch. > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index a816c22c87bc8..1545d64afec01 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -172,7 +172,21 @@ cscfg_alloc_csdev_feat(struct coresight_device *csdev, struct cscfg_feature_desc > } > > /* load one feature into one coresight device */ > +/* > + * A feature matches a device that shares one of its class flags and has all of > + * the capability flags it requires. > + */ > +static bool cscfg_match_feat_csdev(u32 feat_flags, u32 csdev_flags) > +{ > + u32 caps = feat_flags & CS_CFG_MATCH_CAP_MASK; > + > + return (feat_flags & csdev_flags & ~CS_CFG_MATCH_CAP_MASK) && > + (csdev_flags & caps) == caps; For clearer comparison conditions: /* Class type must be matches */ if ((feat_flags & CS_CFG_MATCH_CLASS_MASK) != (csdev_flags & CS_CFG_MATCH_CLASS_MASK) return false; /* No required capabilities miss from the device */ if (feat_flags & ~csdev_flags & CS_CFG_MATCH_CAP_MASK) return false; return true; Thanks, Leo

1 week, 3 days

Re: [PATCH] [v1] coresight: funnel: inport schedule by priority can not take work

by Leo Yan

Hi, On Sun, Oct 25, 2026 at 09:13:07PM +0800, Chao Xu wrote: > Before enable funnel, priority must be set. Changing the port > priorities in real time is not supported. > If the priority control register is written when one or more of ports > are enable, then the write is silently rejected. Could you cite the relevant documentation in commit log? The CoreSight SoC-600 TRM, section 9.11.2, PRIORITYCONTROL, a funnel rejects priority register writes whenever any port is enabled. The current sequence therefore prevent the configured priorities from taking effect. Write the priority register before enabling the first port. > Signed-off-by: Chao Xu <xuchao066(a)163.com> > --- > drivers/hwtracing/coresight/coresight-funnel.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c > index af40814ce560..17f985798d7f 100644 > --- a/drivers/hwtracing/coresight/coresight-funnel.c > +++ b/drivers/hwtracing/coresight/coresight-funnel.c > @@ -66,8 +66,8 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) > functl &= ~FUNNEL_HOLDTIME_MASK; > functl |= FUNNEL_HOLDTIME; > functl |= (1 << port); > - writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); > writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); > + writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); Please move the priority write into the first port branch: /* Claim the device only when we enable the first slave */ if (!(functl & FUNNEL_ENSx_MASK)) { rc = coresight_claim_device_unlocked(csdev); if (rc) goto done; /* Update priorities while all ports are disabled */ writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); } Thanks, Leo

1 week, 4 days

[PATCH] Revert "perf/aux: Allocate non-contiguous AUX pages by default"

by Leo Yan

This reverts commit 18049c8cff9cc89daadc4df6975f7d9069638926. The original commit claimed that contiguous AUX pages unnecessarily exacerbate fragmentation for SPE, TRBE and ETR. This is not generally valid: larger allocations can keep pages with the same lifetime together, while order-0 allocations can scatter them across large blocks and prevent free pages from coalescing [1]. The follow-up discussion [2] has not established how forcing order-0 allocations addresses the reported problem. TRBE and SPE write to virtually addressed buffers. The TRBE L1 TLB has one entry on Neoverse V2 [3] and two on Neoverse V3 [4]. Small mappings increase translation pressure, and TTW stalls can contribute to FIFO overflow and trace loss on TRBE. Larger allocations provide contiguous, aligned chunks for PMD or contiguous-PTE mappings with the proposed vmap() support [5]. With the proposed vmap() support already applied, the tests in [2] showed that preferring larger AUX allocations reduced L2 data TLB refills by 99.68% in the TRBE test and 34.74% in the SPE test. Restore the previous policy of trying higher-order allocations first. The allocator already uses __GFP_NORETRY and falls back to smaller orders, including order 0, when larger allocations fail. Remove PERF_PMU_CAP_AUX_PREFER_LARGE, since the restored default provides that preference. Intel PT retains its existing allocation behaviour, with no functional change. [1] https://lore.kernel.org/all/aPjrRkjiIt6HmXmT@casper.infradead.org/ [2] https://lore.kernel.org/linux-arm-kernel/20260810-perf_aux_trace_large_gran… [3] https://documentation-service.arm.com/static/633fe1ec4c59b30b517730b8#page=… [4] https://documentation-service.arm.com/static/67361bd2c7fc0d1f211da382#page=… [5] https://lore.kernel.org/linux-mm/20260715120813.3609949-1-jiangwen6@xiaomi.… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- arch/x86/events/intel/pt.c | 2 -- include/linux/perf_event.h | 5 ++--- kernel/events/ring_buffer.c | 29 +++++++++-------------------- 3 files changed, 11 insertions(+), 25 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 49349afee6119fb6fad815c847cb3cd9daa97604..3782af40f0832a874a7f0b60961d6652513de241 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1896,8 +1896,6 @@ static __init int pt_init(void) if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG; - else - pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_PREFER_LARGE; pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE | diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index eb3f7bab498ca9bee9ce7193744943b24ab2e0c5..b8d8b005f5c8a7c1def7cad02230bf9ffb876bd6 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -304,9 +304,8 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 #define PERF_PMU_CAP_AUX_PAUSE 0x0200 -#define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 -#define PERF_PMU_CAP_MEDIATED_VPMU 0x0800 -#define PERF_PMU_CAP_SIMD_REGS 0x1000 +#define PERF_PMU_CAP_MEDIATED_VPMU 0x0400 +#define PERF_PMU_CAP_SIMD_REGS 0x0800 /** * pmu::scope diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c index 64d4dbdc6c071b72b670dd044616f52981206ae8..95f4fbdfd2764de5b72d901d778c46302f525fad 100644 --- a/kernel/events/ring_buffer.c +++ b/kernel/events/ring_buffer.c @@ -684,15 +684,7 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, { bool overwrite = !(flags & RING_BUFFER_WRITABLE); int node = (event->cpu == -1) ? -1 : cpu_to_node(event->cpu); - bool use_contiguous_pages = event->pmu->capabilities & ( - PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_PREFER_LARGE); - /* - * Initialize max_order to 0 for page allocation. This allocates single - * pages to minimize memory fragmentation. This is overridden if the - * PMU needs or prefers contiguous pages (use_contiguous_pages = true). - */ - int max_order = 0; - int ret = -ENOMEM; + int ret = -ENOMEM, max_order; if (!has_aux(event)) return -EOPNOTSUPP; @@ -702,8 +694,8 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, if (!overwrite) { /* - * Watermark defaults to half the buffer, to aid PMU drivers - * in double buffering. + * Watermark defaults to half the buffer, and so does the + * max_order, to aid PMU drivers in double buffering. */ if (!watermark) watermark = min_t(unsigned long, @@ -711,19 +703,16 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, (unsigned long)nr_pages << (PAGE_SHIFT - 1)); /* - * If using contiguous pages, use aux_watermark as the basis - * for chunking to help PMU drivers honor the watermark. + * Use aux_watermark as the basis for chunking to + * help PMU drivers honor the watermark. */ - if (use_contiguous_pages) - max_order = get_order(watermark); + max_order = get_order(watermark); } else { /* - * If using contiguous pages, we need to start with the - * max_order that fits in nr_pages, not the other way around, - * hence ilog2() and not get_order. + * We need to start with the max_order that fits in nr_pages, + * not the other way around, hence ilog2() and not get_order. */ - if (use_contiguous_pages) - max_order = ilog2(nr_pages); + max_order = ilog2(nr_pages); watermark = 0; } --- base-commit: 21a7f44fd0765fcc5194130b28767786eba1d1e7 change-id: 20261025-perf_revert_prefer_large_alloc-a0177d6379f6 Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 week, 5 days

Re: [PATCH v4 7/7] coresight: Add pmu_pulse/extout_pulse

by James Clark

On 26/10/2026 05:48, Amir Ayupov wrote: > Add ETMv4 configuration 'pmu_pulse' with 'extout_pulse' feature which > requires an ETE whose PMU counts its external outputs > (CS_CFG_MATCH_CAP_TRCEXTOUT): event 1 selects the always-true > resource and drives TRCEXTOUT1 PMU event which pulses on every cycle > while the trace unit is enabled. > > Assisted-by: Devmate:Opus-5.5 > Signed-off-by: Amir Ayupov <aaupov(a)fb.com> > Reviewed-by: Daniel Pereira <danielmaraboo(a)gmail.com> > --- > .../trace/coresight/coresight-config.rst | 5 ++ > .../trace/coresight/coresight-perf.rst | 15 +++++ > drivers/hwtracing/coresight/Makefile | 1 + > .../coresight/coresight-cfg-pmu-pulse.c | 55 +++++++++++++++++++ > .../coresight/coresight-cfg-preload.c | 2 + > .../coresight/coresight-cfg-preload.h | 2 + > 6 files changed, 80 insertions(+) > create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pmu-pulse.c > > diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst > index 6d5ffa6f73471..3eed728bf0de1 100644 > --- a/Documentation/trace/coresight/coresight-config.rst > +++ b/Documentation/trace/coresight/coresight-config.rst > @@ -129,6 +129,11 @@ The following steps take place in the operation of a configuration. > > 5) At the end of the perf session, the configuration will be disabled. > > +The built-in 'pmu_pulse' configuration pulses ETM external output 1 for a PMU > +event to count. It only pulses while the ETM is enabled, so combined with AUX > +pause and resume the PMU event can time each trace window (see > +coresight-perf.rst). > + > > Viewing Configurations and Features > =================================== > diff --git a/Documentation/trace/coresight/coresight-perf.rst b/Documentation/trace/coresight/coresight-perf.rst > index 0a77741a431ef..6770a455c6b59 100644 > --- a/Documentation/trace/coresight/coresight-perf.rst > +++ b/Documentation/trace/coresight/coresight-perf.rst > @@ -109,6 +109,21 @@ Example for triggering AUX pause and resume with PMU event:: > -e cycles/aux-action=pause,period=10000000/ \ > -e cycles/aux-action=resume,period=1050000/ -- sleep 1 > > +ETM-timed pause events > +~~~~~~~~~~~~~~~~~~~~~~ > + > +The built-in ``pmu_pulse`` configuration pulses ETM external output 1 on every > +cycle of allowed trace, and a PMU event counting that output pauses trace after > +``N`` pulses, here 1000 cycles:: > + > + perf record -a -e cs_etm/pmu_pulse,aux-action=start-paused/u \ > + -e cycles/aux-action=resume,period=10000000/u \ > + -e trcextout1/aux-action=pause,period=1000/u \ > + -- sleep 1 > + > +Each window is about ``N`` traced cycles plus the pause interrupt latency. > +The configuration only loads on an ETE whose PMU counts its external outputs. > + > Perf test - Verify kernel and userspace perf CoreSight work > ----------------------------------------------------------- > > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index ab16d06783a57..568e797ac5a17 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o > coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ > coresight-sysfs.o coresight-syscfg.o coresight-config.o \ > coresight-cfg-preload.o coresight-cfg-afdo.o coresight-cfg-pstop.o \ > + coresight-cfg-pmu-pulse.o \ > coresight-syscfg-configfs.o coresight-trace-id.o > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ > diff --git a/drivers/hwtracing/coresight/coresight-cfg-pmu-pulse.c b/drivers/hwtracing/coresight/coresight-cfg-pmu-pulse.c > new file mode 100644 > index 0000000000000..61472154dd02a > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-cfg-pmu-pulse.c > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Pulse ETM external output 1 on every traced cycle for a PMU event to count. > + * Based on coresight-cfg-afdo.c > + */ > + > +#include "coresight-config.h" > + > +/* ETMv4 includes and features */ > +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) > +#include "coresight-etm4x-cfg.h" > + > +/* > + * extout_pulse feature: event 1 selects the always-true resource, so ETM > + * external output 1 pulses on every cycle while the trace unit is enabled. A > + * PMU event counting that output (TRCEXTOUT1), for example with > + * aux-action=pause, then fires after as many traced cycles as its sample > + * period. Event 0 is avoided because it is the trace unit trigger, and the > + * TRBE driver treats a detected trigger as fatal. > + */ > +static struct cscfg_regval_desc extout_pulse_regs[] = { > + /* event 1: resource selector 1 (always true), drives external output 1 */ > + { > + .type = CS_CFG_REG_TYPE_STD | CS_CFG_REG_TYPE_VAL_MASK, > + .offset = TRCEVENTCTL0R, > + .val32 = 0x0100, > + .mask32 = 0xff00, > + }, > + /* end of regs */ > +}; > + > +struct cscfg_feature_desc extout_pulse_etm4x = { > + .name = "extout_pulse", > + .description = "Pulse external output 1 on every traced cycle.\n", > + .match_flags = CS_CFG_MATCH_CLASS_SRC_ETM4 | CS_CFG_MATCH_CAP_TRCEXTOUT, > + .nr_regs = ARRAY_SIZE(extout_pulse_regs), > + .regs_desc = extout_pulse_regs, > +}; > + > +/* create a pmu_pulse configuration */ > + > +static const char *pmu_pulse_ref_names[] = { > + "extout_pulse", > +}; > + > +struct cscfg_config_desc pmu_pulse_etm4x = { > + .name = "pmu_pulse", > + .description = "Pulse ETM external output 1 on every traced cycle for the PMU\n" > + "to count as TRCEXTOUT1\n", > + .nr_feat_refs = ARRAY_SIZE(pmu_pulse_ref_names), > + .feat_ref_names = pmu_pulse_ref_names, > +}; > + > +/* end of ETM4x configurations */ > +#endif /* IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) */ > diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.c b/drivers/hwtracing/coresight/coresight-cfg-preload.c > index 4980e68483c5b..a9a60a1c40845 100644 > --- a/drivers/hwtracing/coresight/coresight-cfg-preload.c > +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.c > @@ -14,6 +14,7 @@ static struct cscfg_feature_desc *preload_feats[] = { > #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) > &strobe_etm4x, > &gen_etrig_etm4x, > + &extout_pulse_etm4x, > #endif > NULL > }; > @@ -22,6 +23,7 @@ static struct cscfg_config_desc *preload_cfgs[] = { > #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) > &afdo_etm4x, > &pstop_etm4x, > + &pmu_pulse_etm4x, > #endif > NULL > }; > diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.h b/drivers/hwtracing/coresight/coresight-cfg-preload.h > index 291ba530a6a52..0058627f65ae5 100644 > --- a/drivers/hwtracing/coresight/coresight-cfg-preload.h > +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.h > @@ -12,4 +12,6 @@ extern struct cscfg_feature_desc strobe_etm4x; > extern struct cscfg_config_desc afdo_etm4x; > extern struct cscfg_feature_desc gen_etrig_etm4x; > extern struct cscfg_config_desc pstop_etm4x; > +extern struct cscfg_feature_desc extout_pulse_etm4x; > +extern struct cscfg_config_desc pmu_pulse_etm4x; > #endif Reviewed-by: James Clark <james.clark(a)linaro.org>

1 week, 5 days

Re: [PATCH v4 6/7] coresight: etm4x: Report whether the PMU counts the external outputs

by James Clark

On 26/10/2026 05:48, Amir Ayupov wrote: > Some CPUs count the trace unit's external outputs as the PMU common > events TRCEXTOUT0-3 (0x4010-0x4013), which lets a configuration drive a > PMU event from trace unit events. Other CPUs, Neoverse N1 for example, > have no such events, and a feature relying on them would silently do > nothing there. > > Detect at probe, on the trace unit's CPU, whether the PMU counts every > external output: the trace unit has an external output for each of its > events (caps.nr_event), and pmuv3_event_implemented() reports whether > the PMU implements TRCEXTOUTn. Only check ETE: per its specification, an > implemented TRCEXTOUTn event counts external output n, while whether that > output is also an external input is IMPLEMENTATION DEFINED. > > Add a CS_CFG_MATCH_CAP_TRCEXTOUT capability match flag, set it on those > trace units, and show it in the feature's configfs 'matches' attribute. > With capabilities matched separately from the device class, a feature > that requires it only loads on those trace units. > > Assisted-by: Devmate:Opus-5.5 > Signed-off-by: Amir Ayupov <aaupov(a)fb.com> > --- > .../hwtracing/coresight/coresight-config.h | 2 ++ > .../hwtracing/coresight/coresight-etm4x-cfg.c | 6 ++++- > .../coresight/coresight-etm4x-core.c | 26 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ > .../coresight/coresight-syscfg-configfs.c | 3 +++ > 5 files changed, 39 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h > index 220bc54f8e5e1..4cf53230854d0 100644 > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -38,6 +38,8 @@ > * a device that matches one of its classes and has all of its capabilities. > */ > #define CS_CFG_MATCH_CAP_MASK GENMASK_U32(15, 8) > +/* the PMU counts the trace unit's external outputs as TRCEXTOUTn */ > +#define CS_CFG_MATCH_CAP_TRCEXTOUT BIT(8) > > /* > * Limit number of presets in a configuration > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > index 52cb036bb04b9..9e4dc5950c13d 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > @@ -176,9 +176,13 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, > > int etm4_cscfg_register(struct coresight_device *csdev) > { > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct cscfg_csdev_feat_ops ops; > + u32 match_flags = CS_CFG_ETM4_MATCH_FLAGS; > > ops.load_feat = &etm4_cfg_load_feature; > + if (drvdata->caps.trcextout) > + match_flags |= CS_CFG_MATCH_CAP_TRCEXTOUT; > > - return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); > + return cscfg_register_csdev(csdev, match_flags, &ops); > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index af017bd8a5477..cb5fbb0279b88 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -30,6 +30,7 @@ > #include <linux/uaccess.h> > #include <linux/perf_event.h> > #include <linux/perf/arm_pmu.h> > +#include <linux/perf/arm_pmuv3.h> > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > #include <linux/property.h> > @@ -1399,6 +1400,29 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps) > } > } > > +/* > + * Whether the PMU counts each external output of this trace unit as > + * TRCEXTOUTn. The trace unit has an external output for each of its events. > + * Only ETE is checked: per its specification, an implemented TRCEXTOUTn event > + * counts external output n. > + * > + * Must run on the CPU that owns the trace unit. > + */ > +static bool etm4_pmu_counts_extout(struct etmv4_drvdata *drvdata) > +{ > + int n; > + > + if (!etm4x_is_ete(drvdata) || !drvdata->caps.nr_event) > + return false; > + > + for (n = 0; n < drvdata->caps.nr_event; n++) { > + if (!pmuv3_event_implemented(ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 + n)) > + return false; > + } > + > + return true; > +} > + > static void etm4_init_arch_data(void *info) > { > u32 etmidr0; > @@ -1562,6 +1586,8 @@ static void etm4_init_arch_data(void *info) > /* NUMCNTR, bits[30:28] number of counters available for tracing */ > caps->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); > > + caps->trcextout = etm4_pmu_counts_extout(drvdata); > + > coresight_clear_self_claim_tag_unlocked(csa); > etm4_cs_lock(drvdata, csa); > cpu_detect_trace_filtering(drvdata); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 5417280cdb274..33994ad4b2641 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -868,6 +868,8 @@ enum etm_impdef_type { > * @lpoverride: If the implementation can support low-power state over. > * @skip_power_up: Indicates if an implementation can skip powering up > * the trace unit. > + * @trcextout: The trace unit is an ETE whose PMU counts its external > + * outputs as TRCEXTOUTn. > */ > struct etmv4_caps { > u8 nr_pe; > @@ -907,6 +909,7 @@ struct etmv4_caps { > bool atbtrig : 1; > bool lpoverride : 1; > bool skip_power_up : 1; > + bool trcextout : 1; > }; > > /** > diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c > index 2b40e556be872..7b3800138f625 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c > @@ -250,6 +250,9 @@ static ssize_t cscfg_feat_matches_show(struct config_item *item, char *page) > if (match_flags & CS_CFG_MATCH_CLASS_SRC_ETM4) > used += scnprintf(page + used, PAGE_SIZE - used, "SRC_ETMV4 "); > > + if (match_flags & CS_CFG_MATCH_CAP_TRCEXTOUT) > + used += scnprintf(page + used, PAGE_SIZE - used, "TRCEXTOUT "); > + > used += scnprintf(page + used, PAGE_SIZE - used, "\n"); > return used; > } Reviewed-by: James Clark <james.clark(a)linaro.org>

1 week, 5 days

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