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[PATCH v7 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v7: - Updated the commit log in patch 11 (Mike). - Link to v6: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-0-… Changes in v6: - Added a 'retain_ss_status' flag to indicate if need to restain single-shot status (Suzuki). - Introduced __etm4_disable_hw() without calling etm4_cs_{unlock|lock}() pairs, which is convenient for the save callback (Suzuki). - Link to v5: https://lore.kernel.org/r/20251103-arm_coresight_power_management_fix-v5-0-… Changes in v5: - Added more info for removing redundant DSB in etm4_{enable|disable}_trace_unit() (Suzuki/Levi). - Dropped moving isb() out from etm4_{enable|disable}_trace_unit() (Suzuki). - Reordered patches to move fixes earlier. - Link to v4: https://lore.kernel.org/r/20251024-arm_coresight_power_management_fix-v4-0-… Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the redundant DSB coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to retain single-shot status coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 358 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 64 +--- include/linux/coresight.h | 25 +- 4 files changed, 172 insertions(+), 334 deletions(-) --- base-commit: b139702a889692ec30702534ebb1ae2b11ed1cbf change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 weeks, 3 days

Re: [PATCH] coresight: etm-perf: Fix reference count leak in etm_setup_aux

by Suzuki K Poulose

Hi On 11/11/2025 14:42, Ma Ke wrote: > In etm_setup_aux(), when a user sink is obtained via > coresight_get_sink_by_id(), it increments the reference count of the > sink device. However, if the sink is used in path building, the path > holds a reference, but the initial reference from > coresight_get_sink_by_id() is not released, causing a reference count > leak. We should release the initial reference after the path is built. > > Found by code review. > > Cc: stable(a)vger.kernel.org > Fixes: 0e6c20517596 ("coresight: etm-perf: Allow an event to use different sinks") > Signed-off-by: Ma Ke <make24(a)iscas.ac.cn> > --- > drivers/hwtracing/coresight/coresight-etm-perf.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index f677c08233ba..6584f6aa87bf 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -453,6 +453,11 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > if (!event_data->snk_config) > goto err; > > + if (user_sink) { > + put_device(&user_sink->dev); > + user_sink = NULL; > + } > + I would recommend moving this to the out: label below, to make sure we drop the refcount even in the error path. Otherwise looks good to me. Suzuki > out: > return event_data; >

2 weeks, 4 days

[PATCH v4 0/6] Refactoring finding CPU phandles in DT

by Alireza Sanaee

This series refactor the way CPU IDs are retrieved from the device tree. Usually, there is a for loop that goes over every single CPU that can be avoided. This also reduces the amount of NULL pointer checks in drivers. I have abstracted away that loop and introduced a new function (of_cpu_node_to_id) for this. This patchset is a subset of [1], where I removed content and patches relevant to hyper-threaded cores for DT. Based on the discussion, the code refactor is still useful, hence this patchset. [1] https://lore.kernel.org/all/20250512080715.82-1-alireza.sanaee@huawei.co Changes since v3: - Rebased to d69eb204c255c35abd9e8cb621484e8074c75eaa Changes since v2: - Addressed Jonathan Cameron's comments. - Added reviewed-by tags. - Added a new commit where I suggest simplfing the code in arch_topology.c to remove the use of cpu_node on failure path. - Improve documentation. - Caught a bug in patch 1. - Commit message fixed for patch 2. Changes since v1: - Rebased on top of the latest mainline. - Addressed Krzysztof Kozlowski's comments -- Hopefully :-) - Addressed Jonathan Cameron's comments. Alireza Sanaee (6): of: add infra for finding CPU id from phandle arch_topology: drop the use of cpu_node in the pr_info arch_topology: update CPU map to use of_cpu_phandle_to_id coresight: cti: Use of_cpu_phandle_to_id for grabbing CPU id coresight: Use of_cpu_phandle_to_id for grabbing CPU ID perf/arm-dsu: refactor cpu id retrieval via new API of_cpu_phandle_to_id drivers/base/arch_topology.c | 22 ++++----- .../coresight/coresight-cti-platform.c | 13 +---- .../hwtracing/coresight/coresight-platform.c | 15 +----- drivers/of/cpu.c | 48 +++++++++++++++++++ drivers/perf/arm_dsu_pmu.c | 7 +-- include/linux/of.h | 9 ++++ 6 files changed, 71 insertions(+), 43 deletions(-) -- 2.43.0

2 weeks, 4 days

[PATCH v5 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v5: - Added more info for removing redundant DSB in etm4_{enable|disable}_trace_unit() (Suzuki/Levi). - Dropped moving isb() out from etm4_{enable|disable}_trace_unit() (Suzuki). - Reordered patches to move fixes earlier. - Link to v4: https://lore.kernel.org/r/20251024-arm_coresight_power_management_fix-v4-0-… Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the redundant DSB coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 347 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---- include/linux/coresight.h | 25 +- 4 files changed, 157 insertions(+), 336 deletions(-) --- base-commit: 6146a0f1dfae5d37442a9ddcba012add260bceb0 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 weeks, 4 days

Re: [PATCH v2 0/3] coresight: replace the void pointer with coresight_path pointer

by Suzuki K Poulose

On Thu, 25 Sep 2025 18:42:30 +0800, Jie Gan wrote: > Patch 1: > Fix the issue that the catu cannot correctly read the handle of the AUX > event which is caused by the commit[1]. > > [1] 080ee83cc361 ("Coresight: Change functions to accept the coresight_path") > > Exeception call trace: > tmc_etr_get_buffer+0x30/0x80 [coresight_tmc] (P) > catu_enable_hw+0xbc/0x3d0 [coresight_catu] > catu_enable+0x70/0xe0 [coresight_catu] > coresight_enable_path+0xb0/0x258 [coresight] > > [...] Applied, thanks! [1/3] coresight: tmc: add the handle of the event to the path https://git.kernel.org/coresight/c/aaa5abcc9d44 [2/3] coresight: change helper_ops to accept coresight_path https://git.kernel.org/coresight/c/94baedb51dea [3/3] coresight: change the sink_ops to accept coresight_path https://git.kernel.org/coresight/c/b139702a8896 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 weeks, 5 days

Re: [PATCH v3] coresight: ETR: Fix ETR buffer use-after-free issue

by Suzuki K Poulose

On Tue, 21 Oct 2025 16:45:25 +0800, Xiaoqi Zhuang wrote: > When ETR is enabled as CS_MODE_SYSFS, if the buffer size is changed > and enabled again, currently sysfs_buf will point to the newly > allocated memory(buf_new) and free the old memory(buf_old). But the > etr_buf that is being used by the ETR remains pointed to buf_old, not > updated to buf_new. In this case, it will result in a memory > use-after-free issue. > > [...] Applied, thanks! [1/1] coresight: ETR: Fix ETR buffer use-after-free issue https://git.kernel.org/coresight/c/35501ac3c7d4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 weeks, 1 day

Re: [PATCH] coresight: tpdm: remove redundant check for drvdata

by Suzuki K Poulose

On Fri, 07 Nov 2025 14:16:39 +0800, Jie Gan wrote: > Remove the redundant check for drvdata data because the drvdata here already > has been guarranted to be non-NULL. > > Applied, thanks! [1/1] coresight: tpdm: remove redundant check for drvdata https://git.kernel.org/coresight/c/aa5edd1b5ece Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 weeks, 1 day

Re: [PATCH] coresight: tpdm: remove redundant check for drvdata

by Suzuki K Poulose

On 07/11/2025 06:16, Jie Gan wrote: > Remove the redundant check for drvdata data because the drvdata here already > has been guarranted to be non-NULL. > > Fixes: 350ba15ae187 ("coresight-tpdm: Add nodes for dsb msr support") > Fixes: 8e8804145a46 ("coresight-tpdm: Add msr register support for CMB") This doesn't need to be backported as such, as it is a cleanup. I will drop the Fixes tag and merge this. Suzuki > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpdm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 0e3896c12f07..06e0a905a67d 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -1402,11 +1402,11 @@ static int tpdm_probe(struct device *dev, struct resource *res) > if (ret) > return ret; > > - if (drvdata && tpdm_has_dsb_dataset(drvdata)) > + if (tpdm_has_dsb_dataset(drvdata)) > of_property_read_u32(drvdata->dev->of_node, > "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > > - if (drvdata && tpdm_has_cmb_dataset(drvdata)) > + if (tpdm_has_cmb_dataset(drvdata)) > of_property_read_u32(drvdata->dev->of_node, > "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); > } else { > > --- > base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c > change-id: 20251107-fix_tpdm_redundant_check-a5a7bad4b7c8 > prerequisite-change-id: 20251028-add_static_tpdm_support-1f62477857e2:v4 > prerequisite-patch-id: eda8dd6884b831cb10affc22477aece39c78b408 > prerequisite-patch-id: 7beb8b17d54ff21bc57eab10b56e6ffcfa4d1963 > prerequisite-patch-id: f6f1e78dba3f1d3b1191ab827adab5a3b7b2326a > > Best regards,

3 weeks, 1 day

[PATCH] coresight: tmc: Prevent sysfs parameter changes if sink in use

by Mike Leach

The sysfs files that change the operational parameters for TMC buffer_size, stop_on_flush and trigger_cntr are writable when the TMC is in use. The new values will have no effect and be silently ignored. Alter the sysfs functions to return -EBUSY if the TMC is currently in use, and also protect the write values using the spinlock. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- .../hwtracing/coresight/coresight-tmc-core.c | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 36599c431be6..a1216a1f9681 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -489,15 +489,24 @@ static ssize_t trigger_cntr_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long val, flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = kstrtoul(buf, 16, &val); if (ret) return ret; + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } drvdata->trigger_cntr = val; - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(trigger_cntr); @@ -514,7 +523,7 @@ static ssize_t buffer_size_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long val, flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); /* Only permitted for TMC-ETRs */ @@ -527,8 +536,18 @@ static ssize_t buffer_size_store(struct device *dev, /* The buffer size should be page aligned */ if (val & (PAGE_SIZE - 1)) return -EINVAL; + + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } drvdata->size = val; - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(buffer_size); @@ -547,17 +566,27 @@ static ssize_t stop_on_flush_store(struct device *dev, { int ret; u8 val; + unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = kstrtou8(buf, 0, &val); if (ret) return ret; + + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } if (val) drvdata->stop_on_flush = true; else drvdata->stop_on_flush = false; - - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(stop_on_flush); -- 2.32.0

3 weeks, 2 days

Re: [subset] [PATCH v4 0/3] coresight: add static TPDM support

by Suzuki K Poulose

On Tue, 28 Oct 2025 18:11:39 +0800, Jie Gan wrote: > The static TPDM function as a dummy source, however, it is essential > to enable the port connected to the TPDA and configure the element size. > Without this, the TPDA cannot correctly receive trace data from the > static TPDM. Since the static TPDM does not require MMIO mapping to > access its registers, a clock controller is not mandatory for its > operation. > > [...] Applied, thanks! [1/3] dt-bindings: arm: document the static TPDM compatible https://git.kernel.org/coresight/c/8d204b6f1f7a [2/3] coresight: tpdm: add static tpdm support https://git.kernel.org/coresight/c/14ae052f7947 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 weeks, 2 days

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