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Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

On 05/01/2022 11:16, Anshuman Khandual wrote: > > > On 1/5/22 3:43 PM, Suzuki K Poulose wrote: >> Hi Anshuman >> >> On 05/01/2022 05:05, Anshuman Khandual wrote: >>> TRBE implementations affected by Arm erratum #2038923 might get TRBE into >>> an inconsistent view on whether trace is prohibited within the CPU. As a >>> result, the trace buffer or trace buffer state might be corrupted. This >>> happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, >>> followed by just a single context synchronization event before execution >>> changes from a context, in which trace is prohibited to one where it isn't, >>> or vice versa. In these mentioned conditions, the view of whether trace is >>> prohibited is inconsistent between parts of the CPU, and the trace buffer >>> or the trace buffer state might be corrupted. >>> >>> Work around this problem in the TRBE driver by preventing an inconsistent >>> view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by >>> immediately following a change to TRBLIMITR_EL1.E with at least one ISB >>> instruction before an ERET, or two ISB instructions if no ERET is to take >>> place. This adds a new cpu errata in arm64 errata framework and also >>> updates TRBE driver as required. >>> >>> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >>> Cc: Will Deacon <will(a)kernel.org> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> >>> Cc: coresight(a)lists.linaro.org >>> Cc: linux-doc(a)vger.kernel.org >>> Cc: linux-arm-kernel(a)lists.infradead.org >>> Cc: linux-kernel(a)vger.kernel.org >>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> --- >>> Documentation/arm64/silicon-errata.rst | 2 + >>> arch/arm64/Kconfig | 23 ++++++++++ >>> arch/arm64/kernel/cpu_errata.c | 9 ++++ >>> arch/arm64/tools/cpucaps | 1 + >>> drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- >>> 5 files changed, 72 insertions(+), 10 deletions(-) >> >> As with the previous patch, it may be a good idea to split the >> patch to arm64 and trbe parts. > > Sure, will do. > >> >>> >>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >>> index c9b30e6c2b6c..e0ef3e9a4b8b 100644 >>> --- a/Documentation/arm64/silicon-errata.rst >>> +++ b/Documentation/arm64/silicon-errata.rst >>> @@ -54,6 +54,8 @@ stable kernels. >>> +----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | >>> +----------------+-----------------+-----------------+-----------------------------+ >>> +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | >>> ++----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | >>> +----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | >>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>> index 2105b68d88db..026e34fb6fad 100644 >>> --- a/arch/arm64/Kconfig >>> +++ b/arch/arm64/Kconfig >>> @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 >>> If unsure, say Y. >>> +config ARM64_ERRATUM_2038923 >>> + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" >>> + depends on CORESIGHT_TRBE >>> + default y >>> + help >>> + This option adds the workaround for ARM Cortex-A510 erratum 2038923. >>> + >>> + Affected Cortex-A510 core might cause an inconsistent view on whether trace is >>> + prohibited within the CPU. As a result, the trace buffer or trace buffer state >>> + might be corrupted. This happens after TRBE buffer has been enabled by setting >>> + TRBLIMITR_EL1.E, followed by just a single context synchronization event before >>> + execution changes from a context, in which trace is prohibited to one where it >>> + isn't, or vice versa. In these mentioned conditions, the view of whether trace >>> + is prohibited is inconsistent between parts of the CPU, and the trace buffer or >>> + the trace buffer state might be corrupted. >>> + >>> + Work around this in the driver by preventing an inconsistent view of whether the >>> + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a >>> + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or >>> + two ISB instructions if no ERET is to take place. >>> + >>> + If unsure, say Y. >>> + >>> config CAVIUM_ERRATUM_22375 >>> bool "Cavium erratum 22375, 24313" >>> default y >>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >>> index cbb7d5a9aee7..60b0c1f1d912 100644 >>> --- a/arch/arm64/kernel/cpu_errata.c >>> +++ b/arch/arm64/kernel/cpu_errata.c >>> @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>> ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>> }, >>> #endif >>> +#ifdef CONFIG_ARM64_ERRATUM_2038923 >>> + { >>> + .desc = "ARM erratum 2038923", >>> + .capability = ARM64_WORKAROUND_2038923, >>> + >>> + /* Cortex-A510 r0p0 - r0p2 */ >>> + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>> + }, >>> +#endif >>> { >>> } >>> }; >>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >>> index fca3cb329e1d..45a06d36d080 100644 >>> --- a/arch/arm64/tools/cpucaps >>> +++ b/arch/arm64/tools/cpucaps >>> @@ -56,6 +56,7 @@ WORKAROUND_1463225 >>> WORKAROUND_1508412 >>> WORKAROUND_1542419 >>> WORKAROUND_2064142 >>> +WORKAROUND_2038923 >>> WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>> WORKAROUND_TSB_FLUSH_FAILURE >>> WORKAROUND_TRBE_WRITE_OUT_OF_RANGE >>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>> index ec24b62b2cec..0689c6dab96d 100644 >>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>> @@ -92,11 +92,13 @@ struct trbe_buf { >>> #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 >>> #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 >>> #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 >>> +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 >>> static int trbe_errata_cpucaps[] = { >>> [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, >>> [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, >>> [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, >>> + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, >>> -1, /* Sentinel, must be the last entry */ >>> }; >>> @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) >>> return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); >>> } >>> +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) >>> +{ >> >> minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? > > trbe_needs_ctxt_sync_after_enable() sounds better. Also will have to change > the index above as well .. TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE. > >> >>> + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); >>> +} >>> + >>> static int trbe_alloc_node(struct perf_event *event) >>> { >>> if (event->cpu == -1) >>> @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) >>> dsb(nsh); >>> } >>> +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) >>> +{ >>> + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); >> >> minor nit: This implies we do the TRBE programming in the following >> manner in the common case (i.e, TRBE enabled in the beginning of a >> session). >> -> set TRBE LIMIT >> -> read TRBE LIMIT >> -> set TRBE ENABLED >> >> Could we please optimize this ? I believe the buf->trbe_limit >> must hold the LIMITR value at any point in time. And thus this > > But is not bit risky though ! We have got the following places where > given trbe_limit instance changes its value. > > drivers/../coresight-trbe.c: buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; > drivers/../coresight-trbe.c: buf->trbe_limit = compute_trbe_buffer_limit(handle); > drivers/../coresight-trbe.c: buf->trbe_limit -= PAGE_SIZE; Those are the places where we compute the trbe_limit, *before* we enable the TRBE. And we don't change recompute the limit *without disabling* the TRBE. To make it more clear, the only place where we set TRBE enabled without "computing" the trbe_limit is when we hit a spurious interrupt. But the value in the TRBLIMITR should already match the buf->trbe_limit and we are only going to re-enable the TRBE with the same limit. The other option is to pass down the "limit" to the set_trbe_enabled(). > >> function could simply be : >> >> set_trbe_enabled(trbe_buf) >> { >> limitr = trbe_buf->limit | LIMITR_ENABLE >> write(limitr, TRBLIMITR_EL1); >> ... >> } > > Is the potential for performance improvement here, out weigh possible > risks of using buf->trbe_limit directly while enabling the TRBE ? I somehow don't like the fact that we have additional write and read for the most common case of the TRBE usage (i.e, for arm_trbe_enable()). If we could avoid that, that may be better. Cheers Suzuki

3 years, 5 months

Re: [PATCH 4/4] coresight: trbe: Workaround TRBE trace data corruption

by Suzuki K Poulose

On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #1902691 might corrupt trace > data or deadlock, when it's being written into the memory. Workaround this > problem in the driver, by preventing TRBE initialization on affected cpus. > This adds a new cpu errata in arm64 errata framework and also updates TRBE > driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 16 ++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++ > 5 files changed, 40 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index e0ef3e9a4b8b..50018f60c4d4 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -56,6 +56,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 026e34fb6fad..1ea5c3b4aac0 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -819,6 +819,22 @@ config ARM64_ERRATUM_2038923 > > If unsure, say Y. > > +config ARM64_ERRATUM_1902691 > + bool "Cortex-A510: 1902691: workaround TRBE trace corruption" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 1902691. > + > + Affected Cortex-A510 core might cause trace data corruption, when being written > + into the memory. Effectively TRBE is broken and hence cannot be used to capture > + trace data. > + > + Work around this problem in the driver by just preventing TRBE initialization on > + affected cpus. > + > + If unsure, say Y. > + It might be better to add : "The firmware must have disabled the access to TRBE for the kernel on such implementations. This will cover the kernel for any firmware that doesn't do this already" > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 60b0c1f1d912..a3336dfb5a8a 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -615,6 +615,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > /* Cortex-A510 r0p0 - r0p2 */ > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_1902691 > + { > + .desc = "ARM erratum 1902691", > + .capability = ARM64_WORKAROUND_1902691, > + > + /* Cortex-A510 r0p0 - r0p1 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 45a06d36d080..e7719e8f18de 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -57,6 +57,7 @@ WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > WORKAROUND_2038923 > +WORKAROUND_1902691 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 0689c6dab96d..b9b4e34fac15 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -93,12 +93,14 @@ struct trbe_buf { > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > #define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 > +#define TRBE_IS_BROKEN 4 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, > [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, > + [TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -181,6 +183,11 @@ static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); > } > > +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_IS_BROKEN); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -1291,6 +1298,11 @@ static void arm_trbe_probe_cpu(void *info) > */ > trbe_check_errata(cpudata); > > + if (trbe_is_broken(cpudata)) { > + pr_err("TRBE might corrupt the trace on cpu %d\n", cpu); It may be better to say: "Disabling TRBE on CPU%d due to erratum" Otherwise looks good to me. Suzuki

3 years, 5 months

Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

Hi Anshuman On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2038923 might get TRBE into > an inconsistent view on whether trace is prohibited within the CPU. As a > result, the trace buffer or trace buffer state might be corrupted. This > happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, > followed by just a single context synchronization event before execution > changes from a context, in which trace is prohibited to one where it isn't, > or vice versa. In these mentioned conditions, the view of whether trace is > prohibited is inconsistent between parts of the CPU, and the trace buffer > or the trace buffer state might be corrupted. > > Work around this problem in the TRBE driver by preventing an inconsistent > view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by > immediately following a change to TRBLIMITR_EL1.E with at least one ISB > instruction before an ERET, or two ISB instructions if no ERET is to take > place. This adds a new cpu errata in arm64 errata framework and also > updates TRBE driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 + > arch/arm64/Kconfig | 23 ++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 ++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- > 5 files changed, 72 insertions(+), 10 deletions(-) As with the previous patch, it may be a good idea to split the patch to arm64 and trbe parts. > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index c9b30e6c2b6c..e0ef3e9a4b8b 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -54,6 +54,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 2105b68d88db..026e34fb6fad 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 > > If unsure, say Y. > > +config ARM64_ERRATUM_2038923 > + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 2038923. > + > + Affected Cortex-A510 core might cause an inconsistent view on whether trace is > + prohibited within the CPU. As a result, the trace buffer or trace buffer state > + might be corrupted. This happens after TRBE buffer has been enabled by setting > + TRBLIMITR_EL1.E, followed by just a single context synchronization event before > + execution changes from a context, in which trace is prohibited to one where it > + isn't, or vice versa. In these mentioned conditions, the view of whether trace > + is prohibited is inconsistent between parts of the CPU, and the trace buffer or > + the trace buffer state might be corrupted. > + > + Work around this in the driver by preventing an inconsistent view of whether the > + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a > + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or > + two ISB instructions if no ERET is to take place. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index cbb7d5a9aee7..60b0c1f1d912 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > #endif > +#ifdef CONFIG_ARM64_ERRATUM_2038923 > + { > + .desc = "ARM erratum 2038923", > + .capability = ARM64_WORKAROUND_2038923, > + > + /* Cortex-A510 r0p0 - r0p2 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > + }, > +#endif > { > } > }; > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index fca3cb329e1d..45a06d36d080 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -56,6 +56,7 @@ WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > +WORKAROUND_2038923 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index ec24b62b2cec..0689c6dab96d 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -92,11 +92,13 @@ struct trbe_buf { > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, > + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); > } > > +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) > +{ minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? > + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) > dsb(nsh); > } > > +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) > +{ > + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); minor nit: This implies we do the TRBE programming in the following manner in the common case (i.e, TRBE enabled in the beginning of a session). -> set TRBE LIMIT -> read TRBE LIMIT -> set TRBE ENABLED Could we please optimize this ? I believe the buf->trbe_limit must hold the LIMITR value at any point in time. And thus this function could simply be : set_trbe_enabled(trbe_buf) { limitr = trbe_buf->limit | LIMITR_ENABLE write(limitr, TRBLIMITR_EL1); ... } Otherwise looks good to me Suzuki

3 years, 5 months

Re: [PATCH 1/4] arm64: Add Cortex-A510 CPU part definition

by Suzuki K Poulose

On 05/01/2022 05:05, Anshuman Khandual wrote: > Add the CPU Partnumbers for the new Arm designs. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 19b8441aa8f2..e8fdc10395b6 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -73,6 +73,7 @@ > #define ARM_CPU_PART_CORTEX_A76 0xD0B > #define ARM_CPU_PART_NEOVERSE_N1 0xD0C > #define ARM_CPU_PART_CORTEX_A77 0xD0D > +#define ARM_CPU_PART_CORTEX_A510 0xD46 > #define ARM_CPU_PART_CORTEX_A710 0xD47 > #define ARM_CPU_PART_NEOVERSE_N2 0xD49 Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 5 months

Re: [PATCH 2/4] coresight: trbe: Work around the ignored system register writes

by Suzuki K Poulose

Hi Anshuman On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2064142 might fail to write > into certain system registers after the TRBE has been disabled. Under some > conditions after TRBE has been disabled, writes into certain TRBE registers > TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be > ignored and not be effected. > > Work around this problem in the TRBE driver by executing TSB CSYNC and DSB > just after the trace collection has stopped and before performing a system > register write to one of the affected registers. This adds a new cpu errata > in arm64 errata framework and also updates TRBE driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 + > arch/arm64/Kconfig | 18 +++++++ > arch/arm64/kernel/cpu_errata.c | 9 ++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 54 ++++++++++++++------ > drivers/hwtracing/coresight/coresight-trbe.h | 8 --- > 6 files changed, 68 insertions(+), 24 deletions(-) I think it may be a good idea to split the patch into two parts : - arm64 kernel part. (cpucap defintions and detection) - trbe driver part So that it is easier to merge these series upstream to avoid conflicts. > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 5342e895fb60..c9b30e6c2b6c 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -52,6 +52,8 @@ stable kernels. > | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index c4207cf9bb17..2105b68d88db 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -778,6 +778,24 @@ config ARM64_ERRATUM_2224489 > > If unsure, say Y. > > +config ARM64_ERRATUM_2064142 > + bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 2064142. > + > + Affected Cortex-A510 core might fail to write into system registers after the > + TRBE has been disabled. Under some conditions after the TRBE has been disabled > + writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, > + and TRBTRG_EL1 will be ignored and will not be effected. > + > + Work around this in the driver by executing TSB CSYNC and DSB after collection > + is stopped and before performing a system register write to one of the affected > + registers. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 9e1c1aef9ebd..cbb7d5a9aee7 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -597,6 +597,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2064142 > + { > + .desc = "ARM erratum 2064142", > + .capability = ARM64_WORKAROUND_2064142, > + > + /* Cortex-A510 r0p0 - r0p2 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 870c39537dd0..fca3cb329e1d 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -55,6 +55,7 @@ WORKAROUND_1418040 > WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > +WORKAROUND_2064142 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 276862c07e32..ec24b62b2cec 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -91,10 +91,12 @@ struct trbe_buf { > */ > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > +#define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > + [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, super minor nit: TRBE_NEEDS_DRAIN_AFTER_DISABLE ? > -1, /* Sentinel, must be the last entry */ > }; > > @@ -167,6 +169,11 @@ static inline bool trbe_may_write_out_of_range(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_WRITE_OUT_OF_RANGE); > } > > +static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) > +{ minor nit: trbe_needs_drain_after_disable() ? Either ways, the patch looks good to me. Suzuki

3 years, 5 months

Re: [RFC V3 PATCH] coresight: change tmc from misc device to cdev device

by Mathieu Poirier

Good day Jay, For your next iteration, please remove the "RFC" from the patch title, we are well pass that now. On Tue, Dec 21, 2021 at 08:04:37PM +0800, Jay Chen wrote: > Currently, there are 130 etr and etf on our machine, > but the current coresight tmc driver uses misc_register > to register the device, which leads to the error that > the device number is not enough. > > coresight-tmc: probe of xxxxx failed with error -16 > > This patch changes the device registration method > to cdev's dynamic registration method to solve the > problem of insufficient device numbers. This is much better. > > Signed-off-by: Jay Chen <jkchen(a)linux.alibaba.com> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 91 +++++++++++++++---- > drivers/hwtracing/coresight/coresight-tmc.h | 10 +- > 2 files changed, 83 insertions(+), 18 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index d0276af82494..0d51071e9f88 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,6 +31,12 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > +static DEFINE_IDA(tmc_ida); > +static dev_t tmc_major; > +static struct class *tmc_class; > + > +#define TMC_DEV_MAX (MINORMASK + 1) > + > void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > struct coresight_device *csdev = drvdata->csdev; > @@ -147,7 +153,7 @@ static int tmc_open(struct inode *inode, struct file *file) > { > int ret; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > > ret = tmc_read_prepare(drvdata); > if (ret) > @@ -179,7 +185,7 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len, > char *bufp; > ssize_t actual; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); > if (actual <= 0) > return 0; > @@ -200,7 +206,7 @@ static int tmc_release(struct inode *inode, struct file *file) > { > int ret; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > > ret = tmc_read_unprepare(drvdata); > if (ret) > @@ -451,6 +457,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > { > int ret = 0; > u32 devid; > + dev_t devt; > void __iomem *base; > struct device *dev = &adev->dev; > struct coresight_platform_data *pdata = NULL; > @@ -546,14 +553,32 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > goto out; > } > > - drvdata->miscdev.name = desc.name; > - drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; > - drvdata->miscdev.fops = &tmc_fops; > - ret = misc_register(&drvdata->miscdev); > + ret = ida_simple_get(&tmc_ida, 0, TMC_DEV_MAX, GFP_KERNEL); > + if (ret < 0) > + goto err_coresight_unregister; > + > + cdev_init(&drvdata->cdev.cdev, &tmc_fops); > + drvdata->cdev.cdev.owner = THIS_MODULE; > + devt = MKDEV(MAJOR(tmc_major), ret); > + ret = cdev_add(&drvdata->cdev.cdev, devt, 1); > if (ret) > - coresight_unregister(drvdata->csdev); > - else > + goto err_free_tmc_ida; > + > + drvdata->cdev.dev = device_create(tmc_class, NULL, devt, &drvdata->cdev, desc.name); > + if (IS_ERR(drvdata->cdev.dev)) { > + ret = PTR_ERR(drvdata->cdev.dev); > + goto err_delete_cdev; > + } else > pm_runtime_put(&adev->dev); > + > + return 0; > + > +err_delete_cdev: > + cdev_del(&drvdata->cdev.cdev); > +err_free_tmc_ida: > + ida_simple_remove(&tmc_ida, MINOR(devt)); > +err_coresight_unregister: > + coresight_unregister(drvdata->csdev); > out: > return ret; > } > @@ -583,13 +608,11 @@ static void tmc_shutdown(struct amba_device *adev) > static void tmc_remove(struct amba_device *adev) > { > struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + struct device *dev = drvdata->cdev.dev; > > - /* > - * Since misc_open() holds a refcount on the f_ops, which is > - * etb fops in this case, device is there until last file > - * handler to this device is closed. > - */ > - misc_deregister(&drvdata->miscdev); > + ida_simple_remove(&tmc_ida, dev->devt); ida_simple_remove(&tmc_ida, MINOR(dev->devt)); > + device_destroy(tmc_class, dev->devt); > + cdev_del(&drvdata->cdev.cdev); > coresight_unregister(drvdata->csdev); > } > > @@ -618,7 +641,43 @@ static struct amba_driver tmc_driver = { > .id_table = tmc_ids, > }; > > -module_amba_driver(tmc_driver); > +static int __init tmc_init(void) > +{ > + int ret; > + > + ret = alloc_chrdev_region(&tmc_major, 0, TMC_DEV_MAX, "tmc"); > + if (ret < 0) { > + pr_err("tmc: failed to allocate char dev region\n"); > + return ret; > + } > + > + tmc_class = class_create(THIS_MODULE, "tmc"); > + if (IS_ERR(tmc_class)) { > + pr_err("tmc: failed to create class\n"); > + ret = PTR_ERR(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > + return ret; You can simply return PTR_ERR(tmc_class)... > + } > + > + ret = amba_driver_register(&tmc_driver); > + if (ret) { > + pr_err("tmc: error registering amba driver\n"); > + class_destroy(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > + } > + > + return ret; > +} > + > +static void __exit tmc_exit(void) > +{ > + amba_driver_unregister(&tmc_driver); > + class_destroy(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > +} > + > +module_init(tmc_init); > +module_exit(tmc_exit); > > MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 6bec20a392b3..b65ac363f9e4 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -7,6 +7,7 @@ > #ifndef _CORESIGHT_TMC_H > #define _CORESIGHT_TMC_H > > +#include <linux/cdev.h> > #include <linux/dma-mapping.h> > #include <linux/idr.h> > #include <linux/miscdevice.h> miscdevice.h can likely be removed in both .c and .h files. Thanks, Mathieu > @@ -163,11 +164,16 @@ struct etr_buf { > void *private; > }; > > +struct tmc_cdev { > + struct cdev cdev; > + struct device *dev; > +}; > + > /** > * struct tmc_drvdata - specifics associated to an TMC component > * @base: memory mapped base address for this component. > * @csdev: component vitals needed by the framework. > - * @miscdev: specifics to handle "/dev/xyz.tmc" entry. > + * @tmc_cdev: specifics to handle "/dev/xyz.tmc" entry. > * @spinlock: only one at a time pls. > * @pid: Process ID of the process being monitored by the session > * that is using this component. > @@ -191,7 +197,7 @@ struct etr_buf { > struct tmc_drvdata { > void __iomem *base; > struct coresight_device *csdev; > - struct miscdevice miscdev; > + struct tmc_cdev cdev; > spinlock_t spinlock; > pid_t pid; > bool reading; > -- > 2.27.0 >

3 years, 5 months

[GIT PULL] Coresight changes for v5.17

by Mathieu Poirier

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.17 for you to fetch changes up to efa56eddf5d5c03a90abe708431f16c12c291837: coresight: core: Fix typo in a comment (2021-12-13 11:54:07 -0700) ---------------------------------------------------------------- Coresight changes for v5.17 Hi Greg, I'm sending this a little early due to the holiday schedule. There might be another pull request for rc8 in January - let's see when we get there. This pull request includes: - A patch that uses devm_bitmap_zalloc() instead of the open-coded equivalent. - Work to make coresight complex configuration loadable via modules. - Some coresight documentation updates. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Christophe JAILLET (1): coresight: Use devm_bitmap_zalloc when applicable Jason Wang (1): coresight: core: Fix typo in a comment Mike Leach (7): Documentation: coresight: Fix documentation issue coresight: configuration: Update API to introduce load owner concept coresight: configuration: Update API to permit dynamic load/unload coresight: syscfg: Update load API for config loadable modules coresight: syscfg: Example CoreSight configuration loadable module coresight: configfs: Allow configfs to activate configuration Documentation: coresight: Update coresight configuration docs Documentation/trace/coresight/coresight-config.rst | 78 ++++- MAINTAINERS | 1 + .../hwtracing/coresight/coresight-cfg-preload.c | 9 +- drivers/hwtracing/coresight/coresight-config.h | 9 +- drivers/hwtracing/coresight/coresight-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 +- drivers/hwtracing/coresight/coresight-stm.c | 10 +- .../coresight/coresight-syscfg-configfs.c | 87 ++++++ .../coresight/coresight-syscfg-configfs.h | 4 + drivers/hwtracing/coresight/coresight-syscfg.c | 315 +++++++++++++++++++-- drivers/hwtracing/coresight/coresight-syscfg.h | 39 ++- samples/Kconfig | 9 + samples/Makefile | 1 + samples/coresight/Makefile | 4 + samples/coresight/coresight-cfg-sample.c | 73 +++++ 15 files changed, 595 insertions(+), 57 deletions(-) create mode 100644 samples/coresight/Makefile create mode 100644 samples/coresight/coresight-cfg-sample.c

3 years, 6 months

[PATCH v3] drivers/coresight: Add Ultrasoc System Memory Buffer driver

by Qi Liu

This patch adds driver for Ultrasoc SMB(System Memory Buffer) device. SMB provides a way to buffer messages from ETM, and store these CPU instructions in system memory. SMB is developed by Ultrasoc technology, which is acquired by Siemens, and we still use "Ultrasoc" to name driver. Signed-off-by: Qi Liu <liuqi115(a)huawei.com> Tested-by: JunHao He <hejunhao2(a)hisilicon.com> --- Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight. - Link:https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of Ultrasoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move ultrasoc driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/ultrasoc-smb.c | 607 +++++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 116 ++++ 4 files changed, 737 insertions(+) create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 514a9b8086e3..d24a5d95153a 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,16 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. + +config ULTRASOC_SMB + tristate "Ultrasoc system memory buffer drivers" + depends on ARM64 && CORESIGHT + help + This driver provides support for the Ultrasoc system memory buffer (SMB). + SMB is responsible for receiving the trace data from Coresight ETM devices + and storing them to a system buffer. + + To compile this driver as a module, choose M here: the module will be + called ultrasoc-smb. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..2899e5a5d5cd 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -27,3 +27,5 @@ obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o + +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c new file mode 100644 index 000000000000..b477fc51fbbb --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 HiSilicon Limited. + * + * Code herein communicates with and accesses proprietary hardware which is + * licensed intellectual property (IP) belonging to Siemens Digital Industries + * Software Ltd. + * + * Siemens Digital Industries Software Ltd. asserts and reserves all rights to + * their intellectual property. This paragraph may not be removed or modified + * in any way without permission from Siemens Digital Industries Software Ltd. + */ + +#include <linux/acpi.h> +#include <linux/circ_buf.h> +#include <linux/err.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include "ultrasoc-smb.h" + +DEFINE_CORESIGHT_DEVLIST(sink_devs, "sink_smb"); + +static bool smb_buffer_is_empty(struct smb_drv_data *drvdata) +{ + u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS); + + return buf_status & BIT(0) ? false : true; +} + +static bool smb_buffer_cmp_pointer(struct smb_drv_data *drvdata) +{ + u32 wr_offset, rd_offset; + + wr_offset = readl(drvdata->base + SMB_LB_WR_ADDR); + rd_offset = readl(drvdata->base + SMB_LB_RD_ADDR); + return wr_offset == rd_offset; +} + +static void smb_reset_buffer_status(struct smb_drv_data *drvdata) +{ + writel(0xf, drvdata->base + SMB_LB_INT_STS); +} + +/* Purge data remaining in hardware path to SMB. */ +static void smb_purge_data(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_LB_PURGE); +} + +static void smb_update_data_size(struct smb_drv_data *drvdata) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + u32 write_offset; + + smb_purge_data(drvdata); + if (smb_buffer_cmp_pointer(drvdata)) { + if (smb_buffer_is_empty(drvdata)) + sdb->data_size = 0; + else + sdb->data_size = sdb->buf_size; + return; + } + + write_offset = readl(drvdata->base + SMB_LB_WR_ADDR) - sdb->start_addr; + sdb->data_size = CIRC_CNT(write_offset, sdb->rd_offset, sdb->buf_size); +} + +static int smb_open(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + + if (local_cmpxchg(&drvdata->reading, 0, 1)) + return -EBUSY; + + return 0; +} + +static ssize_t smb_read(struct file *file, char __user *data, size_t len, loff_t *ppos) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct device *dev = &drvdata->csdev->dev; + unsigned long flags; + int to_copy = 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (!sdb->data_size) { + smb_update_data_size(drvdata); + if (!sdb->data_size) + goto out; + } + + if (atomic_read(drvdata->csdev->refcnt)) { + to_copy = -EBUSY; + goto out; + } + + to_copy = min(sdb->data_size, len); + + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + to_copy > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + + if (copy_to_user(data, (void *)sdb->buf_base + sdb->rd_offset, to_copy)) { + dev_dbg(dev, "Failed to copy data to user.\n"); + to_copy = -EFAULT; + goto out; + } + + *ppos += to_copy; + sdb->data_size -= to_copy; + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + dev_dbg(dev, "%d bytes copied.\n", to_copy); +out: + if (!sdb->data_size) + smb_reset_buffer_status(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return to_copy; +} + +static int smb_release(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + local_set(&drvdata->reading, 0); + return 0; +} + +static const struct file_operations smb_fops = { + .owner = THIS_MODULE, + .open = smb_open, + .read = smb_read, + .release = smb_release, + .llseek = no_llseek, +}; + +smb_simple_func(struct smb_drv_data, read_pos, SMB_LB_RD_ADDR); +smb_simple_func(struct smb_drv_data, write_pos, SMB_LB_WR_ADDR); +smb_simple_func(struct smb_drv_data, buf_status, SMB_LB_INT_STS); + +static ssize_t buf_size_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size); +} +static DEVICE_ATTR_RO(buf_size); + +static struct attribute *smb_sink_attrs[] = { + &dev_attr_read_pos.attr, + &dev_attr_write_pos.attr, + &dev_attr_buf_status.attr, + &dev_attr_buf_size.attr, + NULL, +}; + +static const struct attribute_group smb_sink_group = { + .attrs = smb_sink_attrs, + .name = "status", +}; + +static const struct attribute_group *smb_sink_groups[] = { + &smb_sink_group, + NULL, +}; + +static int smb_set_perf_buffer(struct perf_output_handle *handle) +{ + struct cs_buffers *buf = etm_perf_sink_config(handle); + u32 head; + + if (!buf) + return -EINVAL; + + /* Wrap head around to the amount of space we have */ + head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + + /* Find the page to write to and offset within that page */ + buf->cur = head / PAGE_SIZE; + buf->offset = head % PAGE_SIZE; + + local_set(&buf->data_size, 0); + + return 0; +} + +static void smb_enable_hw(struct smb_drv_data *drvdata) +{ + writel(0x1, drvdata->base + SMB_GLOBAL_EN); +} + +static void smb_disable_hw(struct smb_drv_data *drvdata) +{ + writel(0x0, drvdata->base + SMB_GLOBAL_EN); +} + +static int smb_enable_sysfs(struct smb_drv_data *drvdata) +{ + if (drvdata->mode == CS_MODE_PERF) + return -EBUSY; + + if (drvdata->mode == CS_MODE_SYSFS) + return 0; + + smb_enable_hw(drvdata); + drvdata->mode = CS_MODE_SYSFS; + return 0; +} + +static int smb_enable_perf(struct smb_drv_data *drvdata, void *data) +{ + struct device *dev = &drvdata->csdev->dev; + struct perf_output_handle *handle = data; + pid_t pid; + + if (drvdata->mode == CS_MODE_SYSFS) { + dev_err(dev, "Device is already in used by sysfs.\n"); + return -EBUSY; + } + + /* Get a handle on the pid of the target process*/ + pid = task_pid_nr(handle->event->owner); + if (drvdata->pid != -1 && drvdata->pid != pid) { + dev_err(dev, "Device is already in used by other session.\n"); + return -EBUSY; + } + /* The sink is already enabled by this session. */ + if (drvdata->pid == pid) + return 0; + + if (smb_set_perf_buffer(handle)) + return -EINVAL; + + smb_enable_hw(drvdata); + drvdata->pid = pid; + drvdata->mode = CS_MODE_PERF; + + return 0; +} + +static int smb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + int ret = -EINVAL; + + /* Do nothing if trace data is reading by other interface now. */ + if (local_read(&drvdata->reading)) + return -EBUSY; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (mode == CS_MODE_SYSFS) + ret = smb_enable_sysfs(drvdata); + + if (mode == CS_MODE_PERF) + ret = smb_enable_perf(drvdata, data); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + if (ret) + return ret; + + atomic_inc(csdev->refcnt); + dev_dbg(&csdev->dev, "Ultrasoc SMB enabled.\n"); + + return 0; +} + +static int smb_disable(struct coresight_device *csdev) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + smb_disable_hw(drvdata); + + /* + * Data remaining in hardware path will be sent to SMB after purge, so needs to + * synchronize the read pointer to write pointer in perf mode. + */ + smb_purge_data(drvdata); + if (drvdata->mode == CS_MODE_PERF) + writel(readl(drvdata->base + SMB_LB_WR_ADDR), drvdata->base + SMB_LB_RD_ADDR); + + /* Dissociate from the target process. */ + drvdata->pid = -1; + drvdata->mode = CS_MODE_DISABLED; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_dbg(&csdev->dev, "Ultrasoc SMB disabled.\n"); + return 0; +} + +static void *smb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) +{ + struct cs_buffers *buf; + int node; + + node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->snapshot = overwrite; + buf->nr_pages = nr_pages; + buf->data_pages = pages; + + return buf; +} + +static void smb_free_buffer(void *config) +{ + struct cs_buffers *buf = config; + + kfree(buf); +} + +static void smb_sync_perf_buffer(struct smb_drv_data *drvdata, + struct cs_buffers *buf, unsigned long data_size) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + char **dst_pages = (char **)buf->data_pages; + unsigned long buf_offset = buf->offset; + unsigned int cur = buf->cur; + unsigned long to_copy; + + while (data_size) { + /* Copy parts of trace data when the read pointer will wrap around SMB buffer. */ + if (sdb->rd_offset + PAGE_SIZE - buf_offset > sdb->buf_size) + to_copy = sdb->buf_size - sdb->rd_offset; + else + to_copy = min(data_size, PAGE_SIZE - buf_offset); + + memcpy_fromio(dst_pages[cur] + buf_offset, sdb->buf_base + sdb->rd_offset, to_copy); + + buf_offset += to_copy; + if (buf_offset >= PAGE_SIZE) { + buf_offset = 0; + cur++; + cur %= buf->nr_pages; + } + data_size -= to_copy; + /* ensure memcpy finished before update the read pointer */ + sdb->rd_offset += to_copy; + sdb->rd_offset %= sdb->buf_size; + } + + sdb->data_size = 0; + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR); + smb_reset_buffer_status(drvdata); +} + +static unsigned long smb_update_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct cs_buffers *buf = sink_config; + unsigned long data_size = 0; + unsigned long flags; + bool lost = false; + + if (!buf) + return 0; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink. */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + + smb_update_data_size(drvdata); + data_size = sdb->data_size; + if (data_size > handle->size) { + sdb->rd_offset += data_size - handle->size; + sdb->rd_offset %= sdb->buf_size; + data_size = handle->size; + lost = true; + } + + smb_sync_perf_buffer(drvdata, buf, data_size); + if (!buf->snapshot && lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); + +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return data_size; +} + +static const struct coresight_ops_sink smb_cs_ops = { + .enable = smb_enable, + .disable = smb_disable, + .alloc_buffer = smb_alloc_buffer, + .free_buffer = smb_free_buffer, + .update_buffer = smb_update_buffer, +}; + +static const struct coresight_ops cs_ops = { + .sink_ops = &smb_cs_ops, +}; + +static int smb_init_data_buffer(struct platform_device *pdev, struct smb_data_buffer *sdb) +{ + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "SMB device failed to get resource.\n"); + return -EINVAL; + } + + sdb->start_addr = res->start & SMB_BASE_LOW_MASK; + sdb->buf_size = resource_size(res); + if (sdb->buf_size == 0) + return -EINVAL; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + sdb->buf_base = base; + + return 0; +} + +static void smb_init_hw(struct smb_drv_data *drvdata) +{ + u32 value; + + /* First disable smb and clear the status of SMB buffer */ + smb_reset_buffer_status(drvdata); + smb_disable_hw(drvdata); + smb_purge_data(drvdata); + + /* Using smb in single-end mode, and set other configures default */ + value = SMB_BUF_CFG_STREAMING | SMB_BUF_SINGLE_END | SMB_BUF_EN; + writel(value, drvdata->base + SMB_LB_CFG_LO); + value = SMB_MSG_FILTER(0x0, 0xff); + writel(value, drvdata->base + SMB_LB_CFG_HI); + + writel(SMB_GLOBAL_CFG, drvdata->base + SMB_CFG_REG); + writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLOBAL_INT); + writel(SMB_BUF_INT_CFG, drvdata->base + SMB_LB_INT_CTRL); +} + +static int smb_register_sink(struct platform_device *pdev, struct smb_drv_data *drvdata) +{ + struct coresight_platform_data *pdata = NULL; + struct coresight_desc desc = { 0 }; + int ret; + + pdata = coresight_get_platform_data(&pdev->dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + desc.type = CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + desc.ops = &cs_ops; + desc.pdata = pdata; + desc.dev = &pdev->dev; + desc.groups = smb_sink_groups; + desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev); + if (!desc.name) { + dev_err(&pdev->dev, "Failed to alloc coresight device name."); + return -ENOMEM; + } + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &smb_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) { + coresight_unregister(drvdata->csdev); + dev_err(&pdev->dev, "Failed to register misc, ret=%d.\n", ret); + } + + return ret; +} + +static void smb_unregister_sink(struct smb_drv_data *drvdata) +{ + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); +} + +/* + * Send ultrasoc messge to control hardwares on the tracing path, + * using DSM calls to avoid exposing ultrasoc message format. + */ +static int smb_config_inport(struct device *dev, bool enable) +{ + u32 flag = enable ? 1 : 0; + union acpi_object *obj; + guid_t guid; + + if (guid_parse("82ae1283-7f6a-4cbe-aa06-53e8fb24db18", &guid)) { + dev_err(dev, "Get GUID failed.\n"); + return -EINVAL; + } + + obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, flag, NULL); + if (!obj) + dev_err(dev, "ACPI handle failed!\n"); + else + ACPI_FREE(obj); + + return 0; +} + +static int smb_probe(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata; + int ret; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) { + dev_err(&pdev->dev, "Failed to ioremap resource.\n"); + return PTR_ERR(drvdata->base); + } + + ret = smb_init_data_buffer(pdev, &drvdata->sdb); + if (ret) { + dev_err(&pdev->dev, "Failed to init buffer, ret = %d.\n", ret); + return ret; + } + + smb_init_hw(drvdata); + spin_lock_init(&drvdata->spinlock); + drvdata->pid = -1; + + ret = smb_register_sink(pdev, drvdata); + if (ret) { + dev_err(&pdev->dev, "Failed to register smb sink.\n"); + return ret; + } + + ret = smb_config_inport(&pdev->dev, true); + if (ret) { + smb_unregister_sink(drvdata); + return ret; + } + + platform_set_drvdata(pdev, drvdata); + return 0; +} + +static int smb_remove(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata = platform_get_drvdata(pdev); + int ret; + + ret = smb_config_inport(&pdev->dev, false); + if (ret) + return ret; + + smb_unregister_sink(drvdata); + return 0; +} + +static const struct acpi_device_id ultrasoc_smb_acpi_match[] = { + {"HISI03A1", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match); + +static struct platform_driver smb_driver = { + .driver = { + .name = "ultrasoc,smb", + .acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match), + .suppress_bind_attrs = true, + }, + .probe = smb_probe, + .remove = smb_remove, +}; +module_platform_driver(smb_driver); + +MODULE_DESCRIPTION("Ultrasoc smb driver"); +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Jonathan Zhou <jonathan.zhouwen(a)huawei.com>"); +MODULE_AUTHOR("Qi Liu <liuqi115(a)huawei.com>"); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h new file mode 100644 index 000000000000..0b725db88f84 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2021 HiSilicon Limited. + * + * Code herein communicates with and accesses proprietary hardware which is + * licensed intellectual property (IP) belonging to Siemens Digital Industries + * Software Ltd. + * + * Siemens Digital Industries Software Ltd. asserts and reserves all rights to + * their intellectual property. This paragraph may not be removed or modified + * in any way without permission from Siemens Digital Industries Software Ltd. + */ + +#ifndef _ULTRASOC_SMB_H +#define _ULTRASOC_SMB_H + +#include <linux/coresight.h> +#include <linux/list.h> +#include <linux/miscdevice.h> + +#include "coresight-etm-perf.h" +#include "coresight-priv.h" + +/* Offset of SMB logical buffer registers */ +#define SMB_CFG_REG 0X0 +#define SMB_GLOBAL_EN 0X4 +#define SMB_GLOBAL_INT 0X8 +#define SMB_LB_CFG_LO 0X40 +#define SMB_LB_CFG_HI 0X44 +#define SMB_LB_INT_CTRL 0X48 +#define SMB_LB_INT_STS 0X4C +#define SMB_LB_LIMIT 0X58 +#define SMB_LB_RD_ADDR 0X5C +#define SMB_LB_WR_ADDR 0X60 +#define SMB_LB_PURGE 0X64 + +/* Set SMB_CFG_REG register */ +#define SMB_IDLE_PRD(period) (((period - 216) & 0xf) << 12) +#define SMB_MEM_WR(credit, rate) (((credit) << 16) | ((rate) << 18)) +#define SMB_MEM_RD(credit, rate) (((credit) << 22) | ((rate) << 24)) +#define SMB_BURST_LEN(len) ((len - 1) << 4) +#define SMB_GLOBAL_CFG (SMB_IDLE_PRD(231) | SMB_MEM_WR(0x3, 0x0) | \ + SMB_MEM_RD(0x3, 0x6) | SMB_BURST_LEN(16)) + +/* Set SMB_GLOBAL_INT register */ +#define SMB_INT_EN BIT(0) +#define SMB_INT_TYPE_PULSE BIT(1) +#define SMB_INT_POLARITY_HIGH BIT(2) +#define SMB_GLB_INT_CFG (SMB_INT_EN | SMB_INT_TYPE_PULSE | SMB_INT_POLARITY_HIGH) + +/* Set SMB_LB_CFG_LO register */ +#define SMB_BUF_EN BIT(0) +#define SMB_BUF_SINGLE_END BIT(1) +#define SMB_BUF_INIT BIT(8) +#define SMB_BUF_CONTINUOUS BIT(11) +#define SMB_FLOW_MASK GENMASK(19, 16) +#define SMB_BUF_CFG_STREAMING (SMB_BUF_INIT | SMB_BUF_CONTINUOUS | SMB_FLOW_MASK) +#define SMB_BASE_LOW_MASK GENMASK(31, 0) + +/* Set SMB_LB_CFG_HI register */ +#define SMB_MSG_FILTER(lower, upper) ((lower & 0xff) | ((upper & 0xff) << 8)) +#define SMB_BUF_INT_EN BIT(0) +#define SMB_BUF_NOTE_MASK GENMASK(11, 8) +#define SMB_BUF_INT_CFG (SMB_BUF_INT_EN | SMB_BUF_NOTE_MASK) + +/** + * struct smb_data_buffer - Details of the buffer used by SMB + * @buf_base : Memory mapped base address of SMB. + * @start_addr : SMB buffer start Physical address. + * @buf_size : Size of the buffer. + * @data_size : Size of Trace data copy to userspace. + * @rd_offset : Offset of the read pointer in the buffer. + */ +struct smb_data_buffer { + void __iomem *buf_base; + u32 start_addr; + unsigned long buf_size; + unsigned long data_size; + unsigned long rd_offset; +}; + +/** + * struct smb_drv_data - specifics associated to an SMB component + * @base: Memory mapped base address for SMB component. + * @csdev: Component vitals needed by the framework. + * @sdb: Data buffer for SMB. + * @miscdev: Specifics to handle "/dev/xyz.tmc" entry. + * @spinlock: Only one at a time pls. + * @reading: Synchronise user space access to SMB buffer. + * @pid: Process ID of the process being monitored by the session + * that is using this component. + * @mode: how this SMB is being used, perf mode or sysfs mode. + */ +struct smb_drv_data { + void __iomem *base; + struct coresight_device *csdev; + struct smb_data_buffer sdb; + struct miscdevice miscdev; + spinlock_t spinlock; + local_t reading; + pid_t pid; + u32 mode; +}; + +#define smb_simple_func(type, name, offset) \ +static ssize_t name##_show(struct device *_dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + type *drvdata = dev_get_drvdata(_dev->parent); \ + u32 val = readl(drvdata->base + offset); \ + \ + return sysfs_emit(buf, "0x%x\n", val); \ +} \ +static DEVICE_ATTR_RO(name) + +#endif -- 2.33.0

3 years, 6 months

Re: [RFC V2 PATCH] coresight: change tmc from misc device to cdev device

by Leo Yan

Hi Jay, On Mon, Dec 20, 2021 at 10:32:21AM +0800, Jiankang Chen wrote: [...] > > > +module_init(tmc_init); > > Should invoke tmc_init() in an ealier phase so it can prepare device class > > prior to the TMC devices registration? In other words, I think here > > should be: > > > > subsys_initcall(tmc_init); > > > Your suggestion is very good. I will revise it according to your suggestion; As I clarified for Mathieu's concerning in another reply, please ignore this comment. Thanks, Leo

3 years, 6 months

Re: [RFC V2 PATCH] coresight: change tmc from misc device to cdev device

by Leo Yan

Hi Jay, On Fri, Dec 17, 2021 at 11:42:08AM +0800, Jay Chen wrote: > From: root <root(a)localhost.localdomain> Please use your company's email address rather than using an invalid email address. > For coresight in the server scenario, if there are too many > funnel (about 130) and tmc (about 130) peripherals, the error > of insufficient device numbers will occur by misc device Incomplete commit log ... For a better practice, it's deserve to write a high quality commit log which is helpful for maintainers to understand your patch, at the end, it also can accelerate your patch's merging. Let me quote a suggestion for the commit log format from an old reply [1]: ... Please use the customary changelog style we use in the kernel: " Current code does (A), this has a problem when (B). We can improve this doing (C), because (D)." [1] https://lkml.org/lkml/2013/11/11/146 > Signed-off-by: root <root(a)localhost.localdomain> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 84 +++++++++++++++---- > drivers/hwtracing/coresight/coresight-tmc.h | 10 ++- > 2 files changed, 75 insertions(+), 19 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index d0276af82494..03b114c0616a 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,6 +31,11 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > +static dev_t tmc_major; > +static struct class *tmc_class; > + > +#define TMC_DEV_MAX (MINORMASK + 1) > + > void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > struct coresight_device *csdev = drvdata->csdev; > @@ -147,7 +152,7 @@ static int tmc_open(struct inode *inode, struct file *file) > { > int ret; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > > ret = tmc_read_prepare(drvdata); > if (ret) > @@ -179,7 +184,7 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len, > char *bufp; > ssize_t actual; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); > if (actual <= 0) > return 0; > @@ -200,7 +205,7 @@ static int tmc_release(struct inode *inode, struct file *file) > { > int ret; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > > ret = tmc_read_unprepare(drvdata); > if (ret) > @@ -449,8 +454,9 @@ static u32 tmc_etr_get_max_burst_size(struct device *dev) > > static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > { > - int ret = 0; > + int ret = 0, tmc_num = 0; > u32 devid; > + dev_t devt; > void __iomem *base; > struct device *dev = &adev->dev; > struct coresight_platform_data *pdata = NULL; > @@ -546,14 +552,26 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > goto out; > } > > - drvdata->miscdev.name = desc.name; > - drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; > - drvdata->miscdev.fops = &tmc_fops; > - ret = misc_register(&drvdata->miscdev); > - if (ret) > + tmc_num = etb_devs.nr_idx + etf_devs.nr_idx + > + etr_devs.nr_idx; I am struggling to understand this line code, but looks to me this is right. The system might have both ETR and ETF components, so we need to calculate index for all sinks. > + > + cdev_init(&drvdata->cdev.cdev, &tmc_fops); > + drvdata->cdev.cdev.owner = THIS_MODULE; > + devt = MKDEV(MAJOR(tmc_major), tmc_num - 1); > + ret = cdev_add(&drvdata->cdev.cdev, devt, 1); > + if (ret) { > coresight_unregister(drvdata->csdev); > - else > + goto out; > + } > + > + drvdata->cdev.dev = device_create(tmc_class, NULL, devt, &drvdata->cdev, desc.name); > + if (IS_ERR(drvdata->cdev.dev)) { > + ret = PTR_ERR(drvdata->cdev.dev); > + cdev_del(&drvdata->cdev.cdev); > + coresight_unregister(drvdata->csdev); > + } else > pm_runtime_put(&adev->dev); > + > out: > return ret; > } > @@ -584,12 +602,8 @@ static void tmc_remove(struct amba_device *adev) > { > struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev); > > - /* > - * Since misc_open() holds a refcount on the f_ops, which is > - * etb fops in this case, device is there until last file > - * handler to this device is closed. > - */ > - misc_deregister(&drvdata->miscdev); > + device_destroy(tmc_class, drvdata->cdev.dev->devt); > + cdev_del(&drvdata->cdev.cdev); > coresight_unregister(drvdata->csdev); > } > > @@ -618,7 +632,43 @@ static struct amba_driver tmc_driver = { > .id_table = tmc_ids, > }; > > -module_amba_driver(tmc_driver); > +static int __init tmc_init(void) > +{ > + int ret; > + > + ret = alloc_chrdev_region(&tmc_major, 0, TMC_DEV_MAX, "tmc"); > + if (ret < 0) { > + pr_err("tmc: failed to allocate char dev region\n"); > + return ret; > + } > + > + tmc_class = class_create(THIS_MODULE, "tmc"); > + if (IS_ERR(tmc_class)) { > + pr_err("failed to create tmc class\n"); > + ret = PTR_ERR(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > + return ret; > + } > + > + ret = amba_driver_register(&tmc_driver); > + if (ret) { > + pr_err("tmc: error registering amba driver\n"); > + class_destroy(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > + } > + > + return ret; > +} > + > +static void __exit tmc_exit(void) > +{ > + amba_driver_unregister(&tmc_driver); > + class_destroy(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > +} > + > +module_init(tmc_init); Should invoke tmc_init() in an ealier phase so it can prepare device class prior to the TMC devices registration? In other words, I think here should be: subsys_initcall(tmc_init); Thanks, Leo > +module_exit(tmc_exit); > > MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 6bec20a392b3..b65ac363f9e4 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -7,6 +7,7 @@ > #ifndef _CORESIGHT_TMC_H > #define _CORESIGHT_TMC_H > > +#include <linux/cdev.h> > #include <linux/dma-mapping.h> > #include <linux/idr.h> > #include <linux/miscdevice.h> > @@ -163,11 +164,16 @@ struct etr_buf { > void *private; > }; > > +struct tmc_cdev { > + struct cdev cdev; > + struct device *dev; > +}; > + > /** > * struct tmc_drvdata - specifics associated to an TMC component > * @base: memory mapped base address for this component. > * @csdev: component vitals needed by the framework. > - * @miscdev: specifics to handle "/dev/xyz.tmc" entry. > + * @tmc_cdev: specifics to handle "/dev/xyz.tmc" entry. > * @spinlock: only one at a time pls. > * @pid: Process ID of the process being monitored by the session > * that is using this component. > @@ -191,7 +197,7 @@ struct etr_buf { > struct tmc_drvdata { > void __iomem *base; > struct coresight_device *csdev; > - struct miscdevice miscdev; > + struct tmc_cdev cdev; > spinlock_t spinlock; > pid_t pid; > bool reading; > -- > 2.27.0 >

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