CoreSight

coresight@lists.linaro.org

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2382 discussions

by giftcn

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4 years

Re: ThunderX2 and Coresight bring up

by Zhenghao Hu

Hi, We are a group of researchers from NYU trying to bring up Coresight ETM interfaces on ThunderX2. So we dug out this old thread ( https://lists.linaro.org/pipermail/coresight/2018-August/001626.html) and trying to get things spinning. We are current on Linux 5.12.9 kernel, but it seems some of the DTS entries are missing from the upstream. Just to be sure, would it be possible that you could share the DTS scripts? Thank you! Zhenghao

4 years

from Altan Ibrahim

by globalfundings

4 years

[PATCH v6 0/1] perf cs-etm: Split Coresight decode by aux records

by James Clark

Changes since v5: * Fixed typo in commit message * Indentation fix James Clark (1): perf cs-etm: Split Coresight decode by aux records tools/perf/util/cs-etm.c | 156 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 1 deletion(-) -- 2.28.0

4 years

[PATCH v5 0/1] perf cs-etm: Split Coresight decode by aux records

by James Clark

Changes since RFC v4: * Style and indentation fixes * Add a warning when the buffer isn't found (suggested by Leo) * Undo change to set 'etm->data_queued' * Replace 'matchesCpuPid' with early exit when CPU/TID doesn't match * Check more return value errors * Remove TODOs from commit message and code * Add motivation to commit message James Clark (1): perf cs-etm: Split Coresight decode by aux records tools/perf/util/cs-etm.c | 158 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 1 deletion(-) -- 2.28.0

4 years

ACCOUNT WARNING: Undelivered mails coresight@lists.linaro.org Kindly rectify

by Noreply＠lists.linaro.org

4 years

[PATCHv2 0/4] perf/core: Add support to exclude kernel mode PMU tracing

by Sai Prakash Ranjan

Hardware assisted tracing families such as ARM Coresight, Intel PT provides rich tracing capabilities including instruction level tracing and accurate timestamps which are very useful for profiling and also pose a significant security risk. One such example of security risk is when kernel mode tracing is not excluded and these hardware assisted tracing can be used to analyze cryptographic code execution. In this case, even the root user must not be able to infer anything. To explain it more clearly in the words of a security team member (credits: Mattias Nissler), "Consider a system where disk contents are encrypted and the encryption key is set up by the user when mounting the file system. From that point on the encryption key resides in the kernel. It seems reasonable to expect that the disk encryption key be protected from exfiltration even if the system later suffers a root compromise (or even against insiders that have root access), at least as long as the attacker doesn't manage to compromise the kernel." Here the idea is to protect such important information from all users including root users since root privileges does not have to mean full control over the kernel [1] and root compromise does not have to be the end of the world. But "Peter said even the regular counters can be used for full branch trace, the information isn't as accurate as PT and friends and not easier but is good enough to infer plenty". This would mean that a global tunable config for all kernel mode pmu tracing is more appropriate than the one targeting the hardware assisted instruction tracing. Currently we can exclude kernel mode tracing via perf_event_paranoid sysctl but it has following limitations, * No option to restrict kernel mode instruction tracing by the root user. * Not possible to restrict kernel mode instruction tracing when the hardware assisted tracing IPs like ARM Coresight ETMs use an additional interface via sysfs for tracing in addition to perf interface. So introduce a new config CONFIG_EXCLUDE_KERNEL_PMU_TRACE to exclude kernel mode pmu tracing for all users including root which will be generic and applicable to all hardware tracing families and which can also be used with other interfaces like sysfs in case of ETMs. Patch 1 adds this new config and the support in perf core to exclude all kernel mode PMU tracing. Patch 2 adds the perf evsel warning message when the perf tool users attempt to perform a kernel mode trace with the config enabled to exclude the kernel mode tracing. Patch 3 and Patch 4 adds the support for excluding kernel mode for ARM Coresight ETM{4,3}XX sysfs mode using the newly introduced generic config. [1] https://lwn.net/Articles/796866/ Changes in v2: * Move from kernel mode instruction tracing to all kernel level PMU tracing (Peter) * Move the check and warning to the caller mode_store() (Doug) Sai Prakash Ranjan (4): perf/core: Add support to exclude kernel mode PMU tracing perf evsel: Print warning for excluding kernel mode instruction tracing coresight: etm4x: Add support to exclude kernel mode tracing coresight: etm3x: Add support to exclude kernel mode tracing drivers/hwtracing/coresight/coresight-etm3x-core.c | 3 +++ drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 6 ++++++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++++++ init/Kconfig | 11 +++++++++++ kernel/events/core.c | 3 +++ tools/perf/util/evsel.c | 3 ++- 7 files changed, 36 insertions(+), 2 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

4 years

Important:: Action required lists.linaro.org

by Email ADMIN

4 years

[PATCH v2 0/8] perf: Refine barriers for AUX ring buffer

by Leo Yan

Based on the discussion [1], this patch series is to refine the memory barriers for AUX ring buffer. Patches 01 ~ 04 to address the barriers usage in the kernel. The first patch is to make clear comment for how to use the barriers between the data store and aux_head store, this asks the driver to make sure the data is visible. Patches 02 ~ 04 is to refine the drivers for barriers after the data store. Patches 05 ~ 07 is to fix and clean up the memory barries in perf tool for AUX ring buffer. Since the 64-bit value's atomicity is not promised on 32-bit perf, the last patch is to report error and let perf to directly exit for this case. Have testes the patches on Arm64 Juno platform. [1] https://lore.kernel.org/patchwork/patch/1431867/ Leo Yan (8): perf/ring_buffer: Add comment for barriers on AUX ring buffer coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering perf/x86: Add barrier after updating bts perf auxtrace: Change to use SMP memory barriers perf auxtrace: Drop legacy __sync functions perf auxtrace: Use WRITE_ONCE() for updating aux_tail perf record: Directly bail out for compat case arch/x86/events/intel/bts.c | 3 +++ .../hwtracing/coresight/coresight-tmc-etf.c | 6 +++++ .../hwtracing/coresight/coresight-tmc-etr.c | 8 ++++++ kernel/events/ring_buffer.c | 9 +++++++ tools/perf/builtin-record.c | 17 ++++++++++++ tools/perf/util/auxtrace.h | 27 +++---------------- 6 files changed, 47 insertions(+), 23 deletions(-) -- 2.25.1

4 years

From Nasser Rashid

by Nasser Rashid

4 years

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