CoreSight

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[GIT PULL v3] Coresight changes for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16.v3 for you to fetch changes up to 561ced0bb90a4be298b7db5fb54f29731d74a3f6: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-27 11:46:06 -0600) ---------------------------------------------------------------- Coresight changes for v5.16 - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

5 years

Re: [GIT PULL v2] Coresight changes for v5.16

by Mathieu Poirier

On Wed, 27 Oct 2021 at 11:41, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > On Wed, Oct 27, 2021 at 11:32:43AM -0600, Mathieu Poirier wrote: > > On Wed, 27 Oct 2021 at 00:50, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > > > > > On Tue, Oct 26, 2021 at 01:55:45PM -0600, Mathieu Poirier wrote: > > > > The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: > > > > > > > > Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) > > > > > > > > are available in the Git repository at: > > > > > > > > git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16 > > > > > > Better but I get the following errors when my scripts try to merge them. > > > Note, the linux-next scripts will give you the same complaint, so this > > > isn't a new thing: > > > > Can you point me to the linux-next script you are referring to above? > > Usually when that happens I get an email but this time I didn't get > > anything. > > Is this tree/branch in linux-next now? If so, you should have gotten an > email. Definitely: https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git/log/?h=… > > My scripts were sent to the workflow mailing list a year or so ago, I > can dig them up if needed. > Thanks - I'll look it up.

5 years

Re: [GIT PULL v2] Coresight changes for v5.16

by Mathieu Poirier

On Wed, 27 Oct 2021 at 00:50, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > On Tue, Oct 26, 2021 at 01:55:45PM -0600, Mathieu Poirier wrote: > > The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: > > > > Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) > > > > are available in the Git repository at: > > > > git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16 > > Better but I get the following errors when my scripts try to merge them. > Note, the linux-next scripts will give you the same complaint, so this > isn't a new thing: Can you point me to the linux-next script you are referring to above? Usually when that happens I get an email but this time I didn't get anything. > > Commit 6871138a7ab9 ("coresight: etm4x: Add ETM PID for Kryo-5XX") > committer Signed-off-by missing > author email: quic_taozha(a)quicinc.com > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 202d403ae3a9 ("coresight: Don't immediately close events that are run on invalid CPU/sink combos") > committer Signed-off-by missing > author email: james.clark(a)arm.com > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: James Clark <james.clark(a)arm.com> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit ef095e61dc8f ("coresight: Update comments for removing cs_etm_find_snapshot()") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 7be15eef996f ("coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 60067d5ab339 ("coresight: tmc-etf: Add comment for store ordering") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 7c202525ff8c ("coresight: tmc-etr: Add barrier after updating AUX ring buffer") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Errors in tree with Signed-off-by, please fix! > > > Is there some reason you are committing changes to your tree and not signing > off on them? That's not really a good idea :( > Not sure why sarcasm is required here - simply pointing out the problem would have been sufficient. These patches were committed by Suzuki who co-maintains the subsystem with me. The committer information likely got transferred when I cherry-picked the patches when putting the pull request together. > thanks, > > greg k-h

5 years

[GIT PULL v2] Coresight changes for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16 for you to fetch changes up to 7cf0754113f7ed6fad999483e40d95985c987353: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-25 12:06:02 -0600) ---------------------------------------------------------------- Coresight changes for v5.16 - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

5 years

[GIT PULL] Coresight subsystem for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/v5.16-next for you to fetch changes up to 7cf0754113f7ed6fad999483e40d95985c987353: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-25 12:06:02 -0600) ---------------------------------------------------------------- Hi Greg, Please consider these for the next merge window. Also let me know if there is any modifications I can do to this pull request to make things easier on your side. Thanks, Mathieu Included herein: - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

5 years

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Fri, Oct 22, 2021 at 09:14:38AM +0200, Greg KH wrote: > On Thu, Oct 21, 2021 at 05:47:31PM +0100, Will Deacon wrote: > > Hi Mathieu, > > > > [CC Greg] > > > > On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > > > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > > > Suzuki K Poulose (15): > > > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > > > arm64: errata: Add workaround for TSB flush failures > > > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > > > coresight: trbe: Allow driver to choose a different alignment > > > > > > coresight: trbe: Add infrastructure for Errata handling > > > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > > > coresight: trbe: Make sure we have enough space > > > > > > coresight: trbe: Work around write to out of range > > > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > > > address > > > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > > > arch/arm64/Kconfig | 111 ++++++ > > > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > > > arch/arm64/tools/cpucaps | 3 + > > > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > > > > > I have applied this set. > > > > > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > > > for the first four patches to be shared with arm64. Since you've gone > > > > ahead and applied the whole series, please can you provide me a stable > > > > branch with the first four patches only so that I can include them in > > > > the arm64 tree? > > > > > > > > Failing that, I can create a branch for you to pull and apply the remaining > > > > patches on top. > > > > > > > > Please let me know. > > > > > > Coresight patches flow through Greg's tree and as such the coresight-next tree > > > gets rebased anyway. I will remove the first 4 patches and push again. By the > > > way do you also want to pick up patches 14 and 16 since they are concerned with > > > "arch/arm64/Kconfig" or should I keep them? > > > > I'll take the first 4 and put them on a stable branch, which you can choose > > to pull if you like (but please don't rebase it or we'll end up with > > duplicate commits). The rest of the patches, including the later Kconfig > > changes, are yours but I doubt they'll apply cleanly without the initial > > changes. > > > > Are you sure Greg rebases everything? That sounds a bit weird to me, as it > > means it's impossible to share branches with other trees. How do you usually > > handle this situation? > > No, I never rebase my trees. For coresight patches I take them as > emailed patches due to previous history requiring me to review them all > myself. If this is an issue here, I can always take a pull request as > long as you all don't want my review :) Can you expand on the "previous history requiring" you to review coresight patches? Rebasing the coresight-next tree when patches are pulled in the char-misc tree causes problems when features involve other subsystems. I definitely appreciate reviews of coresight patches from anyone. The subsystem has grown to be very complex and more reviewers mean higher probabilities of catching problems. There has to be a way for that to continue while making it easier to collaborate with other subsystems. For this particular patchset, Will has picked up the first 4 patches, I will pick up patches 5 to 13 and patches 14 and 15 will have to go in the next cycle. I doubt this is the best we can do. Regards, Mathieu > > thanks, > > greg k-h

5 years

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Thu, 21 Oct 2021 at 10:47, Will Deacon <will(a)kernel.org> wrote: > > Hi Mathieu, > > [CC Greg] > > On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > > Suzuki K Poulose (15): > > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > > arm64: errata: Add workaround for TSB flush failures > > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > > coresight: trbe: Allow driver to choose a different alignment > > > > > coresight: trbe: Add infrastructure for Errata handling > > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > > coresight: trbe: Make sure we have enough space > > > > > coresight: trbe: Work around write to out of range > > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > > address > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > > arch/arm64/Kconfig | 111 ++++++ > > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > > arch/arm64/tools/cpucaps | 3 + > > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > > > I have applied this set. > > > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > > for the first four patches to be shared with arm64. Since you've gone > > > ahead and applied the whole series, please can you provide me a stable > > > branch with the first four patches only so that I can include them in > > > the arm64 tree? > > > > > > Failing that, I can create a branch for you to pull and apply the remaining > > > patches on top. > > > > > > Please let me know. > > > > Coresight patches flow through Greg's tree and as such the coresight-next tree > > gets rebased anyway. I will remove the first 4 patches and push again. By the > > way do you also want to pick up patches 14 and 16 since they are concerned with > > "arch/arm64/Kconfig" or should I keep them? > > I'll take the first 4 and put them on a stable branch, which you can choose > to pull if you like (but please don't rebase it or we'll end up with > duplicate commits). The rest of the patches, including the later Kconfig > changes, are yours but I doubt they'll apply cleanly without the initial > changes. Right - I just had another look at them and what I suggested above won't work. > > Are you sure Greg rebases everything? That sounds a bit weird to me, as it > means it's impossible to share branches with other trees. How do you usually > handle this situation? Greg applies the patches I send to him near the end of every cycle - see this one [1] as an example. Unfortunately that way of working makes it hard to deal with patchsets such as this one. To move forward you can either pick up this whole series (just add my RB to all the CS patches) or I start sending pull requests to Greg. Greg - what's your take on this? [1]. https://www.spinics.net/lists/arm-kernel/msg915961.html > > Will

5 years

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > Suzuki K Poulose (15): > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > arm64: errata: Add workaround for TSB flush failures > > > arm64: errata: Add detection for TRBE write to out-of-range > > > coresight: trbe: Add a helper to calculate the trace generated > > > coresight: trbe: Add a helper to pad a given buffer area > > > coresight: trbe: Decouple buffer base from the hardware base > > > coresight: trbe: Allow driver to choose a different alignment > > > coresight: trbe: Add infrastructure for Errata handling > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > coresight: trbe: Make sure we have enough space > > > coresight: trbe: Work around write to out of range > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > address > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > arch/arm64/Kconfig | 111 ++++++ > > > arch/arm64/include/asm/barrier.h | 16 +- > > > arch/arm64/include/asm/cputype.h | 4 + > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > I have applied this set. > > Mathieu -- the plan here (which we have discussed on the list [1]) is > for the first four patches to be shared with arm64. Since you've gone > ahead and applied the whole series, please can you provide me a stable > branch with the first four patches only so that I can include them in > the arm64 tree? > > Failing that, I can create a branch for you to pull and apply the remaining > patches on top. > > Please let me know. Coresight patches flow through Greg's tree and as such the coresight-next tree gets rebased anyway. I will remove the first 4 patches and push again. By the way do you also want to pick up patches 14 and 16 since they are concerned with "arch/arm64/Kconfig" or should I keep them? Thanks, Mathieu > > Thanks, > > Will > > [1] https://lore.kernel.org/all/20211008073229.GB32625@willie-the-truck/

5 years

[PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. The Kconfig items for the TRBE errata are initially dropped in with dependency on COMPILE_TEST. These are dropped only after the driver is equipped with the work around in later patches. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v6 Changes since v5: * https://lkml.kernel.org/r/20211014223125.2605031-1-suzuki.poulose@arm.com - Fix typo in the Kconfig symbol usage in errata listing (Will) - Fix typo in commit description for "arm64: errata: Add detection for TRBE overwrite in FILL mode" - Fix commit description checkpatch warnings on column length for: "arm64: errata: Add detection for TRBE write to out-of-range" - Collected Reviews/Acks from Mathieu/Anshuman/Will Changes since v4: * https://lkml.kernel.org/r/20211012131743.2040596-1-suzuki.poulose@arm.com - Fix WARN on trbe driver probe on a hotplugged CPU, by making sure that the arm_trbe_probe_cpu() is called from non-premptible context. this_cpu_has_cap() doesn't like to be called from a preemptible() context. - Fix Kconfig text issues pointed out by Randy Changes since v3: - Fix missing Kconfig selection for TSB flush failure erratum (Will) Merged the Kconfig changes to the core patch for TSB. - Use COMPILE_TEST dependency for the TRBE work arounds instead of delaying the Kconfig entries. Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (15): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 111 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- 7 files changed, 567 insertions(+), 37 deletions(-) -- 2.25.4

5 years

[PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. The Kconfig items for the TRBE errata are initially dropped in with dependency on COMPILE_TEST. These are dropped only after the driver is equipped with the work around in later patches. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v5 Changes since v4: - Fix WARN on trbe driver probe on a hotplugged CPU, by making sure that the arm_trbe_probe_cpu() is called from non-premptible context. this_cpu_has_cap() doesn't like to be called from a preemptible() context. - Fix Kconfig text issues pointed out by Randy Changes since v3: - Fix missing Kconfig selection for TSB flush failure erratum (Will) Merged the Kconfig changes to the core patch for TSB. - Use COMPILE_TEST dependency for the TRBE work arounds instead of delaying the Kconfig entries. Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (15): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 111 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 395 +++++++++++++++++-- 7 files changed, 567 insertions(+), 38 deletions(-) -- 2.25.4

5 years

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