CoreSight

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1977 discussions

[RFT v4 1/8] perf cs-etm: Fix start tracing packet handling

by Leo Yan

Usually the start tracing packet is a CS_ETM_TRACE_ON packet, this packet is passed to cs_etm__flush(); cs_etm__flush() will check the condition 'prev_packet->sample_type == CS_ETM_RANGE' but 'prev_packet' is allocated by zalloc() so 'prev_packet->sample_type' is zero in initialization and this condition is false. So cs_etm__flush() will directly bail out without handling the start tracing packet. This patch is to introduce a new sample type CS_ETM_EMPTY, which is used to indicate the packet is an empty packet. cs_etm__flush() will swap packets when it finds the previous packet is empty, so this can record the start tracing packet into 'etmq->prev_packet'. Another minor change in cs_etm__flush() is to check the condition 'etmq->prev_packet->sample_type == CS_ETM_TRACE_ON', if the previous packet is also a CS_ETM_TRACE_ON packet, the function will skip for contiguous CS_ETM_TRACE_ON packet. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 26 ++++++++++++++++++++++--- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index 743f5f4..612b575 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -23,6 +23,7 @@ struct cs_etm_buffer { }; enum cs_etm_sample_type { + CS_ETM_EMPTY = 0, CS_ETM_RANGE = 1 << 0, CS_ETM_TRACE_ON = 1 << 1, }; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 822ba91..67564c1 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -924,9 +924,18 @@ static int cs_etm__flush(struct cs_etm_queue *etmq) int err = 0; struct cs_etm_packet *tmp; - if (etmq->etm->synth_opts.last_branch && - etmq->prev_packet && - etmq->prev_packet->sample_type == CS_ETM_RANGE) { + if (!etmq->prev_packet) + return 0; + + /* Skip for contiguous CS_ETM_TRACE_ON packet */ + if (etmq->prev_packet->sample_type == CS_ETM_TRACE_ON) + return 0; + + /* Handle start tracing packet */ + if (etmq->prev_packet->sample_type == CS_ETM_EMPTY) + goto swap_packet; + + if (etmq->etm->synth_opts.last_branch) { /* * Generate a last branch event for the branches left in the * circular buffer at the end of the trace. @@ -941,6 +950,10 @@ static int cs_etm__flush(struct cs_etm_queue *etmq) etmq->period_instructions); etmq->period_instructions = 0; + } + +swap_packet: + if (etmq->etm->synth_opts.last_branch) { /* * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for * the next incoming packet. @@ -1020,6 +1033,13 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq) */ cs_etm__flush(etmq); break; + case CS_ETM_EMPTY: + /* + * Should not receive empty packet, + * report error. + */ + pr_err("CS ETM Trace: empty packet\n"); + return -EINVAL; default: break; } -- 2.7.4

6 years, 1 month

[RFT v4 0/6] Perf script: Add python script for CoreSight trace disassembler

by Leo Yan

This patch series is to support for using 'perf script' for CoreSight trace disassembler, for this purpose this patch series adds a new python script to parse CoreSight tracing event and use command 'objdump' for disassembled lines, finally this can generate readable program execution flow for reviewing tracing data. Patches 0001 ~ 0003 are to generate samples for the start packet, CS_ETM_TRACE_ON packet and exception packets. Patch 0004 is to introduce invalid address macro. Patch 0005 is to add python script for trace disassembler. Patch 0006 is to add doc to explain python script usage and give example for it. This patch series has been rebased on acme git tree [1] with the latest commit e9175538c04f ("perf script python: Add addr into perf sample dict") and tested on Hikey (ARM64 octa CA53 cores). In this version the script has no dependency on ARM64 platform and is expected to support ARM32 platform, but I am lacking ARM32 platform for testing on it, so firstly upstream to support ARM64 platform. This patch series is firstly to support 'per-thread' recording tracing data, and it has been verified for kernel panic kdump tracing data. Please note, this patch series (v4) is ONLY used for discussion for packet handling, after we get solid result I will send to LKML for reviewing and merging into mainline kernel. Changes from v3: * Split packet handling for three patches, one is for start tracing packet, one is for CS_ETM_TRACE_ON packet and the last one patch is for exception packet; * Introduce invalid address macro. Changes from v2: * Synced with Rob for handling CS_ETM_TRACE_ON packet, so refined 0001 patch according to dicussion; * Minor cleanup and fixes in 0003 patch for python script: remove 'svc' checking. Changes from v1: * According to Mike and Rob suggestion, add the fixing to generate samples for the start packet and exception packets. * Simplify the python script to remove the exception prediction algorithm, we can rely on the sane exception packets for disassembler. Leo Yan (6): perf cs-etm: Fix start tracing packet handling perf cs-etm: Generate branch sample for CS_ETM_TRACE_ON packet perf cs-etm: Generate branch sample for exception packet perf cs-etm: Introduce invalid address macro perf script python: Add script for CoreSight trace disassembler coresight: Document for CoreSight trace disassembler Documentation/trace/coresight.txt | 52 +++++ tools/perf/scripts/python/arm-cs-trace-disasm.py | 235 +++++++++++++++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 19 +- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 11 +- tools/perf/util/cs-etm.c | 101 ++++++++-- 5 files changed, 390 insertions(+), 28 deletions(-) create mode 100644 tools/perf/scripts/python/arm-cs-trace-disasm.py -- 2.7.4

6 years, 1 month

[PATCH v2 00/12] coresight: tmc-etr Transparent buffer management

by Suzuki K Poulose

This series is split of the Coresight ETR perf support patches posted here [0]. The CATU support and perf backend support will be posted as separate series for better management and review of the patches. This series adds the support for TMC ETR Scatter-Gather mode to allow using physical non-contiguous buffer for holding the trace data. It also adds a layer to handle the buffer management in a transparent manner, independent of the underlying mode used by the TMC ETR. The layer chooses the ETR mode based on different parameters (size, re-using a set of pages, presence of an SMMU etc.). Finally we add a sysfs parameter to tune the buffer size for ETR in sysfs-mode. During the testing, we found out that if the TMC ETR is not properly connected to the memory subsystem, the ETR could lock-up the system while waiting for the "read" transactions to complete in scatter-gather mode. So, we do not use the mode on a system unless it is safe to do so. This is specified by a DT property "arm,scatter-gather". Applies on coreisght-next tree from Mathieu Changes since previous version [1]: - Rebased to Mathieu's coresight-next tree to resolve a conflict. - Added tags for DT changes from Rob and Mathieu - Split the SG mode backend support patch from the ETR-BUF patch. - Address other comments from Mathieu Changes since splitted series [0] : - Split the series in [0] - Address comments on v2 - Rename DT property "scatter-gather" to "arm,scatter-gather" - Add ETM PID for Cortex-A35, use macros to make the listing easier [0] - http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/574875.html [1] - http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/579135.html Suzuki K Poulose (12): coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35 coresight: tmc: Hide trace buffer handling for file read coresight: tmc-etr: Do not clean trace buffer coresight: tmc-etr: Disallow perf mode coresight: Add helper for inserting synchronization packets dts: bindings: Restrict coresight tmc-etr scatter-gather mode dts: juno: Add scatter-gather support for all revisions coresight: Add generic TMC sg table framework coresight: Add support for TMC ETR SG unit coresight: tmc-etr: Add transparent buffer management coresight: tmc-etr buf: Add TMC scatter gather mode backend coresight: tmc: Add configuration support for trace buffer size .../ABI/testing/sysfs-bus-coresight-devices-tmc | 8 + .../devicetree/bindings/arm/coresight.txt | 5 +- arch/arm64/boot/dts/arm/juno-base.dtsi | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 12 +- drivers/hwtracing/coresight/coresight-etm4x.c | 31 +- drivers/hwtracing/coresight/coresight-priv.h | 10 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 45 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 1010 ++++++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc.c | 83 +- drivers/hwtracing/coresight/coresight-tmc.h | 110 ++- drivers/hwtracing/coresight/coresight.c | 3 +- 11 files changed, 1144 insertions(+), 174 deletions(-) -- 2.7.4

6 years, 1 month

[PATCH 6/7] perf script python: Add addr into perf sample dict

by Arnaldo Carvalho de Melo

From: Leo Yan <leo.yan(a)linaro.org> ARM CoreSight auxtrace uses 'sample->addr' to record the target address for branch instructions, so the data of 'sample->addr' is required for tracing data analysis. This commit collects data of 'sample->addr' into perf sample dict, finally can be used for python script for parsing event. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Jonathan Corbet <corbet(a)lwn.net> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Robert Walker <robert.walker(a)arm.com> Cc: Tor Jeremiassen <tor(a)ti.com> Cc: coresight(a)lists.linaro.org Cc: kim.phillips(a)arm.co Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-doc(a)vger.kernel.org Link: http://lkml.kernel.org/r/1527497103-3593-3-git-send-email-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> --- tools/perf/util/scripting-engines/trace-event-python.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index 10dd5fce082b..7f8afacd08ee 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -531,6 +531,8 @@ static PyObject *get_perf_sample_dict(struct perf_sample *sample, PyLong_FromUnsignedLongLong(sample->period)); pydict_set_item_string_decref(dict_sample, "phys_addr", PyLong_FromUnsignedLongLong(sample->phys_addr)); + pydict_set_item_string_decref(dict_sample, "addr", + PyLong_FromUnsignedLongLong(sample->addr)); set_sample_read_in_dict(dict_sample, sample, evsel); pydict_set_item_string_decref(dict, "sample", dict_sample); -- 2.14.3

6 years, 1 month

[RFT v3 0/4] Perf script: Add python script for CoreSight trace disassembler

by Leo Yan

This patch series is to support for using 'perf script' for CoreSight trace disassembler, for this purpose this patch series adds a new python script to parse CoreSight tracing event and use command 'objdump' for disassembled lines, finally this can generate readable program execution flow for reviewing tracing data. Patch 0001 is one fixing patch to generate samples for the start packet and exception packets. Patch 0002 is the prerequisite to add addr into sample dict, so this value can be used by python script to analyze instruction range. Patch 0003 is to add python script for trace disassembler. Patch 0004 is to add doc to explain python script usage and give example for it. This patch series has been rebased on acme git tree [1] with the commit 19422a9f2a3b ("perf tools: Fix kernel_start for PTI on x86") and tested on Hikey (ARM64 octa CA53 cores). In this version the script has no dependency on ARM64 platform and is expected to support ARM32 platform, but I am lacking ARM32 platform for testing on it, so firstly upstream to support ARM64 platform. This patch series is firstly to support 'per-thread' recording tracing data, but we also need to verify the script can dump trace disassembler CPU wide tracing and kernel panic kdump tracing data. I also verified this patch series which can work with kernel panic kdump tracing data, because Mathieu is working on CPU wide tracing related work, so after this we need to retest for CPU wide tracing and kdump tracing to ensure the python script can handle well for all cases. You are very welcome to test the script in this patch series, your testing result and suggestion are very valuable to perfect this script to cover more cases. Changes from v2: * Synced with Rob for handling CS_ETM_TRACE_ON packet, so refined 0001 patch according to dicussion; * Minor cleanup and fixes in 0003 patch for python script: remove 'svc' checking. Changes from v1: * According to Mike and Rob suggestion, add the fixing to generate samples for the start packet and exception packets. * Simplify the python script to remove the exception prediction algorithm, we can rely on the sane exception packets for disassembler. Leo Yan (4): perf cs-etm: Generate branch sample for missed packets perf script python: Add addr into perf sample dict perf script python: Add script for CoreSight trace disassembler coresight: Document for CoreSight trace disassembler Documentation/trace/coresight.txt | 52 +++++ tools/perf/scripts/python/arm-cs-trace-disasm.py | 235 +++++++++++++++++++++ tools/perf/util/cs-etm.c | 93 ++++++-- .../util/scripting-engines/trace-event-python.c | 2 + 4 files changed, 362 insertions(+), 20 deletions(-) create mode 100644 tools/perf/scripts/python/arm-cs-trace-disasm.py -- 2.7.4

6 years, 1 month

[PATCH 00/11] coresight: tmc-etr Transparent buffer management

by Suzuki K Poulose

This series is split of the Coresight ETR perf support patches posted here [0]. The CATU support and perf backend support will be posted as separate series for better management and review of the patches. This series adds the support for TMC ETR Scatter-Gather mode to allow using physical non-contiguous buffer for holding the trace data. It also adds a layer to handle the buffer management in a transparent manner, independent of the underlying mode used by the TMC ETR. The layer chooses the ETR mode based on different parameters (size, re-using a set of pages, presence of an SMMU etc.). Finally we add a sysfs parameter to tune the buffer size for ETR in sysfs-mode. During the testing, we found out that if the TMC ETR is not properly connected to the memory subsystem, the ETR could lock-up the system while waiting for the "read" transactions to complete in scatter-gather mode. So, we do not use the mode on a system unless it is safe to do so. This is specified by a DT property "arm,scatter-gather". Applies on v4.17-rc4 Changes since v2 in [0] : - Split the series in [0] - Address comments on v2 - Rename DT property "scatter-gather" to "arm,scatter-gather" - Add ETM PID for Cortex-A35, use macros to make the listing easier [0] - http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/574875.html Suzuki K Poulose (11): coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35 coresight: tmc: Hide trace buffer handling for file read coresight: tmc-etr: Do not clean trace buffer coresight: tmc-etr: Disallow perf mode coresight: Add helper for inserting synchronization packets dts: bindings: Restrict coresight tmc-etr scatter-gather mode dts: juno: Add scatter-gather support for all revisions coresight: Add generic TMC sg table framework coresight: Add support for TMC ETR SG unit coresight: tmc-etr: Add transparent buffer management coresight: tmc: Add configuration support for trace buffer size .../ABI/testing/sysfs-bus-coresight-devices-tmc | 8 + .../devicetree/bindings/arm/coresight.txt | 5 +- arch/arm64/boot/dts/arm/juno-base.dtsi | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 12 +- drivers/hwtracing/coresight/coresight-etm4x.c | 32 +- drivers/hwtracing/coresight/coresight-priv.h | 10 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 45 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 1032 ++++++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc.c | 83 +- drivers/hwtracing/coresight/coresight-tmc.h | 111 ++- drivers/hwtracing/coresight/coresight.c | 3 +- 11 files changed, 1169 insertions(+), 173 deletions(-) -- 2.7.4

6 years, 1 month

[RFT v2 0/4] Perf script: Add python script for CoreSight trace disassembler

by Leo Yan

This patch series is to support for using 'perf script' for CoreSight trace disassembler, for this purpose this patch series adds a new python script to parse CoreSight tracing event and use command 'objdump' for disassembled lines, finally this can generate readable program execution flow for reviewing tracing data. Patch 0001 is one fixing patch to generate samples for the start packet and exception packets. Patch 0002 is the prerequisite to add addr into sample dict, so this value can be used by python script to analyze instruction range. Patch 0003 is to add python script for trace disassembler. Patch 0004 is to add doc to explain python script usage and give example for it. This patch series has been rebased on acme git tree [1] with the last commit 19422a9f2a3b ("perf tools: Fix kernel_start for PTI on x86") and tested on Hikey (ARM64 octa CA53 cores). In this version the script has no dependency on ARM64 platform and is expected to support ARM32 platform, but I am lacking ARM32 platform for testing on it, so firstly upstream to support ARM64 platform. This patch series is firstly to support 'per-thread' recording tracing data, but we also need to verify the script can dump trace disassembler CPU wide tracing and kernel panic kdump tracing data. I also verified this patch series which can work with kernel panic kdump tracing data, because Mathieu is working on CPU wide tracing related work, so after this we need to retest for CPU wide tracing and kdump tracing to ensure the python script can handle well for all cases. You are very welcome to test the script in this patch series, your testing result and suggestion are very valuable to perfect this script to cover more cases. Changes from v1: * According to Mike and Rob suggestion, add the fixing to generate samples for the start packet and exception packets. * Simplify the python script to remove the exception prediction algorithm, we can rely on the sane exception packets for disassembler. [1] https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git Leo Yan (4): perf cs-etm: Generate sample for missed packets perf script python: Add addr into perf sample dict perf script python: Add script for CoreSight trace disassembler coresight: Document for CoreSight trace disassembler Documentation/trace/coresight.txt | 52 +++++ tools/perf/scripts/python/arm-cs-trace-disasm.py | 234 +++++++++++++++++++++ tools/perf/util/cs-etm.c | 35 ++- .../util/scripting-engines/trace-event-python.c | 2 + 4 files changed, 316 insertions(+), 7 deletions(-) create mode 100644 tools/perf/scripts/python/arm-cs-trace-disasm.py -- 2.7.4

6 years, 1 month

Displaying processor type in kernel boot logs

by Mathieu Poirier

Good morning Al, Suzuki sent me this patch [1] that has the effect of printing the following [2] in the kernel boot log at initialisation time. I think it is quite useful since one can correlate CPU information and ETM engine without having to go back to the DT or having to look at all the tracers in sysFS. On the flip side I'm a little weary (since peripheral numbers are implementation specific) that at one point we may end up with say, a Cortex-A53 with different peripheral IDs or another CPU type advertising a peripheral ID that is already taken. As I said I think this is a good idea but before applying a change that will be very public I'd like to make sure there aren't any ramification we haven't thought about. Please let me know what you think. Best regards, Mathieu [1]. https://www.spinics.net/lists/arm-kernel/msg653904.html [2]. https://pastebin.com/gbiLaJHJ

6 years, 1 month

[RFT 0/3] Perf script: Add python script for CoreSight trace disassembler

by Leo Yan

6 years, 1 month

Re: Re: Re: OpenCSD on Juno

by marekzmyslowski

Hello Mathieu, Thank for the config file. It works. I was able to build the OpenCSD kernel (form the perf-opencsd-master branch) and install on the USB (I used the ArchLinuxARM-aarch64-latest.tar.gz). I also built the perf tool (make -C tools/perf). Everything is booting but the perf has some issues: [root@alarm home]# ./perf record -vvv -e cs_etm/(a)20070000.etr/u --per-thread uname map_groups__set_modules_path_dir: cannot open /lib/modules/4.13.0-rc1-ge565ad6 dir Problems setting modules path maps, continuing anyway... ------------------------------------------------------------ perf_event_attr: type 8 size 112 { sample_period, sample_freq } 1 sample_type IP|TID|IDENTIFIER read_format ID disabled 1 exclude_kernel 1 exclude_hv 1 enable_on_exec 1 sample_id_all 1 ------------------------------------------------------------ sys_perf_event_open: pid 2242 cpu -1 group_fd -1 flags 0x8 = 4 ------------------------------------------------------------ perf_event_attr: type 1 size 112 config 0x9 { sample_period, sample_freq } 1 sample_type IP|TID|IDENTIFIER read_format ID disabled 1 exclude_kernel 1 exclude_hv 1 mmap 1 comm 1 enable_on_exec 1 task 1 sample_id_all 1 mmap2 1 comm_exec 1 ------------------------------------------------------------ sys_perf_event_open: pid 2242 cpu -1 group_fd -1 flags 0x8 = 5 mmap size 528384B AUX area mmap length 4194304 perf event ring buffer mmapped per thread failed to mmap AUX area failed to mmap with 12 (Cannot allocate memory) I fixed the "map_groups__set_modules_path_dir: cannot open /lib/modules/4.13.0-rc1-ge565ad6 dir" issue by adding appropriate symbolic link but I still have an issue with the mmap. Any idea what can be wrong here (below limits that I have on my Juno)? [root@alarm ~]# ulimit -a core file size (blocks, -c) unlimited data seg size (kbytes, -d) unlimited scheduling priority (-e) 0 file size (blocks, -f) unlimited pending signals (-i) 31798 max locked memory (kbytes, -l) 64 max memory size (kbytes, -m) unlimited open files (-n) 1024 pipe size (512 bytes, -p) 8 POSIX message queues (bytes, -q) 819200 real-time priority (-r) 0 stack size (kbytes, -s) 8192 cpu time (seconds, -t) unlimited max user processes (-u) 31798 virtual memory (kbytes, -v) unlimited file locks (-x) unlimited [root@alarm ~]# Regards Marek W dniu 2017-08-18 16:54:42 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 18 August 2017 at 04:22, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello Mathieu, > > > > I've decided that currently I don't need Android. The Linux is enough. > > That is probably a better place to start. > > > However I have another issue. I've downloaded the perf-opencsd-master branch. I run the config with the ARCH=arm64 and CROSS_COMPLIE=aarch64-linux-gnu- and added support for Versatile board. Then I compiled kernel - everything was OK. Next I built the USB using the following instruction: > > https://archlinuxarm.org/platforms/armv8/arm/juno (it works fine. The linux boot on the Juno). > > Next I copied the Image file and juno.dtb into the USB but it doesn't boot. It hangs here: > > > > initrd: address 0x0 > > initrd: length 0x0 > > PEI 1132 ms > > DXE 1695 ms > > BDS 368934875444 ms > > BDS 368934873448 ms > > BDS 1535 ms > > Total Time = 368934871781 ms > > > > linux: address 0x80080000 > > linux: length 0x1150200 > > fdt: address 0x9FE00000 > > fdt: length 0x5F54 > > > > Any idea what I'm doing wrong? Any help will be appreciated (I'm so close to have Juno + CoreSight + perf :) ) > > I can't help you with booting the board itself. The best I can do is > advise to use u-boot instead of UEFI and give you my kernel .config > file (attached). For the rest there is plenty of documentation out > there. > > > > > Regards > > Marek > > > > W dniu 2017-08-16 23:08:04 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > >> Hello Marek, > >> > >> Please CC the CoreSight mailing list when asking questions as someone > >> else may also be able to answer. > >> > >> First and foremost I advise using the official CoreSight kernel found > >> on the openCSD site [1] rather than my personal branch [2] - you > >> never know what you'll get with the latter. > >> > >> That being said the CoreSight kernel on the openCSD site is not an > >> Android kernel - it is simply a mainline kernel supplemented with > >> patches that haven't made their way to mainline yet. You will have to > >> either add the android patches to the CoreSight kernel or the other > >> way around (CoreSight patches on android kernel). > >> > >> Android user space is also different and does not include the > >> perf-tools. You will have to add them manually along with the > >> dependencies they require. I haven't gone through that process and as > >> such can't advise more on that portion. > >> > >> Get back to me with your questions if the above isn't sufficient. > >> > >> Best regards, > >> Mathieu > >> > >> [1]. https://github.com/Linaro/OpenCSD/tree/perf-opencsd-master > >> [2]. https://git.linaro.org/people/mathieu.poirier/coresight.git/ > >> > >> On 16 August 2017 at 14:32, marekzmyslowski > >> <marekzmyslowski(a)poczta.onet.pl> wrote: > >> > Hello Mathieu, > >> > > >> > I'm sorry for bothering but I think you may be person that can help me. I'm trying to install and run Android on Juno Board r0. I tested Android 17.05 from Linaro and it works. Now I'm trying to have a perf using Coresight but I'm little confused. Do I need to build Android from Linaro and the kernel from here https://git.linaro.org/people/mathieu.poirier/coresight.git/ or here https://github.com/Linaro/OpenCSD/tree/perf-opencsd-4.12. > >> > Any help with this will be appreciated :) > >> > > >> > Regards > >> > Marek Zmysłowski > >> > > > > > > >

6 years, 1 month

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