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Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures

by Suzuki K Poulose

On 19/10/2021 12:42, Will Deacon wrote: > On Tue, Oct 19, 2021 at 12:36:48PM +0100, Suzuki K Poulose wrote: >> On 19/10/2021 12:02, Will Deacon wrote: >>> On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >>>> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>>> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >>>> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >>>> }, >>>> +#endif >>>> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE >>> >>> You still haven't fixed this typo... >>> >> >> Sorry about that. I thought it was about selecting the >> Kconfig entries, which was fixed. I will fix this. > > Sorry, I thought it was such a howler that it would've jumped out ;) > That's what made me think we should make sure the series compiles without > the coresight changes, so we can catch these problems early. > >>> Seriously, I get compile warnings from this -- are you not seeing them? >> >> No, I don't get any warnings. Is there something that I am missing ? > > Interesting. I see the warning below in my bisection testing, since the typo > means that the midr lookup table isn't used. Maybe you're only compiling the > end result? No, I was compiling this at the commit. Also, please note that the TSB flush failure config is enabled with the patch, unlike the TRBE errata ones. My GCC is : gcc version 9.3.1 20200408 (Red Hat 9.3.1-2) (GCC) $ grep TSB arch/arm64/Kconfig arch/arm64/kernel/cpu_errata.c .config arch/arm64/Kconfig:config ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" arch/arm64/Kconfig: select ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: Affected cores may fail to flush the trace data on a TSB instruction, when arch/arm64/Kconfig: Workaround is to issue two TSB consecutively on affected cores. arch/arm64/Kconfig: bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" arch/arm64/Kconfig: select ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: Affected cores may fail to flush the trace data on a TSB instruction, when arch/arm64/Kconfig: Workaround is to issue two TSB consecutively on affected cores. arch/arm64/kernel/cpu_errata.c:#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/kernel/cpu_errata.c:#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ arch/arm64/kernel/cpu_errata.c:#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE arch/arm64/kernel/cpu_errata.c: .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, .config:CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ git log --oneline -1 89e0c94bd734 (HEAD) arm64: errata: Add workaround for TSB flush failures > > Will > > --->8 > > +arch/arm64/kernel/cpu_errata.c:356:32: warning: ‘tsb_flush_fail_cpus’ defined but not used [-Wunused-const-variable=] > + 356 | static const struct midr_range tsb_flush_fail_cpus[] = { > + | ^~~~~~~~~~~~~~~~~~~ > That looks a valid warning. Hmm, strange. It does complain for an unused function though. $ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o arch/arm64/kernel/cpu_errata.c:90:13: error: ‘here_is_an_unused_function’ defined but not used [-Werror=unused-function] static void here_is_an_unused_function(void) ^~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[2]: *** [scripts/Makefile.build:277: arch/arm64/kernel/cpu_errata.o] Error 1 make[1]: *** [scripts/Makefile.build:540: arch/arm64/kernel] Error 2 make: *** [Makefile:1874: arch/arm64] Error 2 make: *** Waiting for unfinished jobs.... --8>-- diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index aaa66c9eee24..57c83e84b274 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -87,12 +87,20 @@ has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, return (ctr_real != sys) && (ctr_raw != sys); } +static void here_is_an_unused_function(void) +{ + pr_crit("I am unused\n"); +} + static void cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) { u64 mask = arm64_ftr_reg_ctrel0.strict_mask; bool enable_uct_trap = false; +#ifdef CONFIG_UNUSED_FUNCTION + here_is_an_unused_function(); +#endif Cheers Suzuki

5 years

Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures

by Suzuki K Poulose

On 19/10/2021 12:02, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index ccd757373f36..bdbeac75ead6 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { >> }; >> #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ >> >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> +static const struct midr_range tsb_flush_fail_cpus[] = { >> +#ifdef CONFIG_ARM64_ERRATUM_2067961 >> + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), >> +#endif >> +#ifdef CONFIG_ARM64_ERRATUM_2054223 >> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), >> +#endif >> + {}, >> +}; >> +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ >> + >> const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE >> { >> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >> }, >> +#endif >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > > You still haven't fixed this typo... > Sorry about that. I thought it was about selecting the Kconfig entries, which was fixed. I will fix this. > Seriously, I get compile warnings from this -- are you not seeing them? No, I don't get any warnings. Is there something that I am missing ? --8>-- suzuki@ewhatever:coresight$ grep "WERROR\|TSB" .config CONFIG_WERROR=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ grep TSB arch/arm64/kernel/cpu_errata.c #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, suzuki@ewhatever:coresight$ touch arch/arm64/kernel/cpu_errata.c suzuki@ewhatever:coresight$ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o AR arch/arm64/kernel/built-in.a AR arch/arm64/built-in.a GEN .version CHK include/generated/compile.h UPD include/generated/compile.h CC init/version.o AR init/built-in.a LD vmlinux.o MODPOST vmlinux.symvers MODINFO modules.builtin.modinfo GEN modules.builtin LD .tmp_vmlinux.kallsyms1 KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.S LD .tmp_vmlinux.kallsyms2 KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.S LD vmlinux SORTTAB vmlinux SYSMAP System.map MODPOST modules-only.symvers OBJCOPY arch/arm64/boot/Image GEN Module.symvers GZIP arch/arm64/boot/Image.gz Suzuki > > Will >

5 years

Re: [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode

by Suzuki K Poulose

On 19/10/2021 12:04, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:12PM +0100, Suzuki K Poulose wrote: >> Arm Neoverse-N2 and the Cortex-A710 cores are affected >> by a CPU erratum where the TRBE will overwrite the trace buffer >> in FILL mode. The TRBE doesn't stop (as expected in FILL mode) >> when it reaches the limit and wraps to the base to continue >> writing upto 3 cache lines. This will overwrite any trace that >> was written previously. >> >> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum >> (#2119858) to the detection logic. > > Weird typo and double space in this sentence. I have fixed this now. Thanks Suzuki

5 years

Re: [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode

by Suzuki K Poulose

On 19/10/2021 05:36, Anshuman Khandual wrote: > > > On 10/19/21 2:45 AM, Suzuki K Poulose wrote: >> On 18/10/2021 16:51, Mathieu Poirier wrote: >>> On Thu, Oct 14, 2021 at 11:31:20PM +0100, Suzuki K Poulose wrote: >>>> ARM Neoverse-N2 (#2139208) and Cortex-A710(##2119858) suffers from >>>> an erratum, which when triggered, might cause the TRBE to overwrite >>>> the trace data already collected in FILL mode, in the event of a WRAP. >>>> i.e, the TRBE doesn't stop writing the data, instead wraps to the base >>>> and could write upto 3 cache line size worth trace. Thus, this could >>>> corrupt the trace at the "BASE" pointer. >>>> >>>> The workaround is to program the write pointer 256bytes from the >>>> base, such that if the erratum is triggered, it doesn't overwrite >>>> the trace data that was captured. This skipped region could be >>>> padded with ignore packets at the end of the session, so that >>>> the decoder sees a continuous buffer with some padding at the >>>> beginning. The trace data written at the base is considered >>>> lost as the limit could have been in the middle of the perf >>>> ring buffer, and jumping to the "base" is not acceptable. >>>> We set the flags already to indicate that some amount of trace >>>> was lost during the FILL event IRQ. So this is fine. >>>> >>>> One important change with the work around is, we program the >>>> TRBBASER_EL1 to current page where we are allowed to write. >>>> Otherwise, it could overwrite a region that may be consumed >>>> by the perf. Towards this, we always make sure that the >>>> "handle->head" and thus the trbe_write is PAGE_SIZE aligned, >>>> so that we can set the BASE to the PAGE base and move the >>>> TRBPTR to the 256bytes offset. >>>> >>>> Cc: Mike Leach <mike.leach(a)linaro.org> >>>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>>> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >>>> Cc: Leo Yan <leo.yan(a)linaro.org> >>>> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>>> --- >>>> Changes since v2: >>>> - Updated the ASCII art to include better description of >>>> all the steps in the work around >>>> Change since v1: >>>> - Updated comment with ASCII art >>>> - Add _BYTES suffix for the space to skip for the work around. >>>> --- >>>> drivers/hwtracing/coresight/coresight-trbe.c | 169 +++++++++++++++++-- >>>> 1 file changed, 158 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>>> index 314e5e7374c7..b56b166b2dec 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>>> @@ -16,6 +16,7 @@ >>>> #define pr_fmt(fmt) DRVNAME ": " fmt >>>> #include <asm/barrier.h> >>>> +#include <asm/cpufeature.h> >>> >>> Here too I get a checkpatch warning... >>> >> >> That is a false alarm. I guess that warns for including >> linux/cpufeature.h? It is a bit odd, we include this >> for the arm64 cpucaps, not the generic linux feature > > It is a bit odd, I saw that too. > >> checks. (They are used for "loading modules" based >> on "features" which are more like ELF HWCAPs). > > Should <asm/cpufeature.h> be renamed as <asm/arm64_cpufeature.h> > or something similar instead to differentiate it from the generic > <linux/cpufeature.h> as they are not related. Also, probably this > warning could be avoided. It is not that simple. asm/cpufeature.h on arm64 provides : * arch backend for linux/cpufeature.h * CPU feature sanity check infrastructure * CPU capability infrastructure ( features & errata ) So ideally it should be split into 3 for better cleanup and is something that could be pursued outside this series. Suzuki

5 years

[PATCH v2] coresight: trbe: Defer the probe on offline CPUs

by Suzuki K Poulose

If a CPU is offline during the driver init, we could end up causing a kernel crash trying to register the coresight device for the TRBE instance. The trbe_cpudata for the TRBE instance is initialized only when it is probed. Otherwise, we could end up dereferencing a NULL cpudata->drvdata. e.g: [ 0.149999] coresight ete0: CPU0: ete v1.1 initialized [ 0.149999] coresight-etm4x ete_1: ETM arch init failed [ 0.149999] coresight-etm4x: probe of ete_1 failed with error -22 [ 0.150085] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000050 [ 0.150085] Mem abort info: [ 0.150085] ESR = 0x96000005 [ 0.150085] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.150085] SET = 0, FnV = 0 [ 0.150085] EA = 0, S1PTW = 0 [ 0.150085] Data abort info: [ 0.150085] ISV = 0, ISS = 0x00000005 [ 0.150085] CM = 0, WnR = 0 [ 0.150085] [0000000000000050] user address but active_mm is swapper [ 0.150085] Internal error: Oops: 96000005 [#1] PREEMPT SMP [ 0.150085] Modules linked in: [ 0.150085] Hardware name: FVP Base RevC (DT) [ 0.150085] pstate: 00800009 (nzcv daif -PAN +UAO -TCO BTYPE=--) [ 0.150155] pc : arm_trbe_register_coresight_cpu+0x74/0x144 [ 0.150155] lr : arm_trbe_register_coresight_cpu+0x48/0x144 ... [ 0.150237] Call trace: [ 0.150237] arm_trbe_register_coresight_cpu+0x74/0x144 [ 0.150237] arm_trbe_device_probe+0x1c0/0x2d8 [ 0.150259] platform_drv_probe+0x94/0xbc [ 0.150259] really_probe+0x1bc/0x4a8 [ 0.150266] driver_probe_device+0x7c/0xb8 [ 0.150266] device_driver_attach+0x6c/0xac [ 0.150266] __driver_attach+0xc4/0x148 [ 0.150266] bus_for_each_dev+0x7c/0xc8 [ 0.150266] driver_attach+0x24/0x30 [ 0.150266] bus_add_driver+0x100/0x1e0 [ 0.150266] driver_register+0x78/0x110 [ 0.150266] __platform_driver_register+0x44/0x50 [ 0.150266] arm_trbe_init+0x28/0x84 [ 0.150266] do_one_initcall+0x94/0x2bc [ 0.150266] do_initcall_level+0xa4/0x158 [ 0.150266] do_initcalls+0x54/0x94 [ 0.150319] do_basic_setup+0x24/0x30 [ 0.150319] kernel_init_freeable+0xe8/0x14c [ 0.150319] kernel_init+0x14/0x18c [ 0.150319] ret_from_fork+0x10/0x30 [ 0.150319] Code: f94012c8 b0004ce2 9134a442 52819801 (f9402917) [ 0.150319] ---[ end trace d23e0cfe5098535e ]--- [ 0.150346] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b Fix this by skipping the step, if we are unable to probe the CPU. Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") Reported-by: Bransilav Rankov <branislav.rankov(a)arm.com> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Tested-by: Branislav Rankov <branislav.rankov(a)arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- Changes since v1: - Explain why we crash - Add a WARN_ON to ensure the probe was successful. --- drivers/hwtracing/coresight/coresight-trbe.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 5d350acef798..27225b88a2fc 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1182,6 +1182,10 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp if (WARN_ON(trbe_csdev)) return; + /* If the TRBE was not probed on the CPU, we shouldn't be here */ + if (WARN_ON(!cpudata->drvdata)) + return; + dev = &cpudata->drvdata->pdev->dev; desc.name = devm_kasprintf(dev, GFP_KERNEL, "trbe%d", cpu); if (!desc.name) @@ -1286,7 +1290,9 @@ static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata) return -ENOMEM; for_each_cpu(cpu, &drvdata->supported_cpus) { - smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1); + /* If we fail to probe the CPU, let us defer it to hotplug callbacks */ + if (smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1)) + continue; if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) arm_trbe_register_coresight_cpu(drvdata, cpu); if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) -- 2.25.4

5 years

[RFC PATCH 0/2] Support for stopping trace on a programmed address

by Linu Cherian

This patchset adds support for stopping trace on all enabled coresight sources upon execution of a programmed instruction address. ETM stop event is triggered by an instruction address match on a comparator. This address match event is then used to stop the tracing across all ETM source devices with the help of external input/output signals and ECT. The instruction address for the stop event can be programmed using sysfs interface. The event flow diagram is like this, Address comparator --> EXT OUT --> ECT---> EXT IN --> Counter-->ViewInst The original intention of this patch is to stop all ETM sources at the time of kernel panic without software intervention so that it can be used as one of the building block while enabling panic/kdump support in coresight drivers [1]. But there can be other use cases like stopping trace on assertions or error functions etc. as well. I am sending this patch as an RFC so as to get an early feedback on the approach taken for implementation and other inputs if any. Few caveats: - Testing was done only with sysfs interface using a arbitrary kernel symbol address. Perf support will be added later based on initial feedback. - CTI hook for enabling trace event connection need to be rewritten to use existing support APIs. [1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1652258.html Linu Cherian (2): coresight: Add support to setup Trace event signals coresight: etm4x: Add support to generate and synchronize stop event drivers/hwtracing/coresight/coresight-core.c | 37 ++++ .../hwtracing/coresight/coresight-cti-core.c | 21 +++ drivers/hwtracing/coresight/coresight-cti.h | 3 + .../coresight/coresight-etm4x-core.c | 167 ++++++++++++++++++ .../coresight/coresight-etm4x-sysfs.c | 64 +++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 16 ++ include/linux/coresight.h | 6 + 7 files changed, 314 insertions(+) -- 2.31.1

5 years

Re: [PATCH v4 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode

by Suzuki K Poulose

Hi Thanks for the report. I have fixed all of them. Suzuki On 12/10/2021 16:31, Randy Dunlap wrote: > Hi, > > On 10/12/21 6:17 AM, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 077f2ec4eeb2..404f56e87e93 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -666,6 +666,47 @@ config ARM64_ERRATUM_1508412 >> If unsure, say Y. >> +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + bool >> + >> +config ARM64_ERRATUM_2119858 >> + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace >> data in FILL mode" >> + default y >> + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes >> are in >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Cortex-A710 erratum >> 2119858. >> + >> + Affected Cortex-A710 cores could overwrite upto 3 cache lines >> of trace > > up to > >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL >> mode in > > pointed to by > >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the >> TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first >> 256bytes of > > 256 bytes 256 bytes > >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. >> + >> +config ARM64_ERRATUM_2139208 >> + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace >> data in FILL mode" >> + default y >> + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes >> are in >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Neoverse-N2 erratum >> 2139208. >> + >> + Affected Neoverse-N2 cores could overwrite upto 3 cache lines >> of trace > > up to > >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL >> mode in > > pointed to by > >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the >> TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first >> 256bytes of > > 256 bytes 256 bytes > >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. > >

5 years, 1 month

Re: [PATCH] coresight: trbe: Defer the probe on offline CPUs

by Suzuki K Poulose

On 14/10/2021 04:28, Anshuman Khandual wrote: > Hi Suzuki, > > On 10/13/21 10:03 PM, Suzuki K Poulose wrote: >> If a CPU is offline during the driver init, we could end up causing >> a kernel crash trying to register the coresight device for the TRBE >> instance. > > Which pointer deference fails here exactly ? > > static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cpu) > { > struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); > struct coresight_device *trbe_csdev = coresight_get_percpu_sink(cpu); > struct coresight_desc desc = { 0 }; > struct device *dev; > > if (WARN_ON(trbe_csdev)) > return; > > dev = &cpudata->drvdata->pdev->dev; <---- Fails here > > cpudata->drvdata link gets established in arm_trbe_probe_cpu() which > would not have run on an offline cpu. Yes, that is correct. > >> >> e.g: > > Should probably also mention the exact point of dereference failure > before this error message here. > >> >> [ 0.149999] coresight ete0: CPU0: ete v1.1 initialized >> [ 0.149999] coresight-etm4x ete_1: ETM arch init failed >> [ 0.149999] coresight-etm4x: probe of ete_1 failed with error -22 >> [ 0.150085] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000050 >> [ 0.150085] Mem abort info: >> [ 0.150085] ESR = 0x96000005 >> [ 0.150085] EC = 0x25: DABT (current EL), IL = 32 bits >> [ 0.150085] SET = 0, FnV = 0 >> [ 0.150085] EA = 0, S1PTW = 0 >> [ 0.150085] Data abort info: >> [ 0.150085] ISV = 0, ISS = 0x00000005 >> [ 0.150085] CM = 0, WnR = 0 >> [ 0.150085] [0000000000000050] user address but active_mm is swapper >> [ 0.150085] Internal error: Oops: 96000005 [#1] PREEMPT SMP >> [ 0.150085] Modules linked in: >> [ 0.150085] Hardware name: FVP Base RevC (DT) >> [ 0.150085] pstate: 00800009 (nzcv daif -PAN +UAO -TCO BTYPE=--) >> [ 0.150155] pc : arm_trbe_register_coresight_cpu+0x74/0x144 >> [ 0.150155] lr : arm_trbe_register_coresight_cpu+0x48/0x144 >> ... >> >> [ 0.150237] Call trace: >> [ 0.150237] arm_trbe_register_coresight_cpu+0x74/0x144 >> [ 0.150237] arm_trbe_device_probe+0x1c0/0x2d8 >> [ 0.150259] platform_drv_probe+0x94/0xbc >> [ 0.150259] really_probe+0x1bc/0x4a8 >> [ 0.150266] driver_probe_device+0x7c/0xb8 >> [ 0.150266] device_driver_attach+0x6c/0xac >> [ 0.150266] __driver_attach+0xc4/0x148 >> [ 0.150266] bus_for_each_dev+0x7c/0xc8 >> [ 0.150266] driver_attach+0x24/0x30 >> [ 0.150266] bus_add_driver+0x100/0x1e0 >> [ 0.150266] driver_register+0x78/0x110 >> [ 0.150266] __platform_driver_register+0x44/0x50 >> [ 0.150266] arm_trbe_init+0x28/0x84 >> [ 0.150266] do_one_initcall+0x94/0x2bc >> [ 0.150266] do_initcall_level+0xa4/0x158 >> [ 0.150266] do_initcalls+0x54/0x94 >> [ 0.150319] do_basic_setup+0x24/0x30 >> [ 0.150319] kernel_init_freeable+0xe8/0x14c >> [ 0.150319] kernel_init+0x14/0x18c >> [ 0.150319] ret_from_fork+0x10/0x30 >> [ 0.150319] Code: f94012c8 b0004ce2 9134a442 52819801 (f9402917) >> [ 0.150319] ---[ end trace d23e0cfe5098535e ]--- >> [ 0.150346] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b >> >> Fix this by skipping the step, if we are unable to probe the CPU. >> >> Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") >> Reported-by: Bransilav Rankov <branislav.rankov(a)arm.com> >> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Cc: Mike Leach <mike.leach(a)linaro.org> >> Cc: Leo Yan <leo.yan(a)linaro.org> >> Tested-by: Branislav Rankov <branislav.rankov(a)arm.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> drivers/hwtracing/coresight/coresight-trbe.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >> index 5d350acef798..85ceda68af82 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -1286,7 +1286,9 @@ static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata) >> return -ENOMEM; >> >> for_each_cpu(cpu, &drvdata->supported_cpus) { >> - smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1); >> + /* If we fail to probe the CPU, let us defer it to hotplug callbacks */ >> + if (smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1)) >> + continue; >> if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> arm_trbe_register_coresight_cpu(drvdata, cpu); >> if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> > > Right, LGTM. Although I guess the following addition might be worthwhile > just to highlight the fact that cpudata->drvdata is not valid unless the > cpu has gone through arm_trbe_probe_cpu() first. > > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -869,6 +869,7 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp > if (WARN_ON(trbe_csdev)) > return; > > + WARN_ON(!cpudata->drvdata); Ok, I would rather return here with the warning. I will send a revision. Thanks ! Suzuki

5 years, 1 month

[PATCH] coresight: trbe: Defer the probe on offline CPUs

by Suzuki K Poulose

If a CPU is offline during the driver init, we could end up causing a kernel crash trying to register the coresight device for the TRBE instance. e.g: [ 0.149999] coresight ete0: CPU0: ete v1.1 initialized [ 0.149999] coresight-etm4x ete_1: ETM arch init failed [ 0.149999] coresight-etm4x: probe of ete_1 failed with error -22 [ 0.150085] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000050 [ 0.150085] Mem abort info: [ 0.150085] ESR = 0x96000005 [ 0.150085] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.150085] SET = 0, FnV = 0 [ 0.150085] EA = 0, S1PTW = 0 [ 0.150085] Data abort info: [ 0.150085] ISV = 0, ISS = 0x00000005 [ 0.150085] CM = 0, WnR = 0 [ 0.150085] [0000000000000050] user address but active_mm is swapper [ 0.150085] Internal error: Oops: 96000005 [#1] PREEMPT SMP [ 0.150085] Modules linked in: [ 0.150085] Hardware name: FVP Base RevC (DT) [ 0.150085] pstate: 00800009 (nzcv daif -PAN +UAO -TCO BTYPE=--) [ 0.150155] pc : arm_trbe_register_coresight_cpu+0x74/0x144 [ 0.150155] lr : arm_trbe_register_coresight_cpu+0x48/0x144 ... [ 0.150237] Call trace: [ 0.150237] arm_trbe_register_coresight_cpu+0x74/0x144 [ 0.150237] arm_trbe_device_probe+0x1c0/0x2d8 [ 0.150259] platform_drv_probe+0x94/0xbc [ 0.150259] really_probe+0x1bc/0x4a8 [ 0.150266] driver_probe_device+0x7c/0xb8 [ 0.150266] device_driver_attach+0x6c/0xac [ 0.150266] __driver_attach+0xc4/0x148 [ 0.150266] bus_for_each_dev+0x7c/0xc8 [ 0.150266] driver_attach+0x24/0x30 [ 0.150266] bus_add_driver+0x100/0x1e0 [ 0.150266] driver_register+0x78/0x110 [ 0.150266] __platform_driver_register+0x44/0x50 [ 0.150266] arm_trbe_init+0x28/0x84 [ 0.150266] do_one_initcall+0x94/0x2bc [ 0.150266] do_initcall_level+0xa4/0x158 [ 0.150266] do_initcalls+0x54/0x94 [ 0.150319] do_basic_setup+0x24/0x30 [ 0.150319] kernel_init_freeable+0xe8/0x14c [ 0.150319] kernel_init+0x14/0x18c [ 0.150319] ret_from_fork+0x10/0x30 [ 0.150319] Code: f94012c8 b0004ce2 9134a442 52819801 (f9402917) [ 0.150319] ---[ end trace d23e0cfe5098535e ]--- [ 0.150346] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b Fix this by skipping the step, if we are unable to probe the CPU. Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") Reported-by: Bransilav Rankov <branislav.rankov(a)arm.com> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Tested-by: Branislav Rankov <branislav.rankov(a)arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 5d350acef798..85ceda68af82 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1286,7 +1286,9 @@ static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata) return -ENOMEM; for_each_cpu(cpu, &drvdata->supported_cpus) { - smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1); + /* If we fail to probe the CPU, let us defer it to hotplug callbacks */ + if (smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1)) + continue; if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) arm_trbe_register_coresight_cpu(drvdata, cpu); if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) -- 2.25.4

5 years, 1 month

[PATCH v4 00/15] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. The Kconfig items for the TRBE errata are initially dropped in with dependency on COMPILE_TEST. These are dropped only after the driver is equipped with the work around in later patches. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v4 Changes since v3: - Fix missing Kconfig selection for TSB flush failure erratum (Will) Merged the Kconfig changes to the core patch for TSB. - Use COMPILE_TEST dependency for the TRBE work arounds instead of delaying the Kconfig entries. Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (15): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 111 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 ++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 382 +++++++++++++++++-- 7 files changed, 556 insertions(+), 36 deletions(-) -- 2.25.4

5 years, 1 month

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