CoreSight

coresight@lists.linaro.org

7 participants
2807 discussions

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8 years, 2 months

[PATCH v2 1/2] perf cs-etm: Support unknown_thread in cs_etm_auxtrace

by Leo Yan

CoreSight doesn't allocate thread structure for unknown_thread in etm auxtrace, so unknown_thread is NULL pointer. If the perf data doesn't contain valid tid and then cs_etm__mem_access() uses unknown_thread instead as thread handler, this results in segmentation fault when thread__find_addr_map() accesses thread handler. This commit creates new thread data which is used by unknown_thread, so CoreSight tracing can roll back to use unknown_thread if perf data doesn't include valid thread info. This commit also releases thread data for initialization failure case and for normal auxtrace free flow. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> Acked-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> --- tools/perf/util/cs-etm.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 6533b1a..69f21de 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -239,6 +239,7 @@ static void cs_etm__free(struct perf_session *session) for (i = 0; i < aux->num_cpu; i++) zfree(&aux->metadata[i]); + thread__zput(aux->unknown_thread); zfree(&aux->metadata); zfree(&aux); } @@ -1355,6 +1356,23 @@ int cs_etm__process_auxtrace_info(union perf_event *event, etm->auxtrace.free = cs_etm__free; session->auxtrace = &etm->auxtrace; + etm->unknown_thread = thread__new(999999999, 999999999); + if (!etm->unknown_thread) + goto err_free_queues; + + /* + * Initialize list node so that at thread__zput() we can avoid + * segmentation fault at list_del_init(). + */ + INIT_LIST_HEAD(&etm->unknown_thread->node); + + err = thread__set_comm(etm->unknown_thread, "unknown", 0); + if (err) + goto err_delete_thread; + + if (thread__init_map_groups(etm->unknown_thread, etm->machine)) + goto err_delete_thread; + if (dump_trace) { cs_etm__print_auxtrace_info(auxtrace_info->priv, num_cpu); return 0; @@ -1369,16 +1387,18 @@ int cs_etm__process_auxtrace_info(union perf_event *event, err = cs_etm__synth_events(etm, session); if (err) - goto err_free_queues; + goto err_delete_thread; err = auxtrace_queues__process_index(&etm->queues, session); if (err) - goto err_free_queues; + goto err_delete_thread; etm->data_queued = etm->queues.populated; return 0; +err_delete_thread: + thread__zput(etm->unknown_thread); err_free_queues: auxtrace_queues__free(&etm->queues); session->auxtrace = NULL; -- 2.7.4

8 years, 2 months

[PATCH 1/2] perf cs-etm: Support unknown_thread in cs_etm_auxtrace

by Leo Yan

CoreSight doesn't allocate thread structure for unknown_thread in etm auxtrace, so unknown_thread is NULL pointer. If the perf data doesn't contain valid tid and then cs_etm__mem_access() uses unknown_thread instead as thread handler, this results in segmentation fault when thread__find_addr_map() accesses thread handler. This commit creates new thread data which is used by unknown_thread, so CoreSight tracing can roll back to use unknown_thread if perf data doesn't include valid thread info. This commit also releases thread data for initialization failure case and for normal auxtrace free flow. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/util/cs-etm.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 6533b1a..417302c 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -239,6 +239,7 @@ static void cs_etm__free(struct perf_session *session) for (i = 0; i < aux->num_cpu; i++) zfree(&aux->metadata[i]); + thread__zput(aux->unknown_thread); zfree(&aux->metadata); zfree(&aux); } @@ -266,6 +267,7 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u64 address, if (!thread) { if (cpumode != PERF_RECORD_MISC_KERNEL) return -EINVAL; + thread = etmq->etm->unknown_thread; } @@ -1355,6 +1357,23 @@ int cs_etm__process_auxtrace_info(union perf_event *event, etm->auxtrace.free = cs_etm__free; session->auxtrace = &etm->auxtrace; + etm->unknown_thread = thread__new(999999999, 999999999); + if (!etm->unknown_thread) + goto err_free_queues; + + /* + * Initialize list node so that at thread__zput() we can avoid + * segmentation fault at list_del_init(). + */ + INIT_LIST_HEAD(&etm->unknown_thread->node); + + err = thread__set_comm(etm->unknown_thread, "unknown", 0); + if (err) + goto err_delete_thread; + + if (thread__init_map_groups(etm->unknown_thread, etm->machine)) + goto err_delete_thread; + if (dump_trace) { cs_etm__print_auxtrace_info(auxtrace_info->priv, num_cpu); return 0; @@ -1369,16 +1388,18 @@ int cs_etm__process_auxtrace_info(union perf_event *event, err = cs_etm__synth_events(etm, session); if (err) - goto err_free_queues; + goto err_delete_thread; err = auxtrace_queues__process_index(&etm->queues, session); if (err) - goto err_free_queues; + goto err_delete_thread; etm->data_queued = etm->queues.populated; return 0; +err_delete_thread: + thread__zput(etm->unknown_thread); err_free_queues: auxtrace_queues__free(&etm->queues); session->auxtrace = NULL; -- 2.7.4

8 years, 2 months

[PATCH 1/4] tests: printf parameter bugfix

by Mike Leach

>From original patchset created-by: Wookey <wookey(a)wookware.org> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- decoder/tests/ext_dcd_test_eg/c_api_echo_test/ext_dcd_echo_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/decoder/tests/ext_dcd_test_eg/c_api_echo_test/ext_dcd_echo_test.c b/decoder/tests/ext_dcd_test_eg/c_api_echo_test/ext_dcd_echo_test.c index 32365ef..e2ad045 100644 --- a/decoder/tests/ext_dcd_test_eg/c_api_echo_test/ext_dcd_echo_test.c +++ b/decoder/tests/ext_dcd_test_eg/c_api_echo_test/ext_dcd_echo_test.c @@ -330,7 +330,7 @@ void print_test_cov_results(echo_decoder_t *decoder) if (coverage[TEST_COV_MSGLOG_CB] == TEST_RES_OK) /* check we can use the msg logger for outputting the results */ lib_cb_LogMsg(p_fns, OCSD_ERR_SEV_ERROR, coverage_message); else - printf(coverage_message); + printf("%s", coverage_message); } } -- 2.14.2

8 years, 2 months

[RFC PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

by Robert Walker

This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. A32 has a fixed 4 byte instruction size, so the conversion between addresses and instruction counts is handled in the same way as A64. T32 has variable 2 or 4 byte instruction size, so the conversion between addresses and instruction counts requires examination of the instruction bytes. Signed-off-by: Robert Walker <robert.walker(a)arm.com> --- This patch is an initial draft of support for trace of A32 / T32 programs. We need to pass the instruction set for each executed range from the decoder and then use the instruction set information when converting between executed address ranges and instruction counts - for T32 we need to look at the individual instructions to determine if they are 2 or 4 bytes. Regards Rob tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 21 ++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 8 +++ tools/perf/util/cs-etm.c | 93 +++++++++++++++---------- 3 files changed, 86 insertions(+), 36 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 640af88..fbd356f 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -256,6 +256,7 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder) for (i = 0; i < MAX_BUFFER; i++) { decoder->packet_buffer[i].start_addr = 0xdeadbeefdeadbeefUL; decoder->packet_buffer[i].end_addr = 0xdeadbeefdeadbeefUL; + decoder->packet_buffer[i].isa = CS_ETM_ISA_UNKNOWN; decoder->packet_buffer[i].last_instr_taken_branch = false; decoder->packet_buffer[i].exc = false; decoder->packet_buffer[i].exc_ret = false; @@ -285,6 +286,7 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_count++; decoder->packet_buffer[et].sample_type = sample_type; + decoder->packet_buffer[et].isa = CS_ETM_ISA_UNKNOWN; decoder->packet_buffer[et].exc = false; decoder->packet_buffer[et].exc_ret = false; decoder->packet_buffer[et].cpu = *((int *)inode->priv); @@ -314,6 +316,25 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder, packet->start_addr = elem->st_addr; packet->end_addr = elem->en_addr; + + switch (elem->isa) { + case ocsd_isa_aarch64: + packet->isa = CS_ETM_ISA_A64; + break; + case ocsd_isa_arm: + packet->isa = CS_ETM_ISA_A32; + break; + case ocsd_isa_thumb2: + packet->isa = CS_ETM_ISA_T32; + break; + case ocsd_isa_tee: + case ocsd_isa_jazelle: + case ocsd_isa_custom: + case ocsd_isa_unknown: + default: + packet->isa = CS_ETM_ISA_UNKNOWN; + } + switch (elem->last_i_type) { case OCSD_INSTR_BR: case OCSD_INSTR_BR_INDIRECT: diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index 743f5f4..630292e 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -27,10 +27,18 @@ enum cs_etm_sample_type { CS_ETM_TRACE_ON = 1 << 1, }; +enum cs_etm_isa { + CS_ETM_ISA_UNKNOWN, + CS_ETM_ISA_A64, + CS_ETM_ISA_A32, + CS_ETM_ISA_T32, +}; + struct cs_etm_packet { enum cs_etm_sample_type sample_type; u64 start_addr; u64 end_addr; + enum cs_etm_isa isa; u8 last_instr_taken_branch; u8 exc; u8 exc_ret; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 1b0d422..004ace3 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -32,14 +32,6 @@ #define MAX_TIMESTAMP (~0ULL) -/* - * A64 instructions are always 4 bytes - * - * Only A64 is supported, so can use this constant for converting between - * addresses and instruction counts, calculting offsets etc - */ -#define A64_INSTR_SIZE 4 - struct cs_etm_auxtrace { struct auxtrace auxtrace; struct auxtrace_queues queues; @@ -494,40 +486,69 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq) etmq->last_branch_rb->nr = 0; } -static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet) +static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq, + u64 addr) { + u8 instrBytes[2]; + cs_etm__mem_access(etmq, addr, 2, instrBytes); + return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2; +} + +static inline u64 cs_etm__last_executed_instr(struct cs_etm_queue *etmq) { + const struct cs_etm_packet *packet = etmq->prev_packet; + /* * The packet records the execution range with an exclusive end address - * - * A64 instructions are constant size, so the last executed - * instruction is A64_INSTR_SIZE before the end address - * Will need to do instruction level decode for T32 instructions as - * they can be variable size (not yet supported). */ - return packet->end_addr - A64_INSTR_SIZE; + if (packet->isa == CS_ETM_ISA_T32) { + /* + * T32 instructions can be either 2 or 4 bytes + */ + if (packet->end_addr - packet->start_addr == 2) + /* Only one 2 byte instruction in packet*/ + return packet->start_addr; + else if (cs_etm__t32_instr_size(etmq, packet->end_addr) == 4) + return packet->end_addr - 4; + else + return packet->end_addr - 2; + } else { + /* Assume a 4 byte instruction size (A32/A64) */ + return packet->end_addr - 4; + } } -static inline u64 cs_etm__instr_count(const struct cs_etm_packet *packet) +static inline u64 cs_etm__instr_count(struct cs_etm_queue *etmq, + const struct cs_etm_packet *packet) { - /* - * Only A64 instructions are currently supported, so can get - * instruction count by dividing. - * Will need to do instruction level decode for T32 instructions as - * they can be variable size (not yet supported). - */ - return (packet->end_addr - packet->start_addr) / A64_INSTR_SIZE; + if (packet->isa == CS_ETM_ISA_T32) { + u64 addr = packet->start_addr; + u64 count = 0; + while (addr != packet->end_addr) { + addr += cs_etm__t32_instr_size(etmq, addr); + count++; + } + return count; + } else { + /* Assume a 4 byte instruction size (A32/A64) */ + return (packet->end_addr - packet->start_addr) / 4; + } } -static inline u64 cs_etm__instr_addr(const struct cs_etm_packet *packet, +static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq, + const struct cs_etm_packet *packet, u64 offset) { - /* - * Only A64 instructions are currently supported, so can get - * instruction address by muliplying. - * Will need to do instruction level decode for T32 instructions as - * they can be variable size (not yet supported). - */ - return packet->start_addr + offset * A64_INSTR_SIZE; + if (packet->isa == CS_ETM_ISA_T32) { + u64 addr = packet->start_addr; + while (offset > 0) { + addr += cs_etm__t32_instr_size(etmq, addr); + offset--; + } + return addr; + } else { + /* Assume a 4 byte instruction size (A32/A64) */ + return packet->start_addr + offset * 4; + } } static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq) @@ -547,7 +568,7 @@ static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq) etmq->last_branch_pos -= 1; be = &bs->entries[etmq->last_branch_pos]; - be->from = cs_etm__last_executed_instr(etmq->prev_packet); + be->from = cs_etm__last_executed_instr(etmq); be->to = etmq->packet->start_addr; /* No support for mispredict */ be->flags.mispred = 0; @@ -700,7 +721,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq) event->sample.header.misc = PERF_RECORD_MISC_USER; event->sample.header.size = sizeof(struct perf_event_header); - sample.ip = cs_etm__last_executed_instr(etmq->prev_packet); + sample.ip = cs_etm__last_executed_instr(etmq); sample.pid = etmq->pid; sample.tid = etmq->tid; sample.addr = etmq->packet->start_addr; @@ -858,7 +879,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq) int ret; u64 instrs_executed; - instrs_executed = cs_etm__instr_count(etmq->packet); + instrs_executed = cs_etm__instr_count(etmq, etmq->packet); etmq->period_instructions += instrs_executed; /* @@ -888,7 +909,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq) * executed, but PC has not advanced to next instruction) */ u64 offset = (instrs_executed - instrs_over - 1); - u64 addr = cs_etm__instr_addr(etmq->packet, offset); + u64 addr = cs_etm__instr_addr(etmq, etmq->packet, offset); ret = cs_etm__synth_instruction_sample( etmq, addr, etm->instructions_sample_period); @@ -936,7 +957,7 @@ static int cs_etm__flush(struct cs_etm_queue *etmq) * Use the address of the end of the last reported execution * range */ - u64 addr = cs_etm__last_executed_instr(etmq->prev_packet); + u64 addr = cs_etm__last_executed_instr(etmq); err = cs_etm__synth_instruction_sample( etmq, addr, -- 2.7.4

8 years, 2 months

Re: Upstream support for ETM strobing

by Mathieu Poirier

On 27 April 2018 at 12:24, Robert Walker <Robert.Walker(a)arm.com> wrote: > Hi, > > > > Strobing the ETM to reduce the amount of trace data when collecting profiles > for AutoFDO seems to be working and providing useful optimizations. We’re > currently working with some proof of concept patches (attached for > reference) that add parameters to sysfs to configure the strobe period – > before running perf record, the user must write to these parameters for each > ETM. This isn’t suitable for production use as it has to be done for each > ETM and the values persist after the trace session. To get this into > upstream, we need to have this done by the perf record tool. > > > > I understand there is work planned to enable more complex ETM configurations > (such as strobing) from perf, possibly using a file to load register values > from. Is this still the case, and if so, when is it likely to be done? Hi Robert, I am currently working on supporting CPU-wide trace scenarios where I can start seeing the end of the tunnel. After that my plan was to add support for ETMv3.x/PTM trace decoding followed by support for N:N source/sink topology. Part of the latter is to introduce a way to enable more complex ETM configuration using a configuration file. In fact I already stumbled on how I want to do that and have a (very) small prototype that works. So that is what I had in mind... But it doesn't mean I can't be talked into changing my priorities. In fact I will gladly do so if we, as a group, decide it is more important to introduce support for complex configuration before ETMv3.x/PTM decoding. I personally don't have a preference, it is simply a matter of deciding what we want to do. I have CC'ed the coresight mailing list in order to reach a broader audience. Please speak up if you really have an issue (along with the rational) with supporting ETM complex configurations before ETMv3.x/PTM decoding. Best regards, Mathieu > > > > Thanks > > > > Rob > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you.

8 years, 2 months

RE: IBM lotus-accounts

by Chris Samuel

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8 years, 2 months

RE: California Dental Association - Spring - CDA 2018 Attendees list

by Rick Forster

Hello, I hope you're doing well! I am following up with you on the below since I have not heard back from you. Please let me know if you would like to get more information on the same. Looking forward to hearing from you. Warm Regards, Rick Forster From: Rick Forster [mailto:rick.forster@attendeeinfo.com] Sent: 24 April 2018 09:23 To: 'coresight(a)lists.linaro.org' Subject: California Dental Association - Spring - CDA 2018 Attendees list Hello, I hope you are the right person to discuss about California Dental Association - Spring - CDA May 2018 Attendees Info? California Dental Association - Spring - CDA 2018 Attendees list of 18,900 contacts with complete contact details and verified email addresses info will be provided for unlimited usage. Interested? Email me back, I'd love to provide more information. Thank you. Regards, Rick Foster Demand Generation Executive. If you do not wish to receive future emails from us, please reply as "opt-out"

8 years, 3 months

California Dental Association - Spring - CDA 2018 Attendees list

by Rick Forster

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8 years, 3 months

[PATCH v2 3/4] coresight: allow to build as modules

by Kim Phillips

Allow to build coresight as modules. This greatly enhances developer efficiency by allowing the development to take place exclusively on the target, and without needing to reboot in between changes. - Kconfig bools become tristates, to allow =m - MODULE_* macros added: Please correct me if I'm wrong: - assume LICENSE is "GPL v2" - tried to get as close to original authors for MODULE_AUTHOR - The 'select' Kconfig statements are replaced with 'depends on' clauses, to specify the dependencies between the modules including other fixes, e.g., coresight-stm unconditionally calls stm_register_device, it therefore depends on STM. - use -objs to denote merge object directives in Makefile, adds a coresight-core nomenclature for the base module. - add a coresight_exit() that unregisters the coresight bus, add remove fns for most others. - fix up modules with ID tables for autoloading on boot, add missing __init and __exit attributes - move coresight_vpid_to_pid to an externed, single instance in coresight-core, to be used by all submodules. Signed-off-by: Kim Phillips <kim.phillips(a)arm.com> --- Change(s) from first PATCH series: - added user Kconfig help text with the names of the modules. - Addressed Mathieu's comments: - renamed coresight-link-sink-tmc coresight-tmc-core - prevent ability to crash the system by removing drivers from an active path by adding try_module_get() and module_put() calls in funnel and replicator drivers' enable and disable functions (thanks for figuring that out, Mathieu). Change(s) from RFC: Addressed most of Mathieu's comments: - rm __inits causing linker section mismatch errors - barrier_pkt made static, moved to coresight_priv.h - rm unnecessary tmc_* EXPORT_SYMBOL leftovers - add some missing MODULE_AUTHORs drivers/hwtracing/coresight/Kconfig | 63 +++++++++++++------ drivers/hwtracing/coresight/Makefile | 28 ++++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../coresight/coresight-dynamic-replicator.c | 18 +++++- drivers/hwtracing/coresight/coresight-etb10.c | 19 +++++- .../hwtracing/coresight/coresight-etm-cp14.c | 4 ++ .../hwtracing/coresight/coresight-etm-perf.c | 13 +++- .../hwtracing/coresight/coresight-etm-perf.h | 2 +- .../coresight/coresight-etm3x-sysfs.c | 6 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 19 +++++- .../coresight/coresight-etm4x-sysfs.c | 6 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 20 +++++- .../hwtracing/coresight/coresight-funnel.c | 24 ++++++- drivers/hwtracing/coresight/coresight-priv.h | 10 ++- .../coresight/coresight-replicator.c | 25 +++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 +++++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 + .../hwtracing/coresight/coresight-tmc-etr.c | 2 + drivers/hwtracing/coresight/coresight-tmc.c | 19 +++++- drivers/hwtracing/coresight/coresight-tpiu.c | 19 +++++- drivers/hwtracing/coresight/coresight.c | 49 ++++++++++++--- include/linux/coresight.h | 23 +------ 22 files changed, 324 insertions(+), 69 deletions(-) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ef9cb3c164e1..09a682013ea2 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -2,8 +2,8 @@ # Coresight configuration # menuconfig CORESIGHT - bool "CoreSight Tracing Support" - select ARM_AMBA + tristate "CoreSight Tracing Support" + depends on ARM_AMBA select PERF_EVENTS help This framework provides a kernel interface for the CoreSight debug @@ -12,17 +12,24 @@ menuconfig CORESIGHT specification and configure the right series of components when a trace source gets enabled. + To compile this code as a module, choose M here: the + module will be called coresight-core. + if CORESIGHT config CORESIGHT_LINKS_AND_SINKS - bool "CoreSight Link and Sink drivers" + tristate "CoreSight Link and Sink drivers" + depends on CORESIGHT help This enables support for CoreSight link and sink drivers that are responsible for transporting and collecting the trace data respectively. Link and sinks are dynamically aggregated with a trace entity at run time to form a complete trace path. + To compile this code as modules, choose M here: the + modules will be called coresight-funnel and coresight-replicator. + config CORESIGHT_LINK_AND_SINK_TMC - bool "Coresight generic TMC driver" + tristate "Coresight generic TMC driver" depends on CORESIGHT_LINKS_AND_SINKS help This enables support for the Trace Memory Controller driver. @@ -31,8 +38,11 @@ config CORESIGHT_LINK_AND_SINK_TMC complies with the generic implementation of the component without special enhancement or added features. + To compile this code as a module, choose M here: the + module will be called coresight-tmc-core. + config CORESIGHT_SINK_TPIU - bool "Coresight generic TPIU driver" + tristate "Coresight generic TPIU driver" depends on CORESIGHT_LINKS_AND_SINKS help This enables support for the Trace Port Interface Unit driver, @@ -42,57 +52,71 @@ config CORESIGHT_SINK_TPIU connected to an external host for use case capturing more traces than the on-board coresight memory can handle. + To compile this code as a module, choose M here: the + module will be called coresight-tpiu. + config CORESIGHT_SINK_ETBV10 - bool "Coresight ETBv1.0 driver" + tristate "Coresight ETBv1.0 driver" depends on CORESIGHT_LINKS_AND_SINKS help This enables support for the Embedded Trace Buffer version 1.0 driver that complies with the generic implementation of the component without special enhancement or added features. + To compile this code as a module, choose M here: the + module will be called coresight-etb10. + config CORESIGHT_SOURCE_ETM3X - bool "CoreSight Embedded Trace Macrocell 3.x driver" - depends on !ARM64 - select CORESIGHT_LINKS_AND_SINKS + tristate "CoreSight Embedded Trace Macrocell 3.x driver" + depends on !ARM64 && CORESIGHT_LINKS_AND_SINKS help This driver provides support for processor ETM3.x and PTM1.x modules, which allows tracing the instructions that a processor is executing This is primarily useful for instruction level tracing. Depending the ETM version data tracing may also be available. + To compile this code as a module, choose M here: the + module will be called coresight-etm3x-core. + config CORESIGHT_SOURCE_ETM4X - bool "CoreSight Embedded Trace Macrocell 4.x driver" - depends on ARM64 - select CORESIGHT_LINKS_AND_SINKS + tristate "CoreSight Embedded Trace Macrocell 4.x driver" + depends on ARM64 && CORESIGHT_LINKS_AND_SINKS help This driver provides support for the ETM4.x tracer module, tracing the instructions that a processor is executing. This is primarily useful for instruction level tracing. Depending on the implemented version data tracing may also be available. + To compile this code as a module, choose M here: the + module will be called coresight-etm4x-core. + config CORESIGHT_DYNAMIC_REPLICATOR - bool "CoreSight Programmable Replicator driver" + tristate "CoreSight Programmable Replicator driver" depends on CORESIGHT_LINKS_AND_SINKS help This enables support for dynamic CoreSight replicator link driver. The programmable ATB replicator allows independent filtering of the trace data based on the traceid. + To compile this code as a module, choose M here: the + module will be called coresight-dynamic-replicator. + config CORESIGHT_STM - bool "CoreSight System Trace Macrocell driver" + tristate "CoreSight System Trace Macrocell driver" depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 - select CORESIGHT_LINKS_AND_SINKS - select STM + depends on STM && CORESIGHT_LINKS_AND_SINKS help This driver provides support for hardware assisted software instrumentation based tracing. This is primarily used for logging useful software events or data coming from various entities in the system, possibly running different OSs + To compile this code as a module, choose M here: the + module will be called coresight-stm. + config CORESIGHT_CPU_DEBUG tristate "CoreSight CPU Debug driver" - depends on ARM || ARM64 - depends on DEBUG_FS + depends on CORESIGHT && DEBUG_FS help This driver provides support for coresight debugging module. This is primarily used to dump sample-based profiling registers when @@ -103,4 +127,7 @@ config CORESIGHT_CPU_DEBUG properly, please refer Documentation/trace/coresight-cpu-debug.txt for detailed description and the example for usage. + To compile this code as a module, choose M here: the + module will be called coresight-cpu-debug. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 61db9dd0d571..5990710289c2 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -2,19 +2,29 @@ # # Makefile for CoreSight drivers. # -obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o -obj-$(CONFIG_OF) += of_coresight.o -obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o \ - coresight-tmc-etf.o \ - coresight-tmc-etr.o +obj-$(CONFIG_CORESIGHT) += coresight-core.o +coresight-core-objs := coresight.o \ + of_coresight.o + +obj-$(CONFIG_CORESIGHT) += coresight-etm-perf.o + +obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc-core.o +coresight-tmc-core-objs := coresight-tmc.o \ + coresight-tmc-etf.o \ + coresight-tmc-etr.o obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o -obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \ - coresight-etm3x-sysfs.o -obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ - coresight-etm4x-sysfs.o + +obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x-core.o +coresight-etm3x-core-objs := coresight-etm3x.o \ + coresight-etm-cp14.o \ + coresight-etm3x-sysfs.o + +obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x-core.o +coresight-etm4x-core-objs := coresight-etm4x.o coresight-etm4x-sysfs.o + obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 9cdb3fbc8c1f..ff6d3be1b13c 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -683,6 +683,8 @@ static const struct amba_id debug_ids[] = { { 0, 0 }, }; +MODULE_DEVICE_TABLE(amba, debug_ids); + static struct amba_driver debug_driver = { .drv = { .name = "coresight-cpu-debug", diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c index 043da86b0fe9..a7f486a577b0 100644 --- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c +++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c @@ -167,6 +167,15 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR_OR_ZERO(drvdata->csdev); } +static int __exit replicator_remove(struct amba_device *adev) +{ + struct replicator_state *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + #ifdef CONFIG_PM static int replicator_runtime_suspend(struct device *dev) { @@ -208,6 +217,8 @@ static const struct amba_id replicator_ids[] = { { 0, 0 }, }; +MODULE_DEVICE_TABLE(amba, replicator_ids); + static struct amba_driver replicator_driver = { .drv = { .name = "coresight-dynamic-replicator", @@ -215,6 +226,11 @@ static struct amba_driver replicator_driver = { .suppress_bind_attrs = true, }, .probe = replicator_probe, + .remove = replicator_remove, .id_table = replicator_ids, }; -builtin_amba_driver(replicator_driver); +module_amba_driver(replicator_driver); + +MODULE_AUTHOR("Suzuki K Poulose <suzuki.poulose(a)arm.com>"); +MODULE_DESCRIPTION("ARM Coresight Dynamic Replicator Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 580cd381adf3..f5464556b8e7 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -719,6 +719,15 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return ret; } +static int __exit etb_remove(struct amba_device *adev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + #ifdef CONFIG_PM static int etb_runtime_suspend(struct device *dev) { @@ -753,6 +762,8 @@ static const struct amba_id etb_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, etb_ids); + static struct amba_driver etb_driver = { .drv = { .name = "coresight-etb10", @@ -762,6 +773,12 @@ static struct amba_driver etb_driver = { }, .probe = etb_probe, + .remove = etb_remove, .id_table = etb_ids, }; -builtin_amba_driver(etb_driver); +module_amba_driver(etb_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight Embedded Trace Buffer driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etm-cp14.c b/drivers/hwtracing/coresight/coresight-etm-cp14.c index 12a220682117..1e16a6358364 100644 --- a/drivers/hwtracing/coresight/coresight-etm-cp14.c +++ b/drivers/hwtracing/coresight/coresight-etm-cp14.c @@ -589,3 +589,7 @@ int etm_writel_cp14(u32 reg, u32 val) return 0; } + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_DESCRIPTION("Arm CoreSight ETM CP14 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 4e5ed6597f2f..152f2ae49665 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -477,6 +477,7 @@ int etm_perf_symlink(struct coresight_device *csdev, bool link) return 0; } +EXPORT_SYMBOL_GPL(etm_perf_symlink); static int __init etm_perf_init(void) { @@ -504,4 +505,14 @@ static int __init etm_perf_init(void) return ret; } -device_initcall(etm_perf_init); +module_init(etm_perf_init); + +static void __exit etm_perf_exit(void) +{ + perf_pmu_unregister(&etm_pmu); +} +module_exit(etm_perf_exit); + +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight tracer perf driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 3ffc9feb2d64..8c49c7b82d84 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -54,7 +54,7 @@ struct etm_filters { }; -#ifdef CONFIG_CORESIGHT +#if IS_ENABLED(CONFIG_CORESIGHT) int etm_perf_symlink(struct coresight_device *csdev, bool link); #else diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 6e547ec6fead..65cfec6e1749 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -17,6 +17,7 @@ #include <linux/pm_runtime.h> #include <linux/sysfs.h> +#include <linux/coresight.h> #include "coresight-etm.h" #include "coresight-priv.h" @@ -1274,3 +1275,8 @@ const struct attribute_group *coresight_etm_groups[] = { &coresight_etm_mgmt_group, NULL, }; + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace sysfs driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 39f42fdd503d..b1e3fd7ed059 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -873,6 +873,15 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) return ret; } +static int __exit etm_remove(struct amba_device *adev) +{ + struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + #ifdef CONFIG_PM static int etm_runtime_suspend(struct device *dev) { @@ -933,6 +942,8 @@ static const struct amba_id etm_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, etm_ids); + static struct amba_driver etm_driver = { .drv = { .name = "coresight-etm3x", @@ -941,6 +952,12 @@ static struct amba_driver etm_driver = { .suppress_bind_attrs = true, }, .probe = etm_probe, + .remove = etm_remove, .id_table = etm_ids, }; -builtin_amba_driver(etm_driver); +module_amba_driver(etm_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index d21961710713..04119b963454 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -17,6 +17,7 @@ #include <linux/pm_runtime.h> #include <linux/sysfs.h> +#include <linux/coresight.h> #include "coresight-etm4x.h" #include "coresight-priv.h" @@ -2155,3 +2156,8 @@ const struct attribute_group *coresight_etmv4_groups[] = { &coresight_etmv4_trcidr_group, NULL, }; +EXPORT_SYMBOL_GPL(coresight_etmv4_groups); + +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4 sysfs driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index cf364a514c12..89b6afe46b79 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1052,6 +1052,15 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return ret; } +static int __exit etm4_remove(struct amba_device *adev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + static const struct amba_id etm4_ids[] = { { /* ETM 4.0 - Cortex-A53 */ .id = 0x000bb95d, @@ -1071,12 +1080,21 @@ static const struct amba_id etm4_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, etm4_ids); + static struct amba_driver etm4x_driver = { .drv = { .name = "coresight-etm4x", + .owner = THIS_MODULE, .suppress_bind_attrs = true, }, .probe = etm4_probe, + .remove = etm4_remove, .id_table = etm4_ids, }; -builtin_amba_driver(etm4x_driver); +module_amba_driver(etm4x_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 9f8ac0bef853..23713c694213 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -69,6 +69,10 @@ static int funnel_enable(struct coresight_device *csdev, int inport, int outport) { struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct module *module = csdev->dev.parent->driver->owner; + + if (!try_module_get(module)) + return -ENODEV; funnel_enable_hw(drvdata, inport); @@ -93,9 +97,11 @@ static void funnel_disable(struct coresight_device *csdev, int inport, int outport) { struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct module *module = csdev->dev.parent->driver->owner; funnel_disable_hw(drvdata, inport); + module_put(module); dev_info(drvdata->dev, "FUNNEL inport %d disabled\n", inport); } @@ -218,6 +224,15 @@ static int funnel_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR_OR_ZERO(drvdata->csdev); } +static int __exit funnel_remove(struct amba_device *adev) +{ + struct funnel_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + #ifdef CONFIG_PM static int funnel_runtime_suspend(struct device *dev) { @@ -257,6 +272,8 @@ static const struct amba_id funnel_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, funnel_ids); + static struct amba_driver funnel_driver = { .drv = { .name = "coresight-funnel", @@ -265,6 +282,11 @@ static struct amba_driver funnel_driver = { .suppress_bind_attrs = true, }, .probe = funnel_probe, + .remove = funnel_remove, .id_table = funnel_ids, }; -builtin_amba_driver(funnel_driver); +module_amba_driver(funnel_driver); + +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("ARM Coresight Funnel Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index f1d0e21d8cab..335bca44b42d 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -64,7 +64,13 @@ static DEVICE_ATTR_RO(name) #define coresight_simple_reg64(type, name, lo_off, hi_off) \ __coresight_simple_func(type, NULL, name, lo_off, hi_off) -extern const u32 barrier_pkt[5]; +/* + * When losing synchronisation a new barrier packet needs to be inserted at the + * beginning of the data collected in a buffer. That way the decoder knows that + * it needs to look for another sync sequence. + */ +static const u32 barrier_pkt[5] = {0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff, 0x0}; enum etm_addr_type { ETM_ADDR_TYPE_NONE, @@ -143,7 +149,7 @@ struct list_head *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); void coresight_release_path(struct list_head *path); -#ifdef CONFIG_CORESIGHT_SOURCE_ETM3X +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) extern int etm_readl_cp14(u32 off, unsigned int *val); extern int etm_writel_cp14(u32 off, u32 val); #else diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 3756e71cb8f5..21278585b80f 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -41,6 +41,10 @@ static int replicator_enable(struct coresight_device *csdev, int inport, int outport) { struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct module *module = csdev->dev.parent->driver->owner; + + if (!try_module_get(module)) + return -ENODEV; dev_info(drvdata->dev, "REPLICATOR enabled\n"); return 0; @@ -50,7 +54,9 @@ static void replicator_disable(struct coresight_device *csdev, int inport, int outport) { struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct module *module = csdev->dev.parent->driver->owner; + module_put(module); dev_info(drvdata->dev, "REPLICATOR disabled\n"); } @@ -119,6 +125,15 @@ static int replicator_probe(struct platform_device *pdev) return ret; } +static int __exit replicator_remove(struct platform_device *pdev) +{ + struct replicator_drvdata *drvdata = dev_get_drvdata(&pdev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + #ifdef CONFIG_PM static int replicator_runtime_suspend(struct device *dev) { @@ -151,8 +166,11 @@ static const struct of_device_id replicator_match[] = { {} }; +MODULE_DEVICE_TABLE(of, replicator_match); + static struct platform_driver replicator_driver = { .probe = replicator_probe, + .remove = replicator_remove, .driver = { .name = "coresight-replicator", .of_match_table = replicator_match, @@ -160,4 +178,9 @@ static struct platform_driver replicator_driver = { .suppress_bind_attrs = true, }, }; -builtin_platform_driver(replicator_driver); +module_platform_driver(replicator_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("ARM Coresight Replicator Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 15e7ef3891f5..4a4a4e809cef 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -889,6 +889,17 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) return ret; } +static int __exit stm_remove(struct amba_device *adev) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + stm_unregister_device(&drvdata->stm); + + return 0; +} + #ifdef CONFIG_PM static int stm_runtime_suspend(struct device *dev) { @@ -929,6 +940,8 @@ static const struct amba_id stm_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, stm_ids); + static struct amba_driver stm_driver = { .drv = { .name = "coresight-stm", @@ -937,7 +950,12 @@ static struct amba_driver stm_driver = { .suppress_bind_attrs = true, }, .probe = stm_probe, + .remove = stm_remove, .id_table = stm_ids, }; -builtin_amba_driver(stm_driver); +module_amba_driver(stm_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index e2513b786242..971f04d1a5b4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -628,3 +628,5 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) return 0; } + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 68fbc8f7450e..77793bfce412 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -342,3 +342,5 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) return 0; } + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 0ea04f588de0..553885db2daa 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -437,6 +437,16 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) return ret; } +static int __exit tmc_remove(struct amba_device *adev) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); + + return 0; +} + static const struct amba_id tmc_ids[] = { { .id = 0x000bb961, @@ -461,6 +471,8 @@ static const struct amba_id tmc_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, tmc_ids); + static struct amba_driver tmc_driver = { .drv = { .name = "coresight-tmc", @@ -468,6 +480,11 @@ static struct amba_driver tmc_driver = { .suppress_bind_attrs = true, }, .probe = tmc_probe, + .remove = tmc_remove, .id_table = tmc_ids, }; -builtin_amba_driver(tmc_driver); +module_amba_driver(tmc_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 805f7c2210fe..6eff26f769a8 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -171,6 +171,15 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR_OR_ZERO(drvdata->csdev); } +static int __exit tpiu_remove(struct amba_device *adev) +{ + struct tpiu_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + + return 0; +} + #ifdef CONFIG_PM static int tpiu_runtime_suspend(struct device *dev) { @@ -214,6 +223,8 @@ static const struct amba_id tpiu_ids[] = { { 0, 0}, }; +MODULE_DEVICE_TABLE(amba, tpiu_ids); + static struct amba_driver tpiu_driver = { .drv = { .name = "coresight-tpiu", @@ -222,6 +233,12 @@ static struct amba_driver tpiu_driver = { .suppress_bind_attrs = true, }, .probe = tpiu_probe, + .remove = tpiu_remove, .id_table = tpiu_ids, }; -builtin_amba_driver(tpiu_driver); +module_amba_driver(tpiu_driver); + +MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("Arm CoreSight TPIU (Trace Port Interface Unit) driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 389c4baeca9d..5da8c3daba95 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -24,9 +24,32 @@ #include <linux/of_platform.h> #include <linux/delay.h> #include <linux/pm_runtime.h> +#include <linux/sched.h> #include "coresight-priv.h" +#ifdef CONFIG_PID_NS +unsigned long coresight_vpid_to_pid(unsigned long vpid) +{ + struct task_struct *task = NULL; + unsigned long pid = 0; + + rcu_read_lock(); + task = find_task_by_vpid(vpid); + if (task) + pid = task_pid_nr(task); + rcu_read_unlock(); + + return pid; +} +#else +unsigned long coresight_vpid_to_pid(unsigned long vpid) +{ + return vpid; +} +#endif +EXPORT_SYMBOL_GPL(coresight_vpid_to_pid); + static DEFINE_MUTEX(coresight_mutex); /** @@ -53,14 +76,6 @@ static DEFINE_PER_CPU(struct list_head *, tracer_path); */ static struct list_head *stm_path; -/* - * When losing synchronisation a new barrier packet needs to be inserted at the - * beginning of the data collected in a buffer. That way the decoder knows that - * it needs to look for another sync sequence. - */ -const u32 barrier_pkt[5] = {0x7fffffff, 0x7fffffff, - 0x7fffffff, 0x7fffffff, 0x0}; - static int coresight_id_match(struct device *dev, void *data) { int trace_id, i_trace_id; @@ -317,6 +332,7 @@ void coresight_disable_path(struct list_head *path) } } } +EXPORT_SYMBOL_GPL(coresight_disable_path); int coresight_enable_path(struct list_head *path, u32 mode) { @@ -368,6 +384,7 @@ int coresight_enable_path(struct list_head *path, u32 mode) coresight_disable_path(path); goto out; } +EXPORT_SYMBOL_GPL(coresight_enable_path); struct coresight_device *coresight_get_sink(struct list_head *path) { @@ -383,6 +400,7 @@ struct coresight_device *coresight_get_sink(struct list_head *path) return csdev; } +EXPORT_SYMBOL_GPL(coresight_get_sink); static int coresight_enabled_sink(struct device *dev, void *data) { @@ -407,6 +425,7 @@ static int coresight_enabled_sink(struct device *dev, void *data) return 0; } +EXPORT_SYMBOL_GPL(coresight_enabled_sink); /** * coresight_get_enabled_sink - returns the first enabled sink found on the bus @@ -429,6 +448,7 @@ struct coresight_device *coresight_get_enabled_sink(bool deactivate) return dev ? to_coresight_device(dev) : NULL; } +EXPORT_SYMBOL_GPL(coresight_get_enabled_sink); /** * _coresight_build_path - recursively build a path from a @csdev to a sink. @@ -508,6 +528,7 @@ struct list_head *coresight_build_path(struct coresight_device *source, return path; } +EXPORT_SYMBOL_GPL(coresight_build_path); /** * coresight_release_path - release a previously built path. @@ -532,6 +553,7 @@ void coresight_release_path(struct list_head *path) kfree(path); path = NULL; } +EXPORT_SYMBOL_GPL(coresight_release_path); /** coresight_validate_source - make sure a source has the right credentials * @csdev: the device structure for a source. @@ -948,6 +970,7 @@ int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) return -EAGAIN; } +EXPORT_SYMBOL_GPL(coresight_timeout); struct bus_type coresight_bustype = { .name = "coresight", @@ -959,6 +982,12 @@ static int __init coresight_init(void) } postcore_initcall(coresight_init); +static void __exit coresight_exit(void) +{ + bus_unregister(&coresight_bustype); +} +module_exit(coresight_exit); + struct coresight_device *coresight_register(struct coresight_desc *desc) { int i; @@ -1056,3 +1085,7 @@ void coresight_unregister(struct coresight_device *csdev) device_unregister(&csdev->dev); } EXPORT_SYMBOL_GPL(coresight_unregister); + +MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); +MODULE_DESCRIPTION("ARM Coresight Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index d950dad5056a..5863eb1a7335 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -243,7 +243,7 @@ struct coresight_ops { const struct coresight_ops_source *source_ops; }; -#ifdef CONFIG_CORESIGHT +#if IS_ENABLED(CONFIG_CORESIGHT) extern struct coresight_device * coresight_register(struct coresight_desc *desc); extern void coresight_unregister(struct coresight_device *csdev); @@ -274,24 +274,5 @@ static inline struct coresight_platform_data *of_get_coresight_platform_data( struct device *dev, const struct device_node *node) { return NULL; } #endif -#ifdef CONFIG_PID_NS -static inline unsigned long -coresight_vpid_to_pid(unsigned long vpid) -{ - struct task_struct *task = NULL; - unsigned long pid = 0; - - rcu_read_lock(); - task = find_task_by_vpid(vpid); - if (task) - pid = task_pid_nr(task); - rcu_read_unlock(); - - return pid; -} -#else -static inline unsigned long -coresight_vpid_to_pid(unsigned long vpid) { return vpid; } -#endif - +extern unsigned long coresight_vpid_to_pid(unsigned long vpid); #endif -- 2.17.0

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