CoreSight

coresight@lists.linaro.org

6 participants
2571 discussions

[PATCH v7 0/9] coresight: syscfg: Add configuration table load

by Mike Leach

This set extends the configuration management support to allow loading and unloading of configurations as structured tables. The existing coresight configuration configfs API is additionally extended to use this table functionality to load and unload configuration tables as binary files. This allows coresight configurations to be loaded at runtime, and independently of kernel version, without the requirement to re-compile as built in kernel modules. Loading configurations in this way provides a method for atomically programming the trace control elements (e.g. filters and triggers) of multiple connected CoreSight components as a single system for a trace session when selected on the command line both when running trace via perf or running trace via sysfs. All configuration are validated at load time as being compatible with the CoreSight system in use. Additional load and unload attributes are provided in the /config/cs-syscfg subsytem base group to implement the load functionality. Routines to generate configuration tables are supplied in ./tools/coresight. Example generator and reader applications are provided. Tools may be cross compiled or built for use on host system. Documentation is updated to describe feature usage. Changes since v6: 1) Rebased to coresight/next - 6.12-rc4 2) Adjusted patches to split the load/unload API from the configfs attribute declarations 3) As unload order is strictly enforced to ensure dependencies are not broken, unload is now a simple write to attribute to automatically unload the last loaded configuration without need for name of configuration. Changes since v5: 1) Possible memory leak removed. Reported-by: kernel test robot. Reported-by: Dan Carpenter 2) Reuse mechanism for reader code revised. (Christoph) 3) Unload mechnism now by name in standard attribute, rather than entire file 4) Mechanism to check last loaded configuration can be unloaded. 5) Documentation updates. Changes since v4: 1) Update coresight/next - 6.1-rc3 2) Update to lockdep fixes to avoid read lock race in configfs. Changes since v3: 1) Rebase & tested on coresight/next - 5.19-rc3 - which includes the fix patch for earlier configfs works. 2) Lockdep investigations resulted in re-design of some of the code accessing configfs. 3) moved load and unload attributes to root of cs-syscfg. (Mathieu) 4) Additional minor fixes suggested by Mathieu. 5) Memory for configfs loaded and unloaded configurations is now explicitly freed. 6) LOCKDEP nesting fix for configfs base code (fs/configfs/dir.c) Changes since v2: 1) Rebased & tested on coresight/next - 5.18-rc2 2) Moved coresight config generator and reader programs from samples to tools/coresight. Docs updated to match. (suggested by Mathieu) 3) userspace builds now use userspace headers from tools/... 4) Other minor fixes from Mathieu's review. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (9): coresight: config: Add configuration table processing funtionality coresight: configfs: Update memory allocation / free for configfs elements coresight: config: API to dynamically load / unload config tables coresight: configfs: Add static type for config attributes coresight: configfs: Add attributes for unload operations coresight: configfs: Add attribute to load a configuration table coresight: config: extract shared structures to common header file coresight: tools: Add configuration table test tools Documentation: coresight: Docs for configuration table load .../trace/coresight/coresight-config.rst | 287 ++++++++- MAINTAINERS | 1 + drivers/hwtracing/coresight/Makefile | 3 +- .../coresight/coresight-config-desc.h | 105 ++++ .../coresight/coresight-config-table.c | 431 +++++++++++++ .../coresight/coresight-config-table.h | 151 +++++ .../hwtracing/coresight/coresight-config.h | 98 +-- .../coresight/coresight-syscfg-configfs.c | 577 ++++++++++++++++-- .../hwtracing/coresight/coresight-syscfg.c | 103 +++- .../hwtracing/coresight/coresight-syscfg.h | 19 +- tools/coresight/Makefile | 56 ++ tools/coresight/coresight-cfg-bufw.c | 328 ++++++++++ tools/coresight/coresight-cfg-bufw.h | 26 + tools/coresight/coresight-cfg-example1.c | 62 ++ tools/coresight/coresight-cfg-example2.c | 95 +++ tools/coresight/coresight-cfg-examples.h | 25 + tools/coresight/coresight-cfg-file-gen.c | 58 ++ tools/coresight/coresight-cfg-file-gen.h | 17 + tools/coresight/coresight-cfg-file-read.c | 239 ++++++++ tools/coresight/coresight-config-uapi.h | 105 ++++ 20 files changed, 2644 insertions(+), 142 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-desc.h create mode 100644 drivers/hwtracing/coresight/coresight-config-table.c create mode 100644 drivers/hwtracing/coresight/coresight-config-table.h create mode 100644 tools/coresight/Makefile create mode 100644 tools/coresight/coresight-cfg-bufw.c create mode 100644 tools/coresight/coresight-cfg-bufw.h create mode 100644 tools/coresight/coresight-cfg-example1.c create mode 100644 tools/coresight/coresight-cfg-example2.c create mode 100644 tools/coresight/coresight-cfg-examples.h create mode 100644 tools/coresight/coresight-cfg-file-gen.c create mode 100644 tools/coresight/coresight-cfg-file-gen.h create mode 100644 tools/coresight/coresight-cfg-file-read.c create mode 100644 tools/coresight/coresight-config-uapi.h -- 2.25.1

11 months, 4 weeks

Re: [PATCH v2 0/9] coresight: change some driver' spinlock type to raw_spinlock_t

by Mike Leach

This change seems to omit devices: etm3x - which provides support for ETMv3 and PTM, both of which are valid trace sources in the cs_etm handling code. stm - can be integrated into the kernel STM via configfs providing a MIPI source for ftrace. Mike On Tue, 3 Dec 2024 at 11:49, Yeoreum Yun <yeoreum.yun(a)arm.com> wrote: > > In some coresight drivers, drvdata->spinlock can be held during __schedule() > by perf_event_task_sched_out()/in(). > > Since drvdata->spinlock type is spinlock_t and > perf_event_task_sched_out()/in() is called after acquiring rq_lock, > which is raw_spinlock_t (an unsleepable lock), > this poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable. > > To address this,change type drvdata->spinlock in some coresight drivers, > which can be called by perf_event_task_sched_out()/in(), > from spinlock_t to raw_spinlock_t. > > Reviewed-by: James Clark <james.clark(a)linaro.org> > > v1 to v2: > - seperate patchsets to change locktype and apply gurad API. > > Levi Yun (9): > coresight: change coresight_device lock type to raw_spinlock_t > coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t > coresight: change coresight_trace_id_map's lock type to raw_spinlock_t > coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t > coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t > coresight-funnel: change funnel_drvdata spinlock's type to > raw_spinlock_t > coresight-replicator: change replicator_drvdata spinlock's type to > raw_spinlock_t > coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t > coresight/ultrasoc: change cti_drvdata spinlock's type to > raw_spinlock_t > > .../hwtracing/coresight/coresight-config.c | 21 +- > .../hwtracing/coresight/coresight-config.h | 2 +- > drivers/hwtracing/coresight/coresight-core.c | 2 +- > .../hwtracing/coresight/coresight-cti-core.c | 65 +- > .../hwtracing/coresight/coresight-cti-sysfs.c | 135 +++-- > drivers/hwtracing/coresight/coresight-cti.h | 2 +- > drivers/hwtracing/coresight/coresight-etb10.c | 62 +- > .../coresight/coresight-etm4x-core.c | 71 ++- > .../coresight/coresight-etm4x-sysfs.c | 566 +++++++++--------- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- > .../hwtracing/coresight/coresight-funnel.c | 34 +- > .../coresight/coresight-replicator.c | 36 +- > .../hwtracing/coresight/coresight-syscfg.c | 75 ++- > .../hwtracing/coresight/coresight-tmc-core.c | 9 +- > .../hwtracing/coresight/coresight-tmc-etf.c | 195 +++--- > .../hwtracing/coresight/coresight-tmc-etr.c | 199 +++--- > drivers/hwtracing/coresight/coresight-tmc.h | 2 +- > .../hwtracing/coresight/coresight-trace-id.c | 93 ++- > drivers/hwtracing/coresight/ultrasoc-smb.c | 12 +- > drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- > include/linux/coresight.h | 4 +- > 21 files changed, 751 insertions(+), 838 deletions(-) > > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

11 months, 4 weeks

Re: [PATCH v6 1/2] dt-bindings: arm: Add label in the coresight components

by Mike Leach

On Wed, 18 Dec 2024 at 09:21, Krzysztof Kozlowski <krzk(a)kernel.org> wrote: > > On Tue, Dec 17, 2024 at 02:33:23PM +0800, Mao Jinlong wrote: > > Current name of coresight component's folder consists of prefix of > > the device and the id in the device list. When run 'ls' command, > > we can get the register address of the device. Take CTI for example, > > if we want to set the config for modem CTI, but we can't know which > > CTI is modem CTI from all current information. > > > > cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 > > cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 > > > > Add label to show hardware context information of each coresight > > device. There will be a sysfs node label in each device folder. > > > > cat /sys/bus/coresight/devices/cti_sys0/label > > > > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > > Best regards, > Krzysztof > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

11 months, 4 weeks

[PATCH v2 0/3] Add support to configure TPDM MCMB subunit

by Mao Jinlong

Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB subunit has the same number and usage of registers as CMB subunit. Just like the CMB subunit, the MCMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the MCMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports MCMB subunit. All sysfs files of CMB subunit TPDM are included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will have new sysfs files to select and enable the lane. Changes in V2: 1. Use tdpm_data->cmb instead of (tpdm_has_cmb_dataset(tpdm_data) || tpdm_has_mcmb_dataset(tpdm_data)) for cmb dataset support. 2. Embed mcmb_dataset struct into cmb struct. 3. Update the date and version in sysfs-bus-coresight-devices-tpdm Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM .../testing/sysfs-bus-coresight-devices-tpdm | 15 +++ drivers/hwtracing/coresight/coresight-tpda.c | 7 +- drivers/hwtracing/coresight/coresight-tpdm.c | 124 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 33 +++-- 4 files changed, 158 insertions(+), 21 deletions(-) -- 2.17.1

12 months

[PATCH v7 0/4] source filtering for multi-port output

by Tao Zhang

In our hardware design, by combining a funnel and a replicator, it implement a hardware device with one-to-one correspondence between output ports and input ports. The programming usage on this device is the same as funnel. The software uses a funnel and a static replicator to implement the driver of this device. Since original funnels only support a single output connection and original replicator only support a single input connection, the code needs to be modified to support this new feature. The following is a typical topology diagram of multi-port output mechanism. |----------| |---------| |----------| |---------| | TPDM 0 | | Source0 | | Source 1 | | TPDM 1 | |----------| |---------| |----------| |---------| | | | | | | | | | --------- | | | | | | | | | | | | | | | \-------------/ ---------------------- | \ Funnel 0 / | | ----------- | ------------------------------ | | | | | | \------------------/ \ Funnel 1 / ----| \--------------/ | | |----> Combine a funnel and a | | static replicator /-----------------\ | / replicator 0 \ ----| /---------------------\ | | | | | |-----------| | |---------| | | |TPDM0 |TPDM1 | \-----------------/ | \ TPDA 0 / | \-------------/ | | | | |Source0/1 | \-------------------------------/ \ Funnel 2 / \---------------------------/ Changes in V7: 1. Correct the use of incorrect characters. -- Suzuki K Poulose 2. Rebase the series on v6.13-rc1 -- Suzuki K Poulose Changes in V6: 1. Optimize the prompt content of the warning log when the filter handle is not a trace source. -- Suzuki K Poulose 2. Reset the filter device and fwnode if it is not a trace source. -- Suzuki K Poulose Changes in V5: 1. Replace "filter-src" with "filter-source" in the dt-binding document. -- Suzuki K Poulose 2. Optimize the comments of the patch "coresight: Add support for trace filtering by source" due to bad example. -- Suzuki K Poulose 3. Correct spelling errors in the patch "coresight: Add support for trace filtering by source". -- Suzuki K Poulose 4. Optimize the function "coresight_blocks_source". -- Suzuki K Poulose 5. Add { } in the function "of_coresight_parse_endpoint". -- Suzuki K Poulose 6. Adjust the order of the patches. -- Suzuki K Poulose 7. Adjust the alignment in "coresight-platform.c". -- Suzuki K Poulose Changes in V4: 1. Use "coresight_get_source(path)" in the function "coresight_disable_path_from" instead of explicitly passing the source. -- Suzuki K Poulose 2. Optimize the order of the input parameters for "_coresight_build_path". -- Suzuki K Poulose 3. Reuse the method "coresight_block_source" in "_coresight_build_path". -- Suzuki K Poulose 4. Remove the unnecessary () in "coresight_build_path". -- Suzuki K Poulose 5. Add a helper to check if a device is SOURCE. -- Suzuki K Poulose 6. Adjust the posistion of setting "still_orphan" in "coresight_build_path". -- Suzuki K Poulose Changes in V3: 1. Rename the function "coresight_source_filter" to "coresight_block_source". And refine this function. -- Suzuki K Poulose 2. Rename the parameters of the function "coresight_find_out_connection" to avoid confusion. -- Suzuki K Poulose 3. Get the source of path in "coresight_enable_path" and "coresight_disable_path". -- Suzuki K Poulose 4. Fix filter source device before skip the port in "coresight_orphan_match". -- Suzuki K Poulose 5. Make sure the device still orphan if whter is a filter source firmware node but the filter source device is null. -- Suzuki K Poulose 6. Walk through the entire coresight bus and fixup the "filter_src_dev" if the source is being removed. -- Suzuki K Poulose 7. Refine the commit description of patch#2. -- Suzuki K Poulose 8. Fix the warning reported by kernel test robot. -- kernel test robot. 9. Use the source device directly if the port has a hardcoded filter in "tpda_get_element_size". -- Suzuki K Poulose Changes in V2: 1. Change the reference for endpoint property in dt-binding. -- Krzysztof Kozlowski 2. Change the property name "filter_src" to "filter-src". -- Krzysztof Kozlowski 3. Fix the errors in running 'make dt_binding_check'. -- Rob Herring 4. Pass in the source parameter instead of path. -- Suzuki K Poulose 5. Reset the "filter_src_dev" if the "src" csdev is being removed. -- Suzuki K Poulose 6. Add a warning if the "filter_src_dev" is of not the type DEV_TYPE_SOURCE. -- Suzuki K Poulose 7. Optimize the procedure for handling all possible cases. -- Suzuki K Poulose Changes in V1: 1. Add a static replicator connect to a funnel to implement the correspondence between the output ports and the input ports on funnels. -- Suzuki K Poulose 2. Add filter_src_dev and filter_src_dev phandle to "coresight_connection" struct, and populate them if there is one. -- Suzuki K Poulose 3. To look at the phandle and then fixup/remove the filter_src device in fixup/remove connections. -- Suzuki K Poulose 4. When TPDA reads DSB/CMB element size, it is implemented by looking up filter src device in the connections. -- Suzuki K Poulose Tao Zhang (4): dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering coresight: Add a helper to check if a device is source coresight: Add support for trace filtering by source coresight-tpda: Optimize the function of reading element size .../arm/arm,coresight-static-replicator.yaml | 19 ++- drivers/hwtracing/coresight/coresight-core.c | 113 +++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 21 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 13 +- include/linux/coresight.h | 12 +- 5 files changed, 155 insertions(+), 23 deletions(-) -- 2.17.1

12 months

[PATCH v2 0/3] Extend logging on TMC start / stop errors

by Mike Leach

Extend logging on TMC start / stop errors Recent issues with trying to debug TMC timeouts and flush issues shows a general lack of logging and context around the possible errors Add logging to general wait for stop coresight routines and return values of watched registers. Update TMC to use this logging. Changes since v1: Rebase to coresight/next (kernel 6.13-rc2) Mike Leach (3): coresight: Update timeout functions to allow return of test register value coresight: tmc: Update error logging in tmc common functions coresight: etf: etr: Update logging around flush_and_stop() errors drivers/hwtracing/coresight/coresight-core.c | 50 +++++++++++++++---- .../hwtracing/coresight/coresight-tmc-core.c | 37 +++++++++++--- .../hwtracing/coresight/coresight-tmc-etf.c | 12 +++-- .../hwtracing/coresight/coresight-tmc-etr.c | 8 ++- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- include/linux/coresight.h | 2 + 6 files changed, 86 insertions(+), 25 deletions(-) -- 2.25.1

12 months

[PATCH v1 0/2] Add Qualcomm extended CTI support

by Mao Jinlong

The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Mao Jinlong (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 14 ++ .../hwtracing/coresight/coresight-cti-core.c | 75 +++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 124 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 123 +++++++++++------ 5 files changed, 253 insertions(+), 99 deletions(-) -- 2.41.0

12 months

[PATCH] selftests: arm coresight: sysfsmode testing

by Linu Cherian

Add sysfs mode selftest for ARM Coresight hardware tracer. Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- .../drivers/hwtracing/coresight/Makefile | 5 + .../hwtracing/coresight/sysfs_test_trace.sh | 144 ++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 tools/testing/selftests/drivers/hwtracing/coresight/Makefile create mode 100755 tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/Makefile b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile new file mode 100644 index 000000000000..7dc68ae1c0a9 --- /dev/null +++ b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +TEST_PROGS = sysfs_test_trace.sh + +include ../../../lib.mk diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh new file mode 100755 index 000000000000..0d6307fff1d2 --- /dev/null +++ b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh @@ -0,0 +1,144 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2024 Marvell. + +# Test Arm CoreSight trace capture in sysfs mode +# Based on tools/perf/tests/shell/test_arm_coresight.sh + +glb_err=0 + +arm_cs_report() { + if [ $2 != 0 ]; then + echo "$1: FAIL" + glb_err=$2 + else + echo "$1: PASS" + fi +} + +is_device_sink() { + # If the node of "enable_sink" is existed under the device path, this + # means the device is a sink device. + + if [ -e "$1/enable_sink" ]; then + + return 0 + else + return 1 + fi +} + +# Configure sink for buffer mode +cfg_sink_buf_mode() { + sink_dev=$1 + mode=$2 + # Set buffer mode if supported + if [ -e "$sink_dev/buf_modes_available" ]; then + cat $sink_dev/buf_modes_available | grep -E -q $mode + if [ $? -eq 0 ]; then + echo $mode > $sink_dev/buf_mode_preferred + return 0 + fi + fi + + return 1 +} + +run_app() { + + taskset -c $1 dd if=/dev/urandom of=/dev/null bs=1M count=64 +} + +sysfs_trace() { + src_dev=$1 + sink_dev=$2 + cpu=$3 + + # Enable sink device + echo 1 > $sink_dev/enable_sink + # Enable source device + echo 1 > $src_dev/enable_source + + # Run app to be traced + run_app $cpu + + # Read back trace data + dd if=/dev/$sink_dev_name of=/tmp/tracedata + + # Verify if read is successful + err=$? + + # Disable source device + echo 0 > $src_dev/enable_source + + # Diskable sink device + echo 0 > $sink_dev/enable_sink + + arm_cs_report "CoreSight path testing (CPU$cpu -> $sink_dev_name)" $err +} + +try_sysfs_trace_resrv_buf() { + src_dev=$1 + sink_dev=$2 + cpu=$3 + + # Configure the resrved buffer mode if available + cfg_sink_buf_mode $sink_dev "resrv" + if [ $? -eq 0 ]; then + echo "Running sysfs trace with resrv buf mode" + sysfs_trace $src_dev $sink_dev $cpu + # Restore buffer mode + cfg_sink_buf_mode $sink_dev "auto" + if [ $? -eq 1 ]; then + echo "Failed to restore default buf mode" + fi + fi +} + +arm_cs_iterate_devices() { + src_dev=$1 + cpu=$3 + for cdev in $2/connections/out\:*; do + + # Skip testing if it's not a directory + ! [ -d $cdev ] && continue; + + # Read out its symbol link file name + sink_dev=`readlink -f $cdev` + + # Extract device name from path, e.g. + # sink_dev = '/sys/devices/platform/20010000.etf/tmc_etf0' + # `> sink_dev_name = 'tmc_etf0' + sink_dev_name=$(basename $sink_dev) + + if is_device_sink $sink_dev; then + # Run trace with resrv buf mode (if available) + try_sysfs_trace_resrv_buf $src_dev $sink_dev $cpu + + # Run the default mode + echo "Running sysfs trace with default settings" + sysfs_trace $src_dev $sink_dev $cpu + fi + + arm_cs_iterate_devices $src_dev $cdev $cpu + + done +} + +arm_cs_etm_traverse_path_test() { + # Iterate for every ETM device + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do + # Canonicalize the path + dev=`readlink -f $dev` + + # Find the ETM device belonging to which CPU + cpu=`cat $dev/cpu` + + # Use depth-first search (DFS) to iterate outputs + arm_cs_iterate_devices $dev $dev $cpu + done +} + +arm_cs_etm_traverse_path_test + +exit $glb_err -- 2.34.1

12 months

Re: [PATCH] selftests: arm coresight: sysfsmode testing

by Linu Cherian

Hi, On 2024-12-04 at 05:53:56, Shuah Khan (skhan(a)linuxfoundation.org) wrote: > On 11/29/24 01:38, Linu Cherian wrote: > > Add sysfs mode selftest for ARM Coresight hardware tracer. > > Please add details on what this test does in here. Include > the output from the test? Ack. Will add test descripion here. > > Does this test have dependencies on config? If it does, does > this test detect and skip if config isn't enabled? Will add dependency. Thanks. > > > > > Signed-off-by: Linu Cherian <lcherian(a)marvell.com> > > --- > > .../drivers/hwtracing/coresight/Makefile | 5 + > > .../hwtracing/coresight/sysfs_test_trace.sh | 144 ++++++++++++++++++ > > 2 files changed, 149 insertions(+) > > create mode 100644 tools/testing/selftests/drivers/hwtracing/coresight/Makefile > > create mode 100755 tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh > > > > diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/Makefile b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile > > new file mode 100644 > > index 000000000000..7dc68ae1c0a9 > > --- /dev/null > > +++ b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile > > @@ -0,0 +1,5 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > + > > +TEST_PROGS = sysfs_test_trace.sh > > + > > +include ../../../lib.mk > > diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh > > new file mode 100755 > > index 000000000000..0d6307fff1d2 > > --- /dev/null > > +++ b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh > > @@ -0,0 +1,144 @@ > > +#!/bin/sh > > +# SPDX-License-Identifier: GPL-2.0 > > +# Copyright (C) 2024 Marvell. > > + > > +# Test Arm CoreSight trace capture in sysfs mode > > +# Based on tools/perf/tests/shell/test_arm_coresight.sh > > + > > +glb_err=0 > > + > > +arm_cs_report() { > > + if [ $2 != 0 ]; then > > + echo "$1: FAIL" > > + glb_err=$2 > > + else > > + echo "$1: PASS" > > + fi > > +} > > + > > +is_device_sink() { > > + # If the node of "enable_sink" is existed under the device path, this > > + # means the device is a sink device. > > + > > + if [ -e "$1/enable_sink" ]; then > > + > > + return 0 > > + else > > + return 1 > > + fi > > +} > > + > > +# Configure sink for buffer mode > > +cfg_sink_buf_mode() { > > + sink_dev=$1 > > + mode=$2 > > + # Set buffer mode if supported > > + if [ -e "$sink_dev/buf_modes_available" ]; then > > + cat $sink_dev/buf_modes_available | grep -E -q $mode > > + if [ $? -eq 0 ]; then > > + echo $mode > $sink_dev/buf_mode_preferred > > + return 0 > > + fi > > + fi > > + > > + return 1 > > +} > > + > > +run_app() { > > + > > + taskset -c $1 dd if=/dev/urandom of=/dev/null bs=1M count=64 > > +} > > + > > +sysfs_trace() { > > + src_dev=$1 > > + sink_dev=$2 > > + cpu=$3 > > + > > + # Enable sink device > > + echo 1 > $sink_dev/enable_sink > > + # Enable source device > > + echo 1 > $src_dev/enable_source > > + > > + # Run app to be traced > > + run_app $cpu > > + > > + # Read back trace data > > + dd if=/dev/$sink_dev_name of=/tmp/tracedata > > + > > + # Verify if read is successful > > + err=$? > > + > > + # Disable source device > > + echo 0 > $src_dev/enable_source > > + > > + # Diskable sink device > > + echo 0 > $sink_dev/enable_sink > > + > > + arm_cs_report "CoreSight path testing (CPU$cpu -> $sink_dev_name)" $err > > +} > > + > > +try_sysfs_trace_resrv_buf() { > > + src_dev=$1 > > + sink_dev=$2 > > + cpu=$3 > > + > > + # Configure the resrved buffer mode if available > > + cfg_sink_buf_mode $sink_dev "resrv" > > + if [ $? -eq 0 ]; then > > + echo "Running sysfs trace with resrv buf mode" > > + sysfs_trace $src_dev $sink_dev $cpu > > + # Restore buffer mode > > + cfg_sink_buf_mode $sink_dev "auto" > > + if [ $? -eq 1 ]; then > > + echo "Failed to restore default buf mode" > > + fi > > + fi > > +} > > + > > +arm_cs_iterate_devices() { > > + src_dev=$1 > > + cpu=$3 > > + for cdev in $2/connections/out\:*; do > > + > > + # Skip testing if it's not a directory > > + ! [ -d $cdev ] && continue; > > + > > + # Read out its symbol link file name > > + sink_dev=`readlink -f $cdev` > > + > > + # Extract device name from path, e.g. > > + # sink_dev = '/sys/devices/platform/20010000.etf/tmc_etf0' > > + # `> sink_dev_name = 'tmc_etf0' > > + sink_dev_name=$(basename $sink_dev) > > + > > + if is_device_sink $sink_dev; then > > + # Run trace with resrv buf mode (if available) > > + try_sysfs_trace_resrv_buf $src_dev $sink_dev $cpu > > + > > + # Run the default mode > > + echo "Running sysfs trace with default settings" > > + sysfs_trace $src_dev $sink_dev $cpu > > + fi > > + > > + arm_cs_iterate_devices $src_dev $cdev $cpu > > + > > + done > > +} > > + > > +arm_cs_etm_traverse_path_test() { > > + # Iterate for every ETM device > > + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do > > + # Canonicalize the path > > + dev=`readlink -f $dev` > > + > > + # Find the ETM device belonging to which CPU > > + cpu=`cat $dev/cpu` > > + > > + # Use depth-first search (DFS) to iterate outputs > > + arm_cs_iterate_devices $dev $dev $cpu > > + done > > +} > > + > > +arm_cs_etm_traverse_path_test > > + > > +exit $glb_err > > thanks, > -- Shuah >

12 months

Re: [PATCH v2] coresight-etm4x: add isb() before reading the TRCSTATR

by Yuanfang Zhang

On 12/4/2024 11:16 PM, Leo Yan wrote: > Hi Yuanfang, > > Recently I just acrossed this part, so some comments. > > On Wed, Dec 04, 2024 at 07:23:32PM +0800, yuanfang zhang wrote: >> >> From: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >> >> As recommended by section 4.3.7 ("Synchronization when using system >> instructions to progrom the trace unit") of ARM IHI 0064H.b, the >> self-hosted trace analyzer must perform a Context synchronization >> event between writing to the TRCPRGCTLR and reading the TRCSTATR. >> >> Fixes: ebddaad09e10 ("coresight: etm4x: Add missing single-shot control API to sysfs") >> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >> --- >> Change in V2: >> Added comments in the code. >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 66d44a404ad0..decb3a87e27e 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -906,6 +906,13 @@ static void etm4_disable_hw(void *info) >> tsb_csync(); >> etm4x_relaxed_write32(csa, control, TRCPRGCTLR); >> >> + /* >> + * As recommended by section 4.3.7 ("Synchronization when using system >> + * instructions to progrom the trace unit") of ARM IHI 0064H.b, the >> + * self-hosted trace analyzer must perform a Context synchronization >> + * event between writing to the TRCPRGCTLR and reading the TRCSTATR. >> + */ >> + isb(); > > As described in the doc, the "isb" is only required for system > instructions case. It is good to only apply the ISB on system > register case: > > if (!csa->io_mem) > isb(); > updated in PATCH V3. >> /* wait for TRCSTATR.PMSTABLE to go to '1' */ >> if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) >> dev_err(etm_dev, > > As mentioned in system register case: "Arm recommends that the > self-hosted trace analyzer always executes an ISB instruction after > programming the trace unit registers, to ensure that all updates are > committed to the trace unit before normal code execution resumes." > > And for MMIO case: > > "When the memory is marked as Device-nGnRE or stronger. > ... > - Poll TRCSTATR to ensure the previous write has completed. > — Execute an ISB operation." > > Thus we need to add an ISB after polling. > > isb(); > updated in PATCH V3. > For consistent behaviour, a relevant thing is the dsb(sy) in > etm4_enable_hw(). I do not think the dsb(sy) is necessary, as the > driver uses the sequence "write TRCPRGCTLR + polling TRCSTATR" to > ensure the data has been populated to trace unit, the polling > operations somehow act as a read back. And the ETM manual does not > mention the requirement for DSB when enabling trace unit. Thus, we > should remove dsb(sy) (maybe use a separte patch). > updated in PATCH V3. > Mike / Suzuki / James, please confirm if my conclusions are valid. > > Thanks, > Leo

1 year

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight