CoreSight

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2378 discussions

Re: [PATCH v4 1/4] devres: Provide krealloc_array

by Suzuki K Poulose

On 01/06/2023 10:33, Greg KH wrote: > On Wed, May 31, 2023 at 11:44:55PM +0100, Suzuki K Poulose wrote: >> (Removed irrelevant recipients), +Cc: coresight ml >> >> Hi Greg, >> >> On 15/05/2023 12:55, Greg KH wrote: >>> On Mon, May 15, 2023 at 08:55:33AM +0100, James Clark wrote: >>>> >>>> >>>> On 13/05/2023 12:04, Greg KH wrote: >>>>> On Tue, May 09, 2023 at 10:49:38AM +0100, James Clark wrote: >>>>>> There is no krealloc_array equivalent in devres. Users would have to >>>>>> do their own multiplication overflow check so provide one. >>>>>> >>>>>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> >>>>>> Signed-off-by: James Clark <james.clark(a)arm.com> >>>>>> --- >>>>>> Documentation/driver-api/driver-model/devres.rst | 1 + >>>>>> include/linux/device.h | 11 +++++++++++ >>>>>> 2 files changed, 12 insertions(+) >> >> ... >> >>>> Maybe something could be done with some macro magic, but it would >>>> probably end up being worse than just copying them and would affect the >>>> real ones as well. So yeah I can't think of any easy gains either. >>> >>> Ok, that's good. Given a lack of objections from others, I'll just take >>> this through my driver core tree in a few days. >> >> Apologies for hijacking the thread. We have a series for CoreSight[1] >> that depends on this series, which I see that, is queued in your >> driver-core-next. >> >> I would like to queue [1] for the next version (as there are other >> work that depend on this, e.g., [2]). Do you have any >> recommendations/comments on the proposal ? Are you able to share a >> stable branch which can be merged to coresight/next and queue the >> series ontop ? (PS: I haven't queued anything for coresight/next yet). > > You can pull from my driver-core-next branch just fine and assume it > will be stable. So just pull in that one commit and all should be good > in the future. Thanks Greg, I will give it a go Suzuki > > thanks, > > greg k-h

2 years

[RFC PATCH] coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE

by Suzuki K Poulose

All, This is an RFC patch to allow all ETM4 instances to be detected via AMBA driver without having to add the PIDs to the list. The AMBA driver already supports checking the DEVTYPE and DEVARCH registers for CoreSight components. This patch adds a pid,mask value that is bound to match all PIDs (with PIDR2.JEDEC field mandated to be RA0). With this patch, we wouldn't need to add the PIDs for newer CPUs to be able to use them. An entry in the device tree is all we need. The only side effect of this patch is : If a DT description exists for an ETM and the CPU ETM has an erratum, the driver may still probe it and use it. But then the DT shouldn't have described it in the first place. Thoughts? Suzuki ---8>--- coresight: etm4x: Match all ETM4 instances based on DEVARCH Instead of adding the PIDs forever to the list for the new CPUs, let us detect a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always. Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: frowand.list(a)gmail.com Cc: linux(a)armlinux.org.uk Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- .../coresight/coresight-etm4x-core.c | 5 +++++ drivers/hwtracing/coresight/coresight-priv.h | 19 +++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4c15fae534f3..8a2e24d5686a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2260,6 +2260,11 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ + /* + * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new + * CPUs to the list here. + */ + CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), {}, }; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 595ce5862056..72ec36c9232c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void); } /* coresight AMBA ID, full UCI structure: id table entry. */ -#define CS_AMBA_UCI_ID(pid, uci_ptr) \ +#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \ { \ .id = pid, \ - .mask = 0x000fffff, \ + .mask = m, \ .data = (void *)uci_ptr \ } +#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci) +/* + * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the + * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that + * as a match value for blanket matching all devices in the given CoreSight + * device type and architecture. + */ +#define PIDR2_JEDEC BIT(3) +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) +/* + * Match all PIDs in a given CoreSight device type and architecture, defined + * by the uci. + */ +#define CS_AMBA_MATCH_ALL_UCI(uci) \ + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id) -- 2.34.1

2 years

[PATCH V2 00/14] arm64/sysreg: Convert TRBE registers to automatic generation

by Anshuman Khandual

This series converts TRBE registers to automatic generation, after renaming their fields as per the auto-gen tools format. Although the following field still renames in arch/arm64/include/asm/sysreg.h, as it cannot be converted (shares bits with other fields) in the tools format. #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 This series applies on v6.4-rc4. Changes in V2: - Renamed each individual TRBE register fields as per auto-gen tools - Converted each individual TRBE registers as per auto-gen tools - Added new register fields as per DDI0601 2023-03 Changes in V1: https://lore.kernel.org/all/20230531055524.16562-1-anshuman.khandual@arm.co… Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Marc Zyngier <maz(a)kernel.org> Cc: Mark Brown <broonie(a)kernel.org> Cc: Rob Herring <robh(a)kernel.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: James Morse <james.morse(a)arm.com> Cc: kvmarm(a)lists.linux.dev Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Anshuman Khandual (14): arm64/sysreg: Rename TRBLIMITR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBBASER_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBSR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBTRG_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBIDR_EL1 fields per auto-gen tools format arm64/sysreg: Convert TRBLIMITR_EL1 register to automatic generation arm64/sysreg: Convert TRBPTR_EL1 register to automatic generation arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation arm64/sysreg: Convert TRBSR_EL1 register to automatic generation arm64/sysreg: Convert TRBMAR_EL1 register to automatic generation arm64/sysreg: Convert TRBTRG_EL1 register to automatic generation arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 50 +-------------- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- arch/arm64/tools/sysreg | 64 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.c | 33 +++++----- drivers/hwtracing/coresight/coresight-trbe.h | 38 +++++------- 7 files changed, 101 insertions(+), 90 deletions(-) -- 2.25.1

2 years

Re: [PATCH v4 00/11] Add support to configure TPDM DSB subunit

by Tao Zhang

On 5/23/2023 3:50 PM, Tao Zhang wrote: > On 4/28/2023 12:53 AM, Suzuki K Poulose wrote: >> On 27/04/2023 10:00, Tao Zhang wrote: >>> Introduction of TPDM DSB subunit >>> DSB subunit is responsible for creating a dataset element, and is also >>> optionally responsible for packing it to fit multiple elements on a >>> single ATB transfer if possible in the configuration. The TPDM Core >>> Datapath requests timestamps be stored by the TPDA and then delivering >>> ATB sized data (depending on ATB width and element size, this could >>> be smaller or larger than a dataset element) to the ATB Mast FSM. >>> >>> The DSB subunit must be configured prior to enablement. This series >>> adds support for TPDM to configure the configure DSB subunit. >>> >>> Once this series patches are applied properly, the new tpdm nodes for >>> should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* >>> which supports DSB subunit. >>> e.g. >>> /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts >>> -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type >>> >>> We can use the commands are similar to the below to configure the >>> TPDMs which support DSB subunit. Enable coresight sink first. >>> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink >>> echo 1 > /sys/bus/coresight/devices/tpdm0/reset >>> echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask >>> echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl >>> echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts >>> echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type >>> echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts >>> echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask >>> echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val >>> >>> This patch series depends on patch series "[PATCH v2 0/9] coresight: >>> Fix CTI module refcount leak by making it a helper device" >>> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230425143542.… >>> >> >> There is v6 available for the above and there may be changes in the data >> structures. But the series is stable now, and may be you could cordinate >> with James and repost the series at rc1 ? > > This patch series has depended on James's v6 patch series. It's a > description mistake. > > The link I posted is James's v6 patch series. > > Would you mind continue to review this patch series first? > > > Tao > Hi Suzuki, Do you have more review comments on the rest of the patches(#5-#11) in this series? Or do you prefer me to update patches(#1-#4) and resubmit first? Best, Tao >> >> Suzuki >> >> _______________________________________________ >> CoreSight mailing list -- coresight(a)lists.linaro.org >> To unsubscribe send an email to coresight-leave(a)lists.linaro.org

2 years

Re: [PATCH v4 1/4] devres: Provide krealloc_array

by Suzuki K Poulose

(Removed irrelevant recipients), +Cc: coresight ml Hi Greg, On 15/05/2023 12:55, Greg KH wrote: > On Mon, May 15, 2023 at 08:55:33AM +0100, James Clark wrote: >> >> >> On 13/05/2023 12:04, Greg KH wrote: >>> On Tue, May 09, 2023 at 10:49:38AM +0100, James Clark wrote: >>>> There is no krealloc_array equivalent in devres. Users would have to >>>> do their own multiplication overflow check so provide one. >>>> >>>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> >>>> Signed-off-by: James Clark <james.clark(a)arm.com> >>>> --- >>>> Documentation/driver-api/driver-model/devres.rst | 1 + >>>> include/linux/device.h | 11 +++++++++++ >>>> 2 files changed, 12 insertions(+) ... >> Maybe something could be done with some macro magic, but it would >> probably end up being worse than just copying them and would affect the >> real ones as well. So yeah I can't think of any easy gains either. > > Ok, that's good. Given a lack of objections from others, I'll just take > this through my driver core tree in a few days. Apologies for hijacking the thread. We have a series for CoreSight[1] that depends on this series, which I see that, is queued in your driver-core-next. I would like to queue [1] for the next version (as there are other work that depend on this, e.g., [2]). Do you have any recommendations/comments on the proposal ? Are you able to share a stable branch which can be merged to coresight/next and queue the series ontop ? (PS: I haven't queued anything for coresight/next yet). Kind regards Suzuki

2 years

[PATCH] arm64/sysreg: Convert TRBE registers to automatic generation

by Anshuman Khandual

This converts all TRBE related registers to automatic generation and update the driver as required. This does not cause any functional change. Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Mark Brown <broonie(a)kernel.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Marc Zyngier <maz(a)kernel.org> Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Cc: kvmarm(a)lists.linux.dev Cc: coresight(a)lists.linaro.org Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> --- This applies on v6.4-rc4. arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 49 ---------------- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- arch/arm64/tools/sysreg | 59 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.c | 33 +++++------ drivers/hwtracing/coresight/coresight-trbe.h | 38 +++++-------- 7 files changed, 94 insertions(+), 91 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 037724b19c5c..80e0460ca8bb 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -69,7 +69,7 @@ cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present mrs_s x0, SYS_TRBIDR_EL1 - and x0, x0, TRBIDR_PROG + and x0, x0, TRBIDR_EL1_PROG cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e72d9aaab6b1..51d97ea89972 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,55 +235,6 @@ /*** End of Statistical Profiling Extension ***/ -/* - * TRBE Registers - */ -#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0) -#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) -#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) -#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) -#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) -#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) -#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) - -#define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0) -#define TRBLIMITR_LIMIT_SHIFT 12 -#define TRBLIMITR_NVM BIT(5) -#define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0) -#define TRBLIMITR_TRIG_MODE_SHIFT 3 -#define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0) -#define TRBLIMITR_FILL_MODE_SHIFT 1 -#define TRBLIMITR_ENABLE BIT(0) -#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) -#define TRBPTR_PTR_SHIFT 0 -#define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) -#define TRBBASER_BASE_SHIFT 12 -#define TRBSR_EC_MASK GENMASK(5, 0) -#define TRBSR_EC_SHIFT 26 -#define TRBSR_IRQ BIT(22) -#define TRBSR_TRG BIT(21) -#define TRBSR_WRAP BIT(20) -#define TRBSR_ABORT BIT(18) -#define TRBSR_STOP BIT(17) -#define TRBSR_MSS_MASK GENMASK(15, 0) -#define TRBSR_MSS_SHIFT 0 -#define TRBSR_BSC_MASK GENMASK(5, 0) -#define TRBSR_BSC_SHIFT 0 -#define TRBSR_FSC_MASK GENMASK(5, 0) -#define TRBSR_FSC_SHIFT 0 -#define TRBMAR_SHARE_MASK GENMASK(1, 0) -#define TRBMAR_SHARE_SHIFT 8 -#define TRBMAR_OUTER_MASK GENMASK(3, 0) -#define TRBMAR_OUTER_SHIFT 4 -#define TRBMAR_INNER_MASK GENMASK(3, 0) -#define TRBMAR_INNER_SHIFT 0 -#define TRBTRG_TRG_MASK GENMASK(31, 0) -#define TRBTRG_TRG_SHIFT 0 -#define TRBIDR_FLAG BIT(5) -#define TRBIDR_PROG BIT(4) -#define TRBIDR_ALIGN_MASK GENMASK(3, 0) -#define TRBIDR_ALIGN_SHIFT 0 - #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 55f80fb93925..e09b9607ed52 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -333,7 +333,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) /* Check if we have TRBE implemented and available at the host */ if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && - !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_PROG)) + !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_PROG)) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); } diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c index d756b939f296..9b08f8b498fe 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -56,7 +56,7 @@ static void __debug_save_trace(u64 *trfcr_el1) *trfcr_el1 = 0; /* Check if the TRBE is enabled */ - if (!(read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_ENABLE)) + if (!(read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_EL1_ENABLE)) return; /* * Prohibit trace generation while we are in guest. diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c9a0d1fa3209..2396fa550251 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2200,3 +2200,62 @@ Sysreg ICC_NMIAR1_EL1 3 0 12 9 5 Res0 63:24 Field 23:0 INTID EndSysreg + +Sysreg TRBLIMITR_EL1 3 0 9 11 0 +Field 63:12 LIMIT +Res0 11:6 +Field 5 NVM +Enum 4:3 TRIG_MODE + 0b00 STOP + 0b01 IRQ + 0b11 IGNR +EndEnum +Enum 2:1 FILL_MODE + 0b00 FILL + 0b01 WRAP + 0b11 CBUF +EndEnum +Field 0 ENABLE +EndSysreg + +Sysreg TRBPTR_EL1 3 0 9 11 1 +Field 63:0 PTR +EndSysreg + +Sysreg TRBBASER_EL1 3 0 9 11 2 +Field 63:12 BASE +Res0 11:0 +EndSysreg + +Sysreg TRBSR_EL1 3 0 9 11 3 +Res0 63:32 +Field 31:26 EC +Res0 25:23 +Field 22 IRQ +Field 21 TRG +Field 20 WRAP +Res0 19 +Field 18 ABORT +Field 17 STOP +Res0 16 +Res0 15:6 +Field 5:0 BSC +EndSysreg + +Sysreg TRBMAR_EL1 3 0 9 11 4 +Res0 63:10 +Field 9:8 SH +Field 7:0 ATTR +EndSysreg + +Sysreg TRBTRG_EL1 3 0 9 11 6 +Res0 63:32 +Field 31:0 TRG +EndSysreg + +Sysreg TRBIDR_EL1 3 0 9 11 7 +Res0 63:6 +Field 5 FLAG +Field 4 PROG +Field 3:0 ALIGN +EndSysreg diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 1fc4fd79a1c6..f8f6adb5b0f5 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -218,7 +218,7 @@ static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) * Enable the TRBE without clearing LIMITPTR which * might be required for fetching the buffer limits. */ - trblimitr |= TRBLIMITR_ENABLE; + trblimitr |= TRBLIMITR_EL1_ENABLE; write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); /* Synchronize the TRBE enable event */ @@ -236,7 +236,7 @@ static inline void set_trbe_disabled(struct trbe_cpudata *cpudata) * Disable the TRBE without clearing LIMITPTR which * might be required for fetching the buffer limits. */ - trblimitr &= ~TRBLIMITR_ENABLE; + trblimitr &= ~TRBLIMITR_EL1_ENABLE; write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); if (trbe_needs_drain_after_disable(cpudata)) @@ -582,12 +582,12 @@ static void clr_trbe_status(void) u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1); WARN_ON(is_trbe_enabled()); - trbsr &= ~TRBSR_IRQ; - trbsr &= ~TRBSR_TRG; - trbsr &= ~TRBSR_WRAP; - trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT); - trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT); - trbsr &= ~TRBSR_STOP; + trbsr &= ~TRBSR_EL1_IRQ; + trbsr &= ~TRBSR_EL1_TRG; + trbsr &= ~TRBSR_EL1_WRAP; + trbsr &= ~TRBSR_EL1_EC_MASK; + trbsr &= ~TRBSR_EL1_BSC_MASK; + trbsr &= ~TRBSR_EL1_STOP; write_sysreg_s(trbsr, SYS_TRBSR_EL1); } @@ -596,13 +596,13 @@ static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); unsigned long addr = buf->trbe_limit; - WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT))); + WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_EL1_LIMIT_SHIFT))); WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); - trblimitr &= ~TRBLIMITR_NVM; - trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT); - trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT); - trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT); + trblimitr &= ~TRBLIMITR_EL1_NVM; + trblimitr &= ~TRBLIMITR_EL1_FILL_MODE_MASK; + trblimitr &= ~TRBLIMITR_EL1_TRIG_MODE_MASK; + trblimitr &= ~TRBLIMITR_EL1_LIMIT_MASK; /* * Fill trace buffer mode is used here while configuring the @@ -613,14 +613,15 @@ static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) * trace data in the interrupt handler, before reconfiguring * the TRBE. */ - trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT; + trblimitr |= (TRBLIMITR_EL1_FILL_MODE_FILL << TRBLIMITR_EL1_FILL_MODE_SHIFT) & + TRBLIMITR_EL1_FILL_MODE_MASK; /* * Trigger mode is not used here while configuring the TRBE for * the trace capture. Hence just keep this in the ignore mode. */ - trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << - TRBLIMITR_TRIG_MODE_SHIFT; + trblimitr |= (TRBLIMITR_EL1_TRIG_MODE_IGNR << TRBLIMITR_EL1_TRIG_MODE_SHIFT) & + TRBLIMITR_EL1_TRIG_MODE_MASK; trblimitr |= (addr & PAGE_MASK); set_trbe_enabled(buf->cpudata, trblimitr); } diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 98ff1b17ad07..be0ef7c9b4e6 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -30,7 +30,7 @@ static inline bool is_trbe_enabled(void) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); - return trblimitr & TRBLIMITR_ENABLE; + return trblimitr & TRBLIMITR_EL1_ENABLE; } #define TRBE_EC_OTHERS 0 @@ -39,7 +39,7 @@ static inline bool is_trbe_enabled(void) static inline int get_trbe_ec(u64 trbsr) { - return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK; + return (trbsr & TRBSR_EL1_EC_MASK) >> TRBSR_EL1_EC_SHIFT; } #define TRBE_BSC_NOT_STOPPED 0 @@ -48,63 +48,55 @@ static inline int get_trbe_ec(u64 trbsr) static inline int get_trbe_bsc(u64 trbsr) { - return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK; + return (trbsr & TRBSR_EL1_BSC_MASK) >> TRBSR_EL1_BSC_SHIFT; } static inline void clr_trbe_irq(void) { u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1); - trbsr &= ~TRBSR_IRQ; + trbsr &= ~TRBSR_EL1_IRQ; write_sysreg_s(trbsr, SYS_TRBSR_EL1); } static inline bool is_trbe_irq(u64 trbsr) { - return trbsr & TRBSR_IRQ; + return trbsr & TRBSR_EL1_IRQ; } static inline bool is_trbe_trg(u64 trbsr) { - return trbsr & TRBSR_TRG; + return trbsr & TRBSR_EL1_TRG; } static inline bool is_trbe_wrap(u64 trbsr) { - return trbsr & TRBSR_WRAP; + return trbsr & TRBSR_EL1_WRAP; } static inline bool is_trbe_abort(u64 trbsr) { - return trbsr & TRBSR_ABORT; + return trbsr & TRBSR_EL1_ABORT; } static inline bool is_trbe_running(u64 trbsr) { - return !(trbsr & TRBSR_STOP); + return !(trbsr & TRBSR_EL1_STOP); } -#define TRBE_TRIG_MODE_STOP 0 -#define TRBE_TRIG_MODE_IRQ 1 -#define TRBE_TRIG_MODE_IGNORE 3 - -#define TRBE_FILL_MODE_FILL 0 -#define TRBE_FILL_MODE_WRAP 1 -#define TRBE_FILL_MODE_CIRCULAR_BUFFER 3 - static inline bool get_trbe_flag_update(u64 trbidr) { - return trbidr & TRBIDR_FLAG; + return trbidr & TRBIDR_EL1_FLAG; } static inline bool is_trbe_programmable(u64 trbidr) { - return !(trbidr & TRBIDR_PROG); + return !(trbidr & TRBIDR_EL1_PROG); } static inline int get_trbe_address_align(u64 trbidr) { - return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK; + return (trbidr & TRBIDR_EL1_ALIGN_MASK) >> TRBIDR_EL1_ALIGN_SHIFT; } static inline unsigned long get_trbe_write_pointer(void) @@ -121,7 +113,7 @@ static inline void set_trbe_write_pointer(unsigned long addr) static inline unsigned long get_trbe_limit_pointer(void) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); - unsigned long addr = trblimitr & (TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT); + unsigned long addr = trblimitr & TRBLIMITR_EL1_LIMIT_MASK; WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); return addr; @@ -130,7 +122,7 @@ static inline unsigned long get_trbe_limit_pointer(void) static inline unsigned long get_trbe_base_pointer(void) { u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1); - unsigned long addr = trbbaser & (TRBBASER_BASE_MASK << TRBBASER_BASE_SHIFT); + unsigned long addr = trbbaser & TRBBASER_EL1_BASE_MASK; WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); return addr; @@ -139,7 +131,7 @@ static inline unsigned long get_trbe_base_pointer(void) static inline void set_trbe_base_pointer(unsigned long addr) { WARN_ON(is_trbe_enabled()); - WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_BASE_SHIFT))); + WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_EL1_BASE_SHIFT))); WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); write_sysreg_s(addr, SYS_TRBBASER_EL1); } -- 2.25.1

2 years

[PATCH V4 0/6] coresight: etm4x: Migrate ACPI AMBA devices to platform driver

by Anshuman Khandual

CoreSight ETM4x devices could be accessed either via MMIO (handled via amba_driver) or CPU system instructions (handled via platform driver). But this has the following issues : - Each new CPU comes up with its own PID and thus we need to keep on adding the "known" PIDs to get it working with AMBA driver. While the ETM4 architecture (and CoreSight architecture) defines way to identify a device as ETM4. Thus older kernels won't be able to "discover" a newer CPU, unless we add the PIDs. - With ACPI, the ETM4x devices have the same HID to identify the device irrespective of the mode of access. This creates a problem where two different drivers (both AMBA based driver and platform driver) would hook into the "HID" and could conflict. e.g., if AMBA driver gets hold of a non-MMIO device, the probe fails. If we have single driver hooked into the given "HID", we could handle them seamlessly, irrespective of the mode of access. - CoreSight is heavily dependent on the runtime power management. With ACPI, amba_driver doesn't get us anywhere with handling the power and thus one need to always turn the power ON to use them. Moving to platform driver gives us the power management for free. Due to all of the above, we are moving ACPI MMIO based etm4x devices to be supported via tha platform driver. The series makes the existing platform driver generic to handle both type of the access modes. Although existing AMBA driver would still continue to support DT based etm4x MMIO devices. Although some problems still remain, such as manually adding PIDs for all new AMBA DT based devices. The series applies on 6.4-rc3. Changes in V4: - Changed in-code comment in etm4_check_arch_features() - Re-ordered pm_runtime_disable() in etm4_remove_platform_dev() - Renamed back etm4_match as etm4_sysreg_match - Moved back [PATCH 6/6] as [PATCH 5/6] Changes in V3: https://lore.kernel.org/all/20230519052149.1367814-1-anshuman.khandual@arm.… - Returned from etm4_check_arch_features() for non iomem devices - Renamed ETM_DEVTYPE_ETMv4x_ARCH as CS_DEVTYPE_PE_TRACE - Renamed is_etm4x_devtype() as is_devtype_cpu_trace() - Added a patch to ignore the absence of graph connections Changes in V2: https://lore.kernel.org/all/20230327050537.30861-1-anshuman.khandual@arm.co… - Enables ACPI etm4x device support in the existing platform driver - Dropped last two patches from the series - Dropped redundant 'devarch' checking from is_etm4x_device() - Renamed updated is_etm4x_device() as is_etm4x_devtype() - Fixed arguments in fallback stub for etm4_check_arch_features() - Tagged etm4_dev_pm_ops with etm4_platform_driver - Updated the comment for coresight_get_enable_apb_pclk() helper - Updated the comment for new 'pclk' element in struct etm4_drvdata - Dropped the clock when devm_ioremap_resource() fails - Convert IS_ERR() into a direct pointer check in etm4_remove_platform_dev() - Dropped "arm,coresight-etm4x" compatible property from etm4_match[] Changes in V1: https://lore.kernel.org/all/20230317030501.1811905-1-anshuman.khandual@arm.… Cc: Ganapatrao Kulkarni <gankulkarni(a)os.amperecomputing.com> Cc: Steve Clevenger <scclevenger(a)os.amperecomputing.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Frank Rowand <frowand.list(a)gmail.com> Cc: Russell King (Oracle) <linux(a)armlinux.org.uk> Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> Cc: "Rafael J. Wysocki" <rafael(a)kernel.org> Cc: Len Brown <lenb(a)kernel.org> Cc: Sudeep Holla <sudeep.holla(a)arm.com> Cc: Lorenzo Pieralisi <lpieralisi(a)kernel.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: devicetree(a)vger.kernel.org Cc: linux-acpi(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Anshuman Khandual (4): coresight: etm4x: Allocate and device assign 'struct etmv4_drvdata' earlier coresight: etm4x: Drop iomem 'base' argument from etm4_probe() coresight: etm4x: Drop pid argument from etm4_probe() coresight: etm4x: Change etm4_platform_driver driver for MMIO devices Suzuki K Poulose (2): coresight: platform: acpi: Ignore the absence of graph coresight: etm4x: Add ACPI support in platform driver drivers/acpi/acpi_amba.c | 1 - .../coresight/coresight-etm4x-core.c | 117 ++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 4 + .../hwtracing/coresight/coresight-platform.c | 6 +- include/linux/coresight.h | 59 +++++++++ 5 files changed, 163 insertions(+), 24 deletions(-) -- 2.25.1

2 years

About the new ACPI HID for supporting ARM CoreSight ETE

by hejunhao

Hi Suzuki & Anshuman. I have some questions about the new ACPI HID for ARM CoreSight ETE and need to get you help to confirm. a）Has ARM distributed a new ACPI HID for ETE, or is it plans to do so? If possible, can the new HID be provided in advance? b) Or Is it possible to add an new ACPI HID (HISI0461) for HiSilicon ETE. Best regards, Junhao.

2 years, 1 month

Re: [PATCH v2] perf arm: Fix include path

by Arnaldo Carvalho de Melo

Em Mon, May 15, 2023 at 09:50:39AM -0700, Ian Rogers escreveu: > Change "../cs-etm.h" to just "../../../util/cs-etm.h" as ../cs-etm.h > doesn't exist. Thanks, applied. - Arnaldo > Suggested-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Ian Rogers <irogers(a)google.com> > Reviewed-by: Leo Yan <leo.yan(a)linaro.org> > --- > tools/perf/arch/arm/util/pmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c > index 860a8b42b4b5..a9623b128ece 100644 > --- a/tools/perf/arch/arm/util/pmu.c > +++ b/tools/perf/arch/arm/util/pmu.c > @@ -12,7 +12,7 @@ > #include "arm-spe.h" > #include "hisi-ptt.h" > #include "../../../util/pmu.h" > -#include "../cs-etm.h" > +#include "../../../util/cs-etm.h" > > struct perf_event_attr > *perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused) > -- > 2.40.1.606.ga4b1b128d6-goog > -- - Arnaldo

2 years, 1 month

[PATCH] perf cs-etm: Copy kernel coresight-pmu.h header

by James Clark

Copy the kernel version of the header to fix the header diff build warning. Some new definitions were only added to the tools side header, but these are only used in Perf so move them to a different header. Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/include/linux/coresight-pmu.h | 13 ------------- tools/perf/util/cs-etm.h | 13 +++++++++++++ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index cef3b1c25335..51ac441a37c3 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -21,19 +21,6 @@ */ #define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) -/* CoreSight trace ID is currently the bottom 7 bits of the value */ -#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) - -/* - * perf record will set the legacy meta data values as unused initially. - * This allows perf report to manage the decoders created when dynamic - * allocation in operation. - */ -#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) - -/* Value to set for unused trace ID values */ -#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F - /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 70cac0375b34..ecca40787ac9 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -227,6 +227,19 @@ struct cs_etm_packet_queue { #define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \ sizeof(((struct perf_record_auxtrace_info *)0)->reserved__)) +/* CoreSight trace ID is currently the bottom 7 bits of the value */ +#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) + +/* + * perf record will set the legacy meta data values as unused initially. + * This allows perf report to manage the decoders created when dynamic + * allocation in operation. + */ +#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) + +/* Value to set for unused trace ID values */ +#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F + int cs_etm__process_auxtrace_info(union perf_event *event, struct perf_session *session); struct perf_event_attr *cs_etm_get_default_config(struct perf_pmu *pmu); -- 2.34.1

2 years, 1 month

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