CoreSight

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Re: [PATCH V5 0/4] coresight: trbe: Enable ACPI based devices

by Suzuki K Poulose

On 21/08/2023 12:28, Will Deacon wrote: > On Sat, Aug 19, 2023 at 08:36:28AM +0100, Suzuki K Poulose wrote: >> On 18/08/2023 19:04, Will Deacon wrote: >>> On Thu, 17 Aug 2023 11:24:01 +0530, Anshuman Khandual wrote: >>>> This series enables detection of ACPI based TRBE devices via a stand alone >>>> purpose built representative platform device. But as a pre-requisite this >>>> changes coresight_platform_data structure assignment for the TRBE device. >>>> >>>> This series is based on v6.5-rc5 kernel, is also dependent on the following >>>> EDK2 changes posted earlier by Sami. >>>> >>>> [...] >>> >>> Applied to will (for-next/perf), thanks! >>> >>> [1/4] arm_pmu: acpi: Refactor arm_spe_acpi_register_device() >>> https://git.kernel.org/will/c/81e5ee471609 >>> [2/4] arm_pmu: acpi: Add a representative platform device for TRBE >>> https://git.kernel.org/will/c/1aa3d0274a4a >>> [3/4] coresight: trbe: Add a representative coresight_platform_data for TRBE >>> https://git.kernel.org/will/c/e926b8e9eb40 >> >> This will conflict with what I have (already) sent to Greg for >> coresight/next. Please let me know how you would like handle it > > Hmm, the rationale behind your change to make the pdata allocation > per-device in ("coresight: trbe: Allocate platform data per device") > confuses me: with Anshuman's change to allocate the pdata using > devm_kzalloc(), there shouldn't be any connections for the coresight > core to trip over, should there? Anshuman's patch is working around the problem of "TRBE platform device with ACPI doesn't have a valid companion device" - this is a problem for the acpi_get_coresight_platform_data(). The work around is to move the "allocation" from coresight_get_platform_data() to the driver (given we don't need anything else from the ACPI except the IRQ). That doesn't change *how* it is allocated. Also please note that, the TRBE driver creates a TRBE coresight_device per-CPU and the platform data is shared by all of these devices, which the coresight core driver doesn't cope with. The other option is to move the releasing of these platform-data to the individual drivers, which is quite an invasive change. Or, make the core driver tolerate a NULL platform data, which is also again invasive. So the merged fix is correct and is still valid after this patch. > > It would've been nice to know about the conflict earlier, but since I > think you're away this week and we're likely to hit the merge window > next week, I'm going to drop the coresight patches for now. Apologies, I was expecting to queue the changes via coresight tree, given how it was affecting the tree and was awaiting your Ack. However I didn't confirm it on the list, which is my mistake. The other problem was reported and the fix eventually had to conflict with Anshuman's series, which he was made aware of. Given, your Ack was missing I hoping that Anshuman could respin the series with your Ack on top of the fix and eventually queue that via my tree. Suzuki > > Will

2 years

Re: How to debug SysReg access to ETE causing system crash

by Suzuki K Poulose

Hi Yabin On 26/08/2023 01:30, Yabin Cui wrote: > Hi Suzuki, > > When I saw the crash, the kernel log stopped immediately before "devarch > = read_etm4x_sysreg_const_offset(TRCDEVARCH);". > And then the device rebooted. The reason for the reboot is watchdog crash. Isn't there any way to collect information from your hypervisor ? > > If EL2 doesn't allow accessing the TRC* registers via system instruction > interface, why can't I find any description in the ARM manual? Please look at the description for HDFGRTR_EL2/HDFGWTR_EL2 for more information on this. e.g., HDFGRTR_EL2:TRCID controls read access to TRCDEVARCH, which is where you hit the crash. > > And from my understanding, ETE is still powered on even when the cpu is > idle. Can it not be powered? There is extra clock enabling work > when using the iomem interface, I will try if it matters. As I mentioned, this is very unlikely. Most likely, your hypervisor is at fault. Suzuki > > Thanks, > Yabin > > > On Fri, Aug 18, 2023 at 1:47 AM Suzuki K Poulose <suzuki.poulose(a)arm.com > <mailto:suzuki.poulose@arm.com>> wrote: > > Hi Yabin > > On 17/08/2023 22:06, Yabin Cui wrote: > > Hi coresight driver maintainers, > > > > I am from the Android toolchain team. I am trying to use ETE > (Embedded > > Trace Extension). But on my device, the system crashes when the ETM > > driver is trying to read TRCDEVARCH via sysreg interface. > > When you say crashes, what exactly is reported ? Does the kernel > get an exception ? Or system hangs completely ? > > I suspect : > > 1) You are running some hyp at EL2, which doesn't allow > accessing the TRC* registers and injects a Illegal instruction ? > 2) If not the above, the ETE is not powered (very unlikely) > > > Suzuki > > > > In > > > https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c… <https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c…> <https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c… <https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c…>> : > > > > static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, > > struct csdev_access *csa) > > { > > u32 devarch; > > > > if (!cpu_supports_sysreg_trace()) <- this returns true > > return false; > > > > /* > > * ETMs implementing sysreg access must implement TRCDEVARCH. > > */ > > devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); <- never > see the > > message logged immediately after this line, so should abort here. > > ... > > } > > > > Do you have any suggestions on how I can debug the problem? Is > there any > > other place making sysreg interface to ETE not accessible? Or can > the > > ETE sysreg interface not be implemented? > > I tried the memory mapped register interface of ETE, it works > fine. The > > only change I need is to bypass the devarch version check > > in etm4_init_iomem_access, in in > > > https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c… <https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c…> <https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c… <https://github.com/torvalds/linux/blob/master/drivers/hwtracing/coresight/c…>> > > I wonder if we can allow iomem access for ETE if the sysreg access > > doesn't work on some devices. > > > > Thanks, > > Yabin >

2 years

Re: [PATCH] coresight: tmc-etr: Don't fail probe when non-secure access is disabled

by Suzuki K Poulose

On 26/08/2023 00:39, Yabin Cui wrote: > Because the non-secure access can be enabled later on some devices. How can this be enabled ? Why not enable it before probing the ETR ? How can a user know if this has been done or not ? It is asking for trouble to continue without this. Suzuki > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > --- > drivers/hwtracing/coresight/coresight-tmc-core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index c106d142e632..5ebfd12b627b 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -370,7 +370,7 @@ static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps) > struct tmc_drvdata *drvdata = dev_get_drvdata(parent); > > if (!tmc_etr_has_non_secure_access(drvdata)) > - return -EACCES; > + dev_warn(parent, "TMC ETR doesn't have non-secure access\n"); > > /* Set the unadvertised capabilities */ > tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);

2 years

Re: [PATCH V2] coresight: tmc: Make etr buffer mode user configurable from sysfs

by Suzuki K Poulose

Hi Steve On 26/08/2023 01:14, Steve Clevenger wrote: > > Unfortunately, I tested with the original patch not [PATCH V2]. I've > remedied this. My results below: > > [root@sut01sys-b212 linux]# cat > /sys/devices/system/cpu/cpu123/ARMHC501\:23/tmc_etr35/buf_modes_available > auto flat catu > [root@sut01sys-b212 linux]# cat > /sys/devices/system/cpu/cpu123/ARMHC501\:23/tmc_etr35/buf_mode_preferred > auto > [root@sut01sys-b212 linux]# echo "catu" > > /sys/devices/system/cpu/cpu123/ARMHC501\:23/tmc_etr35/buf_mode_preferred > [root@sut01sys-b212 linux]# cat > /sys/devices/system/cpu/cpu123/ARMHC501\:23/tmc_etr35/buf_mode_preferred > catu > > As with the V1 patch, auto defaults to catu. > > I expected to see tmc-sg (former default) as an available mode, but do > not. As I recall, the buffer mode defaulted to ETR scatter-gather prior > to this patch. Must this capability now be explicitly advertised? I've > seen this done as "arm,scatter-gather" in device trees, but not used by > Ampere. Perhaps someone can enlighten me. Yes, you must add that property to the TMC-ETR node (for both DT and ACPI). In the past, almost all of the TMC-ETRs (except Juno board) locked up the system while using the SG mode (due to the interconnect issues, something to do with the transaction). Thus, we decided to add a property explicitly enabling this for a given platform. When you mentioned, it was using TMC-ETR SG mode, how did you verify this ? Please be aware that the table allocation code etc are shared by both TMC-SG and CATU. Kind regards Suzuki > > Steve C. > > On 8/23/2023 4:10 PM, Steve Clevenger wrote: >> >> Here's some quick feedback. My system shows two modes available; auto catu >> >> etr_buf_mode_current is writable. I expected to see tmc-sg (former >> default) listed in etr_buf_modes_available but it doesn't show up. >> >> Note that both the auto and catu etr_buf_mode_current settings default >> to catu. My understanding is auto should revert to the default behavior. >> On my system the default was tmc-sg. >> >> More later. >> >> [root@sut01sys-b212 kernel]# cat >> /sys/devices/system/cpu/cpu20/ARMHC501\:60/tmc_etr96/etr_buf_modes_available >> >> auto catu >> [root@sut01sys-b212 kernel]# cat >> /sys/devices/system/cpu/cpu20/ARMHC501\:60/tmc_etr96/etr_buf_mode_current >> catu >> [root@sut01sys-b212 kernel]# echo "catu" > >> /sys/devices/system/cpu/cpu20/ARMHC501\:60/tmc_etr96/etr_buf_mode_current >> [root@sut01sys-b212 kernel]# cat >> /sys/devices/system/cpu/cpu20/ARMHC501\:60/tmc_etr96/etr_buf_mode_current >> catu >> >> Steve C. >> >> >> On 8/21/2023 12:40 PM, Steve Clevenger wrote: >>> >>> Hi Suzuki, >>> >>> I may be able to test it this week. You've already pointed me at the >>> patch thread(s). The main holdup is I need to merge the 6.6 pending >>> platform work in order to use the Ampere ACPI. I couldn't get these >>> patches to apply directly to 6.4 last I tried. >>> >>> Steve C. >>> >>> On 8/18/2023 2:39 AM, Suzuki K Poulose wrote: >>>> Cc: Steve >>>> >>>> Steve, >>>> >>>> Are you able to test this with CATU ? >>>> >>>> >>>> On 18/08/2023 09:21, Anshuman Khandual wrote: >>>>> Currently TMC-ETR automatically selects the buffer mode from all >>>>> available >>>>> methods in the following sequentially fallback manner - also in that >>>>> order. >>>>> >>>>> 1. FLAT mode with or without IOMMU >>>>> 2. TMC-ETR-SG (scatter gather) mode when available >>>>> 3. CATU mode when available >>>>> >>>>> But this order might not be ideal for all situations. For example if >>>>> there >>>>> is a CATU connected to ETR, it may be better to use TMC-ETR scatter >>>>> gather >>>>> method, rather than CATU. But hard coding such order changes will prevent >>>>> us from testing or using a particular mode. This change provides >>>>> following >>>>> new sysfs tunables for the user to control TMC-ETR buffer mode >>>>> explicitly, >>>>> if required. This adds following new sysfs files for buffer mode >>>>> selection >>>>> purpose explicitly in the user space. >>>>> >>>>> /sys/bus/coresight/devices/tmc_etr<N>/buf_modes_available >>>>> /sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred >>>>> >>>>> $ cat buf_modes_available >>>>> auto flat tmc-sg catu ------------------> Supported TMC-ETR buffer >>>>> modes >>>>> >>>>> $ echo catu > buf_mode_preferred -------> Explicit buffer mode request >>>>> >>>>> But explicit user request has to be within supported ETR buffer modes >>>>> only. >>>>> These sysfs interface files are exclussive to ETR, and hence these are >>>>> not >>>>> available for other TMC devices such as ETB or ETF etc. >>>>> >>>>> A new auto' mode (i.e ETR_MODE_AUTO) has been added to help fallback >>>>> to the >>>>> existing default behaviour, when user provided preferred buffer mode >>>>> fails. >>>>> ETR_MODE_FLAT and ETR_MODE_AUTO are always available as preferred modes. >>>>> >>>>> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>>>> Cc: Mike Leach <mike.leach(a)linaro.org> >>>>> Cc: James Clark <james.clark(a)arm.com> >>>>> Cc: Leo Yan <leo.yan(a)linaro.org> >>>>> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> >>>>> Cc: coresight(a)lists.linaro.org >>>>> Cc: linux-arm-kernel(a)lists.infradead.org >>>>> Cc: linux-kernel(a)vger.kernel.org >>>>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>>>> --- >>>>> This applies on v6.5-rc6 >>>>> >>>>> Changes in V2: >>>>> >>>>> - Renamed sysfs file etr_buf_modes_available as buf_modes_available >>>>> - Renamed sysfs file buf_mode_current as buf_mode_preferred >>>>> - Renamed etr_supports_flat_mode() as etr_can_use_flat_mode() >>>>> - Renamed coresight_tmc_groups[] as coresight_etf_groups[] >>>>> - Reused coresight_tmc_group[] for trigger_cntr and buffer_size >>>>> - Fallback trying ETR_MODE_AUTO when user preferred mode fails >>>>> - Moved ETR sysfs details into coresight-tmc-etr.c >>>>> - Dropped etr_can_use_flat_mode() check while offering ETR_MODE_FLAT >>>>> in sysfs >>>>> - Moved struct etr_buf_hw inside coresight-tmc-etr.c >>>>> - Moved get_etr_buf_hw() and etr_can_use_flat_mode() inside >>>>> coresight-tmc-etr.c >>>>> - Updated month in >>>>> Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc >>>>> >>>>> Changes in V1: >>>>> >>>>> https://lore.kernel.org/all/20230728084837.276551-1-anshuman.khandual@arm.c… >>>>> >>>>> .../testing/sysfs-bus-coresight-devices-tmc | 16 +++ >>>>> .../hwtracing/coresight/coresight-tmc-core.c | 15 ++- >>>>> .../hwtracing/coresight/coresight-tmc-etr.c | 111 ++++++++++++++++-- >>>>> drivers/hwtracing/coresight/coresight-tmc.h | 3 + >>>>> 4 files changed, 131 insertions(+), 14 deletions(-) >>>> >>>> >>>> Looks good to me. >>>> >>>> Suzuki >>>> >>>>

2 years

Re: [PATCH V4 1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus

by Anshuman Khandual

On 8/19/23 02:41, Randy Dunlap wrote: > Hi-- > > On 8/18/23 04:20, Anshuman Khandual wrote: >> This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata >> 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on >> Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN >> field in ETM gets an wrong value. >> >> If software uses the value returned by the TRCIDR3.CCITMIN register field, >> then it will limit the range which could be used for programming the ETM. >> In reality, the ETM could be programmed with a much smaller value than what >> is indicated by the TRCIDR3.CCITMIN field and still function correctly. >> >> If software reads the TRCIDR3.CCITMIN register field, corresponding to the >> instruction trace counting minimum threshold, observe the value 0x100 or a >> minimum cycle count threshold of 256. The correct value should be 0x4 or a >> minimum cycle count threshold of 4. >> >> This work arounds the problem via storing 4 in drvdata->ccitmin on affected >> systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count >> threshold granularity. >> >> These errata information has been updated in arch/arm64/silicon-errata.rst, >> but without their corresponding configs because these have been implemented >> directly in the driver. >> >> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >> Cc: Will Deacon <will(a)kernel.org> >> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> Cc: Mike Leach <mike.leach(a)linaro.org> >> Cc: James Clark <james.clark(a)arm.com> >> Cc: Jonathan Corbet <corbet(a)lwn.net> >> Cc: linux-doc(a)vger.kernel.org >> Cc: coresight(a)lists.linaro.org >> Cc: linux-arm-kernel(a)lists.infradead.org >> Cc: linux-kernel(a)vger.kernel.org >> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >> --- >> Documentation/arch/arm64/silicon-errata.rst | 10 ++++++ >> .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++++++ >> 2 files changed, 46 insertions(+) >> > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 7e307022303a..591fab73ee79 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1131,6 +1131,39 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) >> drvdata->trfcr = trfcr; >> } >> >> +/* >> + * The following errata on applicable cpu ranges, affect the CCITMIN filed >> + * in TCRIDR3 register. Software read for the field returns 0x100 limiting >> + * the cycle threshold granularity, where as the right value should have > > whereas > >> + * been 0x4, which is well supported in the hardware. >> + */ >> +static struct midr_range etm_wrong_ccitmin_cpus[] = { >> + /* Erratum #1490853 - Cortex-A76 */ >> + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0), >> + /* Erratum #1490853 - Neoverse-N1 */ >> + MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0), >> + /* Erratum #1491015 - Cortex-A77 */ >> + MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), >> + /* Erratum #1502854 - Cortex-X1 */ >> + MIDR_REV(MIDR_CORTEX_X1, 0, 0), >> + /* Erratum #1619801 - Neoverse-V1 */ >> + MIDR_REV(MIDR_NEOVERSE_V1, 0, 0), >> + {}, >> +}; >> + >> +static bool etm4_core_reads_wrong_ccitmin(struct etmv4_drvdata *drvdata) >> +{ >> + /* >> + * Erratum affected cpus will read 256 as the minimum >> + * instruction trace cycle counting threshold where as > > whereas Right, 'whereas' is a single word indeed. I will change these as required.

2 years

[PATCH V4 0/3] coresight: etm: Make cycle count threshold user configurable

by Anshuman Khandual

This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via the perf event attribute. But first, this implements an errata work around affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field. This series applies on v6.5-rc6. Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Jonathan Corbet <corbet(a)lwn.net> Cc: linux-doc(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Changes in V4: - Fixed a typo s/rangess/ranges, - Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin() - Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin() - Moved the comment inside etm4_core_reads_wrong_ccitmin() Changes in V3: https://lore.kernel.org/all/20230811034600.944386-1-anshuman.khandual@arm.c… - Added errata work around affecting TRCIDR3.CCITMIN - Split the document update into a separate patch Changes in V2: https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.c… - s/treshhold/threshold Changes in V1: https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.… Anshuman Khandual (3): coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus coresight: etm: Make cycle count threshold user configurable Documentation: coresight: Add cc_threshold tunable Documentation/arch/arm64/silicon-errata.rst | 10 ++++ Documentation/trace/coresight/coresight.rst | 4 ++ .../hwtracing/coresight/coresight-etm-perf.c | 2 + .../coresight/coresight-etm4x-core.c | 48 ++++++++++++++++++- 4 files changed, 62 insertions(+), 2 deletions(-) -- 2.25.1

2 years

[PATCH v7 00/13] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_idx echo 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0x5 > /sys/bus/coresight/devices/tpdm0/dsb_patt_idx echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0x2 > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_idx echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v7 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v7 Changes in V7: 1. Since the "One value" limitation on SysFs file usage, add the nodes to read/write the index number for configuring the DSB TPDM. The following index number nodes are added. "dsb_edge_ctrl_idx" in the patch #9 "dsb_trig_patt_idx" in the patch #10 "dsb_patt_idx" in the patch #11 "dsb_msr_idx" in the patch #13 -- Suzuki K Poulose Changes in V6: 1. Align the code to fix the styling issue. -- Suzuki K Poulose Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 192 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 96 ++- drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 806 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 91 +++ include/linux/coresight.h | 1 + 8 files changed, 1193 insertions(+), 18 deletions(-) -- 2.7.4

2 years

Re: [PATCH V5 0/4] coresight: trbe: Enable ACPI based devices

by Suzuki K Poulose

Hi Will On 18/08/2023 19:04, Will Deacon wrote: > On Thu, 17 Aug 2023 11:24:01 +0530, Anshuman Khandual wrote: >> This series enables detection of ACPI based TRBE devices via a stand alone >> purpose built representative platform device. But as a pre-requisite this >> changes coresight_platform_data structure assignment for the TRBE device. >> >> This series is based on v6.5-rc5 kernel, is also dependent on the following >> EDK2 changes posted earlier by Sami. >> >> [...] > > Applied to will (for-next/perf), thanks! > > [1/4] arm_pmu: acpi: Refactor arm_spe_acpi_register_device() > https://git.kernel.org/will/c/81e5ee471609 > [2/4] arm_pmu: acpi: Add a representative platform device for TRBE > https://git.kernel.org/will/c/1aa3d0274a4a > [3/4] coresight: trbe: Add a representative coresight_platform_data for TRBE > https://git.kernel.org/will/c/e926b8e9eb40 This will conflict with what I have (already) sent to Greg for coresight/next. Please let me know how you would like handle it Suzuki > [4/4] coresight: trbe: Enable ACPI based TRBE devices > https://git.kernel.org/will/c/0fb93c5ede13 > > Cheers,

2 years

[GIT PULL] coresight: hwtracing: subsystem updates for v6.6

by Suzuki K Poulose

The following changes since commit 6eaae198076080886b9e7d57f4ae06fa782f90ef: Linux 6.5-rc3 (2023-07-23 15:24:10 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.6 for you to fetch changes up to c0a232f1e19e378c5c4e5973a996392942c80090: coresight: trbe: Fix TRBE potential sleep in atomic context (2023-08-18 16:42:26 +0100) ---------------------------------------------------------------- coresigh: Updates for v6.6 Coresight and hwtracing subsystem updates for Linux v6.6 includes: - ACPI support for CoreSight ETMv4x via system instructions and Arm ETE (v9.x). - Fix potential sleeping in atomic context for TRBE driver - Fix memory leak in ACPI platform parsing code - Fix all warnings with W=1 - Fix warning with double free attempt for TRBE platform data - Miscellaneous cleanups and fixes Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Anshuman Khandual (6): coresight: etm4x: Allocate and device assign 'struct etmv4_drvdata' earlier coresight: etm4x: Drop iomem 'base' argument from etm4_probe() coresight: etm4x: Drop pid argument from etm4_probe() coresight: etm4x: Change etm4_platform_driver driver for MMIO devices coresight: trbe: Directly use ID_AA64DFR0_EL1_TraceBuffer_IMP coresight: etm4x: Ensure valid drvdata and clock before clk_put() James Clark (1): coresight: Fix all W=1 build warnings Junhao He (2): coresight: Fix memory leak in acpi_buffer->pointer coresight: trbe: Fix TRBE potential sleep in atomic context Rob Herring (1): hwtracing: coresight: Explicitly include correct DT includes Ruidong Tian (1): coresight: tmc: Explicit type conversions to prevent integer overflow Suzuki K Poulose (3): coresight: platform: acpi: Ignore the absence of graph coresight: etm4x: Add ACPI support in platform driver coresight: trbe: Allocate platform data per device Xiongfeng Wang (1): hwtracing: hisi_ptt: Use pci_dev_id() to simplify the code Yang Yingliang (1): coresight: dummy: simplify the code with module_platform_driver drivers/acpi/acpi_amba.c | 1 - drivers/hwtracing/coresight/coresight-core.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-dummy.c | 12 +-- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 118 +++++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 4 + drivers/hwtracing/coresight/coresight-platform.c | 46 +++++--- drivers/hwtracing/coresight/coresight-tmc-etf.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 43 ++++---- drivers/hwtracing/coresight/coresight-trbe.h | 2 +- drivers/hwtracing/ptt/hisi_ptt.c | 8 +- include/linux/coresight.h | 59 +++++++++++ 15 files changed, 225 insertions(+), 85 deletions(-)

2 years

[PATCH V3] coresight: trbe: Fix TRBE potential sleep in atomic context

by Junhao He

smp_call_function_single() will allocate an IPI interrupt vector to the target processor and send a function call request to the interrupt vector. After the target processor receives the IPI interrupt, it will execute arm_trbe_remove_coresight_cpu() call request in the interrupt handler. According to the device_unregister() stack information, if other process is useing the device, the down_write() may sleep, and trigger deadlocks or unexpected errors. arm_trbe_remove_coresight_cpu coresight_unregister device_unregister device_del kobject_del __kobject_del sysfs_remove_dir kernfs_remove down_write ---------> it may sleep Add a helper arm_trbe_disable_cpu() to disable TRBE precpu irq and reset per TRBE. Simply call arm_trbe_remove_coresight_cpu() directly without useing the smp_call_function_single(), which is the same as registering the TRBE coresight device. Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> Link: https://lore.kernel.org/r/20230814093813.19152-2-hejunhao3@huawei.com [ Remove duplicate cpumask checks during removal ] Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> [ v3 - Remove the operation of assigning NULL to cpudata->drvdata ] --- drivers/hwtracing/coresight/coresight-trbe.c | 32 +++++++++++--------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 8e4eb37e66e8..e20c1c6acc73 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1225,6 +1225,16 @@ static void arm_trbe_enable_cpu(void *info) enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE); } +static void arm_trbe_disable_cpu(void *info) +{ + struct trbe_drvdata *drvdata = info; + struct trbe_cpudata *cpudata = this_cpu_ptr(drvdata->cpudata); + + disable_percpu_irq(drvdata->irq); + trbe_reset_local(cpudata); +} + + static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cpu) { struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); @@ -1329,18 +1339,12 @@ static void arm_trbe_probe_cpu(void *info) cpumask_clear_cpu(cpu, &drvdata->supported_cpus); } -static void arm_trbe_remove_coresight_cpu(void *info) +static void arm_trbe_remove_coresight_cpu(struct trbe_drvdata *drvdata, int cpu) { - int cpu = smp_processor_id(); - struct trbe_drvdata *drvdata = info; - struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); struct coresight_device *trbe_csdev = coresight_get_percpu_sink(cpu); - disable_percpu_irq(drvdata->irq); - trbe_reset_local(cpudata); if (trbe_csdev) { coresight_unregister(trbe_csdev); - cpudata->drvdata = NULL; coresight_set_percpu_sink(cpu, NULL); } } @@ -1369,8 +1373,10 @@ static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata) { int cpu; - for_each_cpu(cpu, &drvdata->supported_cpus) - smp_call_function_single(cpu, arm_trbe_remove_coresight_cpu, drvdata, 1); + for_each_cpu(cpu, &drvdata->supported_cpus) { + smp_call_function_single(cpu, arm_trbe_disable_cpu, drvdata, 1); + arm_trbe_remove_coresight_cpu(drvdata, cpu); + } free_percpu(drvdata->cpudata); return 0; } @@ -1409,12 +1415,8 @@ static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node) { struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node); - if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) { - struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); - - disable_percpu_irq(drvdata->irq); - trbe_reset_local(cpudata); - } + if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) + arm_trbe_disable_cpu(drvdata); return 0; } -- 2.33.0

2 years

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