CoreSight

coresight@lists.linaro.org

9 participants
2378 discussions

[PATCH v1 0/9] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val This series applies to coresight/next https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git?h=next This patch series depends on patch series "[v12,0/9] Coresight: Add support for TPDM and TPDA" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221114144027.… Tao Zhang (9): dt-bindings: arm: Add support for DSB element coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb element creation coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request .../bindings/arm/qcom,coresight-tpda.yaml | 9 + drivers/hwtracing/coresight/coresight-tpda.c | 62 ++ drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 630 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 65 +++ 5 files changed, 765 insertions(+), 5 deletions(-) -- 2.7.4

2 years, 7 months

Re: [PATCH v13 2/2] Documentation: Add document for UltraSoc SMB drivers

by hejunhao

Hi Bagas, On 2022/11/15 15:35, Bagas Sanjaya wrote: > On 11/15/22 14:33, hejunhao wrote: >> Hi Bagas, >> >> will apply the fix in next version. >> Thank you very much. >> > Please don't top-post, reply inline with appropriate context instead. > I had to trim all the below context as a result. Yes, I'm sorry for that. Best regards, Junhao.

2 years, 7 months

Re: [PATCH v13 0/2] Add support for UltraSoc System Memory Buffer

by hejunhao

Hi Bagas, On 2022/11/14 21:11, Bagas Sanjaya wrote: > On Mon, Nov 14, 2022 at 05:03:14PM +0800, Junhao He wrote: >> Add support for UltraSoc System Memory Buffer. >> > The cover letter message (aside changelogs) is short but LGTM. However, > for individual patches description, please write in imperative mood > (that is, no "This patch/commit does foo" but "Do foo" instead). > > Thanks. Yes, I will do that. Best regards, Junhao.

2 years, 7 months

Re: [PATCH v13 2/2] Documentation: Add document for UltraSoc SMB drivers

by hejunhao

Hi Bagas, will apply the fix in next version. Thank you very much. Best regards, Junhao. On 2022/11/14 21:57, Bagas Sanjaya wrote: > On Mon, Nov 14, 2022 at 05:03:16PM +0800, Junhao He wrote: >> diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst >> new file mode 100644 >> index 000000000000..b7fe3f5c7f53 >> --- /dev/null >> +++ b/Documentation/trace/coresight/ultrasoc-smb.rst >> @@ -0,0 +1,82 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +====================================== >> +UltraSoc - HW Assisted Tracing on SoC >> +====================================== >> + :Author: Qi Liu <liuqi115(a)huawei.com> >> + :Date: March 2022 >> + >> +Introduction >> +------------ >> + >> +UltraSoc SMB is a per SCCL(Super CPU Cluster) hardware, and it provides a >> +way to buffer and store CPU trace messages in a region of shared system >> +memory. SMB is plugged as a coresight sink device and the corresponding >> +trace generators (ETM) are plugged in as source devices. >> + >> +Sysfs files and directories >> +--------------------------- >> + >> +The SMB devices appear on the existing coresight bus alongside the other >> +coresight devices:: >> + >> + $# ls /sys/bus/coresight/devices/ >> + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 >> + >> +The ``ultra_smb<N>`` named SMB associated with SCCL.:: >> + >> + $# ls /sys/bus/coresight/devices/ultra_smb0 >> + enable_sink mgmt >> + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt >> + buf_size buf_status read_pos write_pos >> + >> +*Key file items are:-* >> + * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer register. >> + * ``write_pos``: Shows the value held by UltraSoc SMB Write Pointer register. >> + * ``buf_status``: Shows the value held by UltraSoc SMB status register. >> + BIT(0) is zero means buffer is empty. >> + * ``buf_size``: Shows the buffer size of each UltraSoc SMB device. > The key list above doesn't look right, so I have applied the fixup: > > ---- >8 ---- > > diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst > index b7fe3f5c7f53f7..5d0fa1a76b04d1 100644 > --- a/Documentation/trace/coresight/ultrasoc-smb.rst > +++ b/Documentation/trace/coresight/ultrasoc-smb.rst > @@ -30,11 +30,12 @@ The ``ultra_smb<N>`` named SMB associated with SCCL.:: > $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt > buf_size buf_status read_pos write_pos > > -*Key file items are:-* > +Key file items are: > + > * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer register. > * ``write_pos``: Shows the value held by UltraSoc SMB Write Pointer register. > * ``buf_status``: Shows the value held by UltraSoc SMB status register. > - BIT(0) is zero means buffer is empty. > + BIT(0) is zero means buffer is empty. > * ``buf_size``: Shows the buffer size of each UltraSoc SMB device. > > Firmware Bindings > >> + >> +Firmware Bindings >> +--------------------------- >> + >> +SMB device is only supported with ACPI, and ACPI binding of SMB device >> +describes SMB device indentifier, resource information and graph structure. >> + >> +SMB is identified by ACPI HID "HISI03A1", resource of device is declared using >> +the _CRS method. Each SMB must present two base address, the first one is the >> +configuration base address of SMB device, the second one is the 32bits base >> +address of shared system memory. >> + >> +examples:: >> + >> + Device(USMB) { \ >> + Name(_HID, "HISI03A1") \ >> + Name(_CRS, ResourceTemplate() { \ >> + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, NonCacheable, \ >> + ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \ >> + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, Cacheable, \ >> + ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \ >> + }) \ >> + Name(_DSD, Package() { \ >> + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \ >> + /* Use CoreSight Graph ACPI bindings to describe connections topology */ >> + Package() { \ >> + 0, \ >> + 1, \ >> + Package() { \ >> + 1, \ >> + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \ >> + 8, \ >> + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \ >> + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \ >> + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \ >> + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \ >> + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \ >> + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \ >> + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \ >> + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \ >> + } \ >> + } \ >> + }) \ >> + } > The rest of wordings also read a rather weird. What about below instead? > > ---- >8 ---- > > diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst > index 5d0fa1a76b04d1..eee32cbf90d2ea 100644 > --- a/Documentation/trace/coresight/ultrasoc-smb.rst > +++ b/Documentation/trace/coresight/ultrasoc-smb.rst > @@ -9,21 +9,21 @@ UltraSoc - HW Assisted Tracing on SoC > Introduction > ------------ > > -UltraSoc SMB is a per SCCL(Super CPU Cluster) hardware, and it provides a > +UltraSoc SMB is a per SCCL (Super CPU Cluster) hardware. It provides a > way to buffer and store CPU trace messages in a region of shared system > -memory. SMB is plugged as a coresight sink device and the corresponding > -trace generators (ETM) are plugged in as source devices. > +memory. The device acts as a coresight sink device and the > +corresponding trace generators (ETM) are attached as source devices. > > Sysfs files and directories > --------------------------- > > -The SMB devices appear on the existing coresight bus alongside the other > -coresight devices:: > +The SMB devices appear on the existing coresight bus alongside other > +devices:: > > $# ls /sys/bus/coresight/devices/ > ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 > > -The ``ultra_smb<N>`` named SMB associated with SCCL.:: > +The ``ultra_smb<N>`` names SMB device associated with SCCL.:: > > $# ls /sys/bus/coresight/devices/ultra_smb0 > enable_sink mgmt > @@ -32,24 +32,23 @@ The ``ultra_smb<N>`` named SMB associated with SCCL.:: > > Key file items are: > > - * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer register. > - * ``write_pos``: Shows the value held by UltraSoc SMB Write Pointer register. > - * ``buf_status``: Shows the value held by UltraSoc SMB status register. > - BIT(0) is zero means buffer is empty. > - * ``buf_size``: Shows the buffer size of each UltraSoc SMB device. > + * ``read_pos``: Shows the value on the read pointer register. > + * ``write_pos``: Shows the value on the write pointer register. > + * ``buf_status``: Shows the value on the status register. > + BIT(0) is zero value which means the buffer is empty. > + * ``buf_size``: Shows the buffer size of each device. > > Firmware Bindings > ---------------------------- > +----------------- > > -SMB device is only supported with ACPI, and ACPI binding of SMB device > -describes SMB device indentifier, resource information and graph structure. > +The device is only supported with ACPI. Its binding describes device > +identifier, resource information and graph structure. > > -SMB is identified by ACPI HID "HISI03A1", resource of device is declared using > -the _CRS method. Each SMB must present two base address, the first one is the > -configuration base address of SMB device, the second one is the 32bits base > -address of shared system memory. > +The device is identified as ACPI HID "HISI03A1". Device resources are allocated > +using the _CRS method. Each device must present two base address; the first one is the configuration base address of the device, the second one is the 32-bit > +base address of shared system memory. > > -examples:: > +Example:: > > Device(USMB) { \ > Name(_HID, "HISI03A1") \ > > Thanks. >

2 years, 7 months

Re: [PATCH v12 1/2] drivers/coresight: Add UltraSoc System Memory Buffer driver

by Suzuki K Poulose

On 11/11/2022 22:06, kernel test robot wrote: > Hi Junhao, > > I love your patch! Perhaps something to improve: > > [auto build test WARNING on soc/for-next] > [also build test WARNING on linus/master v6.1-rc4 next-20221111] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Junhao-He/Add-support-for-Ul… > base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next > patch link: https://lore.kernel.org/r/20221109135008.9485-2-hejunhao3%40huawei.com > patch subject: [PATCH v12 1/2] drivers/coresight: Add UltraSoc System Memory Buffer driver > config: arm64-randconfig-s033-20221111 > compiler: aarch64-linux-gcc (GCC) 12.1.0 > reproduce: > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # apt-get install sparse > # sparse version: v0.6.4-39-gce1a6720-dirty > # https://github.com/intel-lab-lkp/linux/commit/49ede03fd874b65deca5382ea84c3… > git remote add linux-review https://github.com/intel-lab-lkp/linux > git fetch --no-tags linux-review Junhao-He/Add-support-for-UltraSoc-System-Memory-Buffer/20221109-215158 > git checkout 49ede03fd874b65deca5382ea84c3377188136da > # save the config file > mkdir build_dir && cp config build_dir/.config > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/hwtracing/coresight/ > > If you fix the issue, kindly add following tag where applicable > | Reported-by: kernel test robot <lkp(a)intel.com> > > sparse warnings: (new ones prefixed by >>) >>> drivers/hwtracing/coresight/ultrasoc-smb.c:113:33: sparse: sparse: cast removes address space '__iomem' of expression >>> drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const * @@ got void [noderef] __iomem * @@ > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: expected void const * > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: got void [noderef] __iomem * >>> drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const * @@ got void [noderef] __iomem * @@ > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: expected void const * > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: got void [noderef] __iomem * > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void const * @@ got void [noderef] __iomem * @@ > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: expected void const * > drivers/hwtracing/coresight/ultrasoc-smb.c:354:17: sparse: got void [noderef] __iomem * >>> drivers/hwtracing/coresight/ultrasoc-smb.c:463:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void [noderef] __iomem *base @@ got void * @@ > drivers/hwtracing/coresight/ultrasoc-smb.c:463:14: sparse: expected void [noderef] __iomem *base > drivers/hwtracing/coresight/ultrasoc-smb.c:463:14: sparse: got void * > > vim +/__iomem +113 drivers/hwtracing/coresight/ultrasoc-smb.c > > 89 > 90 static ssize_t smb_read(struct file *file, char __user *data, size_t len, > 91 loff_t *ppos) > 92 { > 93 struct smb_drv_data *drvdata = container_of(file->private_data, > 94 struct smb_drv_data, miscdev); > 95 struct smb_data_buffer *sdb = &drvdata->sdb; > 96 struct device *dev = &drvdata->csdev->dev; > 97 ssize_t to_copy = 0; > 98 > 99 mutex_lock(&drvdata->mutex); > 100 > 101 if (!sdb->data_size) { > 102 smb_update_data_size(drvdata); > 103 if (!sdb->data_size) > 104 goto out; > 105 } > 106 > 107 to_copy = min(sdb->data_size, len); > 108 > 109 /* Copy parts of trace data when read pointer wrap around SMB buffer */ > 110 if (sdb->rd_offset + to_copy > sdb->buf_size) > 111 to_copy = sdb->buf_size - sdb->rd_offset; > 112 > > 113 if (copy_to_user(data, (void *)sdb->buf_base + sdb->rd_offset, > 114 to_copy)) { > 115 dev_dbg(dev, "Failed to copy data to user\n"); > 116 to_copy = -EFAULT; > 117 goto out; > 118 } > 119 Please could we replace this with copy_to_user_fromio() ? Suzuki

2 years, 7 months

[PATCH v15 0/8] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series: "[v5,00/14] coresight: Add new API to allocate trace source ID values" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221101163103.… "arm64: dts: qcom: sm8250: Add coresight components" https://patchwork.kernel.org/project/linux-arm-msm/patch/20221114091251.139… Changes from V14: 1. coresight-tpda: Add more comments in trace id function. 2. qcom,coresight-tpdm.yaml: Add more comments in description. 3. Push "arm64: dts: qcom: sm8250: Add coresight components" out this series. Mao Jinlong (8): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 129 +++++++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++++++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 173 ++++++++++++ drivers/hwtracing/coresight/Kconfig | 23 ++ drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 ++- drivers/hwtracing/coresight/coresight-tpda.c | 211 ++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 259 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 +++++ include/linux/coresight.h | 1 + 13 files changed, 1032 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

2 years, 7 months

[PATCH] arm64: dts: qcom: sm8250: Add coresight components

by Mao Jinlong

Add coresight components for sm8250. STM/ETM are added. Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 498 +++++++++++++++++++++++++++ 1 file changed, 498 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a5b62cadb129..80193bb3c478 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2729,6 +2729,504 @@ }; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = <&funnel_merg_in_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = <&funnel_merg_in_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel_in1_in_funnel_apss_merg: endpoint { + remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_merg_out_funnel_swao: endpoint { + remote-endpoint = <&funnel_swao_in_funnel_merg>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_out_funnel_merg>; + }; + }; + + port@1 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_cx_in_swao_out: endpoint { + remote-endpoint = <&replicator_swao_out_cx_in>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@6b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x06b04000 0 0x1000>; + reg-names = "funnel-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_swao_out_etf: endpoint { + remote-endpoint = <&etf_in_funnel_swao_out>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel_swao_in_funnel_merg: endpoint { + remote-endpoint= <&funnel_merg_out_funnel_swao>; + }; + }; + }; + + }; + + etf@6b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b05000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in_funnel_swao_out: endpoint { + remote-endpoint = <&funnel_swao_out_etf>; + }; + }; + }; + }; + + replicator@6b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06b06000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_swao_out_cx_in: endpoint { + remote-endpoint = <&replicator_cx_in_swao_out>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port { + funnel_apss_merg_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; + }; + }; + }; + }; + cdsp: remoteproc@8300000 { compatible = "qcom,sm8250-cdsp-pas"; reg = <0 0x08300000 0 0x10000>; -- 2.17.1

2 years, 7 months

Re: [PATCH v12 2/2] Documentation: Add document for UltraSoc SMB drivers

by hejunhao

Hi Yicong. On 2022/11/10 20:08, Yicong Yang wrote: > On 2022/11/9 21:50, Junhao He wrote: >> From: Qi Liu <liuqi115(a)huawei.com> >> >> This patch bring in documentation for UltraSoc SMB drivers. >> It simply describes the device, sysfs interface and the >> firmware bindings. >> >> Signed-off-by: Qi Liu <liuqi115(a)huawei.com> >> Signed-off-by: Junhao He <hejunhao3(a)huawei.com> >> --- >> .../sysfs-bus-coresight-devices-ultra_smb | 31 +++++++ >> .../trace/coresight/ultrasoc-smb.rst | 80 +++++++++++++++++++ >> 2 files changed, 111 insertions(+) >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> new file mode 100644 >> index 000000000000..deaefd508105 >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> @@ -0,0 +1,31 @@ >> +What: /sys/bus/coresight/devices/ultra_smb<N>/enable_sink >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (RW) Add/remove a SMB device from a trace path. There can be >> + multiple sources for a single SMB device. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_size >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the buffer size of each UltraSoc SMB device. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_status >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB status register. >> + BIT(0) is zero means buffer is empty. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/read_pos >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB Read Pointer register. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/write_pos >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB Write Pointer register. >> diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst >> new file mode 100644 >> index 000000000000..6d28ef0f6c88 >> --- /dev/null >> +++ b/Documentation/trace/coresight/ultrasoc-smb.rst >> @@ -0,0 +1,80 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +====================================== >> +UltraSoc - HW Assisted Tracing on SoC >> +====================================== >> + :Author: Qi Liu <liuqi115(a)huawei.com> >> + :Date: March 2022 >> + >> +Introduction >> +------------ >> + >> +UltraSoc SMB is a per SCCL(Super CPU Cluster) hardware, and it provides a >> +way to buffer and store CPU trace messages in a region of shared system >> +memory. SMB is plugged as a coresight sink device and the corresponding >> +trace generators (ETM) are plugged in as source devices. >> + >> +Sysfs files and directories >> +--------------------------- >> + >> +The SMB devices appear on the existing coresight bus alongside the other >> +coresight devices:: >> + >> + $# ls /sys/bus/coresight/devices/ >> + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 >> + >> +The ``ultra_smb<N>`` named SMB associated with SCCL.:: >> + >> + $# ls /sys/bus/coresight/devices/ultra_smb0 >> + enable_sink mgmt >> + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt >> + buf_size buf_status read_pos write_pos >> + >> +*Key file items are:-* >> + * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer register. >> + * ``write_pos``: Shows the value held by UltraSoc SMB Write Pointer register. >> + * ``buf_status``: Shows the value held by UltraSoc SMB status register. >> + BIT(0) is zero means buffer is empty. >> + * ``buf_size``: Shows the buffer size of each UltraSoc SMB device. >> + >> +Firmware Bindings >> +--------------------------- >> + >> +SMB device is only supported with ACPI, and ACPI binding of SMB device >> +describes SMB device indentifier, resource information and graph structure. >> + >> +SMB is identified by ACPI HID "HISI03A1", resource of device is declared using >> +the _CRS method. Each SMB must present two base address, the first one is the >> +configuration base address of SMB device, the second one is the base address of >> +shared system memory. >> + >> +examples:: >> + >> + Device(USMB) { \ >> + Name(_HID, "HISI03A1") \ >> + Name(_CRS, ResourceTemplate() { \ >> + MEM_RESRC(0x95100000, 0x951FFFFF, 0x100000) \ >> + MEM_RESRC(0x50000000, 0x53FFFFFF, 0x4000000) \ > I cannot find MEM_RESRC in ACPI Spec 6.4, any references? If it's a self defined macro just expand it here. > > btw, you need to cc linux-doc(a)vger.kernel.org. > > Thanks. "MEM_RESERVE" is a macro. will update the doc and add cc. Thanks for the comments! >> + }) \ >> + Name(_DSD, Package() { \ >> + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \ >> + /* Use CoreSight Graph ACPI bindings to describe connections topology */ >> + Package() { \ >> + 0, \ >> + 1, \ >> + Package() { \ >> + 1, \ >> + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \ >> + 8, \ >> + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \ >> + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \ >> + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \ >> + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \ >> + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \ >> + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \ >> + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \ >> + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \ >> + } \ >> + } \ >> + }) \ >> + } >> > . > Best regards, Junhao.

2 years, 7 months

Re: [PATCH v12 1/2] drivers/coresight: Add UltraSoc System Memory Buffer driver

by hejunhao

Hi Yicong, Thanks for your comments. On 2022/11/10 20:05, Yicong Yang wrote: > Hi Junhao, > > On 2022/11/9 21:50, Junhao He wrote: >> From: Qi Liu <liuqi115(a)huawei.com> >> >> This patch adds driver for UltraSoc SMB(System Memory Buffer) >> device. SMB provides a way to buffer messages from ETM, and >> store these "CPU instructions trace" in system memory. >> >> SMB is developed by UltraSoc technology, which is acquired by >> Siemens, and we still use "UltraSoc" to name driver. >> > Some comments inline. > >> Signed-off-by: Qi Liu <liuqi115(a)huawei.com> >> Signed-off-by: Junhao He <hejunhao3(a)huawei.com> >> Tested-by: JunHao He <hejunhao3(a)huawei.com> >> --- >> drivers/hwtracing/coresight/Kconfig | 11 + >> drivers/hwtracing/coresight/Makefile | 1 + >> drivers/hwtracing/coresight/ultrasoc-smb.c | 635 +++++++++++++++++++++ >> drivers/hwtracing/coresight/ultrasoc-smb.h | 116 ++++ >> 4 files changed, 763 insertions(+) >> create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c >> create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h >> >> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig >> index 45c1eb5dfcb7..cb17c207a728 100644 >> --- a/drivers/hwtracing/coresight/Kconfig >> +++ b/drivers/hwtracing/coresight/Kconfig >> @@ -201,4 +201,15 @@ config CORESIGHT_TRBE >> >> To compile this driver as a module, choose M here: the module will be >> called coresight-trbe. >> + >> +config ULTRASOC_SMB >> + tristate "Ultrasoc system memory buffer drivers" >> + depends on ARM64 && CORESIGHT_LINKS_AND_SINKS >> + help >> + This driver provides support for the Ultrasoc system memory buffer (SMB). >> + SMB is responsible for receiving the trace data from Coresight ETM devices >> + and storing them to a system buffer. >> + >> + To compile this driver as a module, choose M here: the module will be >> + called ultrasoc-smb. >> endif >> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile >> index b6c4a48140ec..344dba8d6ff8 100644 >> --- a/drivers/hwtracing/coresight/Makefile >> +++ b/drivers/hwtracing/coresight/Makefile >> @@ -27,3 +27,4 @@ obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o >> obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o >> coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ >> coresight-cti-sysfs.o >> +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o >> diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c >> new file mode 100644 >> index 000000000000..ea2552a98d28 >> --- /dev/null >> +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c >> @@ -0,0 +1,635 @@ >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >> +/* >> + * Siemens System Memory Buffer driver. >> + * Copyright(c) 2022, HiSilicon Limited. >> + */ >> + >> +#include <linux/atomic.h> >> +#include <linux/acpi.h> >> +#include <linux/circ_buf.h> >> +#include <linux/err.h> >> +#include <linux/fs.h> >> +#include <linux/module.h> >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> + >> +#include "coresight-etm-perf.h" >> +#include "coresight-priv.h" >> +#include "ultrasoc-smb.h" >> + >> +DEFINE_CORESIGHT_DEVLIST(sink_devs, "ultra_smb"); >> + >> +#define ULTRASOC_SMB_DSM_UUID "82ae1283-7f6a-4cbe-aa06-53e8fb24db18" >> + >> +static bool smb_buffer_is_empty(struct smb_drv_data *drvdata) >> +{ >> + u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS_REG); >> + >> + return !FIELD_PREP(SMB_LB_INT_STS_NOT_EMPTY_MSK, buf_status); > Should be FIELD_GET() here? Sure, Will fix in next version. >> +} >> + >> +static void smb_buffer_sync_status(struct smb_drv_data *drvdata) >> +{ >> + struct smb_data_buffer *sdb = &drvdata->sdb; >> + >> + sdb->wr_offset = readl(drvdata->base + SMB_LB_WR_ADDR_REG) - sdb->start_addr; >> + sdb->rd_offset = readl(drvdata->base + SMB_LB_RD_ADDR_REG) - sdb->start_addr; >> + sdb->full = sdb->wr_offset == sdb->rd_offset && !smb_buffer_is_empty(drvdata); > Mistake here? Why to overwrite wr_offset? Here is a comparison of "wr_offset". It maybe too width, I will split the line. >> +} >> + >> +static void smb_reset_buffer_status(struct smb_drv_data *drvdata) >> +{ >> + writel(SMB_LB_INT_BUF_STS_RESET, drvdata->base + SMB_LB_INT_STS_REG); > You'll reset other fields of SMB_LB_INT_STS_REG since SMB_LB_INT_BUF_STS_RESET is only > BIT [3, 0], if it's not intended I'd suggest to only update the necessary fields. So is > other places. Other bits are reserved. For simpler code, we can configure all the REG bits. And I will add a comment here. >> +} >> + >> +/* Purge data remaining in hardware path in case them influence next trace */ >> +static void smb_purge_data(struct smb_drv_data *drvdata) >> +{ >> + writel(SMB_LB_PURGE_PURGED, drvdata->base + SMB_LB_PURGE_REG); >> +} >> + >> +static void smb_update_data_size(struct smb_drv_data *drvdata) >> +{ >> + struct smb_data_buffer *sdb = &drvdata->sdb; >> + >> + smb_purge_data(drvdata); >> + smb_buffer_sync_status(drvdata); >> + if (sdb->full) { >> + sdb->data_size = sdb->buf_size; >> + return; >> + } >> + >> + sdb->data_size = CIRC_CNT(sdb->wr_offset, sdb->rd_offset, sdb->buf_size); >> +} >> + >> +static int smb_open(struct inode *inode, struct file *file) >> +{ >> + struct smb_drv_data *drvdata = container_of(file->private_data, >> + struct smb_drv_data, miscdev); >> + int ret = 0; >> + >> + mutex_lock(&drvdata->mutex); >> + >> + if (local_read(&drvdata->reading)) { >> + ret = -EBUSY; >> + goto out; >> + } >> + >> + if (atomic_read(drvdata->csdev->refcnt)) { >> + ret = -EBUSY; >> + goto out; >> + } >> + >> + local_set(&drvdata->reading, 1); >> +out: >> + mutex_unlock(&drvdata->mutex); >> + >> + return ret; >> +} >> + >> +static ssize_t smb_read(struct file *file, char __user *data, size_t len, >> + loff_t *ppos) >> +{ >> + struct smb_drv_data *drvdata = container_of(file->private_data, >> + struct smb_drv_data, miscdev); >> + struct smb_data_buffer *sdb = &drvdata->sdb; >> + struct device *dev = &drvdata->csdev->dev; >> + ssize_t to_copy = 0; >> + >> + mutex_lock(&drvdata->mutex); >> + >> + if (!sdb->data_size) { >> + smb_update_data_size(drvdata); >> + if (!sdb->data_size) >> + goto out; >> + } >> + > It'd be better to check this earlier in open(). When SMB is full, If the data has been read and the "rd_offset" and "wr_offset" are not equal, the data remained in the link can be purged. So we need to dynamically update the data size in sysfs mode, and make sure to read all data. >> + to_copy = min(sdb->data_size, len); >> + >> + /* Copy parts of trace data when read pointer wrap around SMB buffer */ >> + if (sdb->rd_offset + to_copy > sdb->buf_size) >> + to_copy = sdb->buf_size - sdb->rd_offset; >> + >> + if (copy_to_user(data, (void *)sdb->buf_base + sdb->rd_offset, >> + to_copy)) { >> + dev_dbg(dev, "Failed to copy data to user\n"); >> + to_copy = -EFAULT; >> + goto out; >> + } >> + >> + *ppos += to_copy; >> + sdb->data_size -= to_copy; >> + sdb->rd_offset += to_copy; >> + sdb->rd_offset %= sdb->buf_size; >> + writel(sdb->start_addr + sdb->rd_offset, >> + drvdata->base + SMB_LB_RD_ADDR_REG); >> + dev_dbg(dev, "%zu bytes copied\n", to_copy); >> +out: >> + if (!sdb->data_size) >> + smb_reset_buffer_status(drvdata); >> + mutex_unlock(&drvdata->mutex); >> + >> + return to_copy; >> +} >> + >> +static int smb_release(struct inode *inode, struct file *file) >> +{ >> + struct smb_drv_data *drvdata = container_of(file->private_data, >> + struct smb_drv_data, miscdev); >> + >> + mutex_lock(&drvdata->mutex); >> + local_set(&drvdata->reading, 0); >> + mutex_unlock(&drvdata->mutex); >> + >> + return 0; >> +} >> + >> +static const struct file_operations smb_fops = { >> + .owner = THIS_MODULE, >> + .open = smb_open, >> + .read = smb_read, >> + .release = smb_release, >> + .llseek = no_llseek, >> +}; >> + >> +static ssize_t buf_size_show(struct device *dev, struct device_attribute *attr, >> + char *buf) >> +{ >> + struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent); >> + >> + return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size); > Need to update the data size before sysfs_emit(). This value does not change after SMB driver probe. >> +} >> +static DEVICE_ATTR_RO(buf_size); >> + >> +static struct attribute *smb_sink_attrs[] = { >> + coresight_simple_reg32(read_pos, SMB_LB_RD_ADDR_REG), >> + coresight_simple_reg32(write_pos, SMB_LB_WR_ADDR_REG), >> + coresight_simple_reg32(buf_status, SMB_LB_INT_STS_REG), >> + &dev_attr_buf_size.attr, >> + NULL >> +}; >> + >> +static const struct attribute_group smb_sink_group = { >> + .attrs = smb_sink_attrs, >> + .name = "mgmt", >> +}; >> + >> +static const struct attribute_group *smb_sink_groups[] = { >> + &smb_sink_group, >> + NULL >> +}; >> + >> +static void smb_enable_hw(struct smb_drv_data *drvdata) >> +{ >> + writel(SMB_GLB_EN_HW_ENABLE, drvdata->base + SMB_GLB_EN_REG); >> +} >> + >> +static void smb_disable_hw(struct smb_drv_data *drvdata) >> +{ >> + writel(0x0, drvdata->base + SMB_GLB_EN_REG); >> +} >> + >> +static void smb_enable_sysfs(struct coresight_device *csdev) >> +{ >> + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> + >> + if (drvdata->mode != CS_MODE_DISABLED) >> + return; >> + >> + smb_enable_hw(drvdata); >> + drvdata->mode = CS_MODE_SYSFS; >> +} >> + >> +static int smb_enable_perf(struct coresight_device *csdev, void *data) >> +{ >> + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> + struct perf_output_handle *handle = data; >> + struct cs_buffers *buf = etm_perf_sink_config(handle); >> + pid_t pid; >> + >> + if (!buf) >> + return -EINVAL; >> + >> + /* Get a handle on the pid of the target process */ >> + pid = buf->pid; >> + >> + /* Device is already in used by other session */ >> + if (drvdata->pid != -1 && drvdata->pid != pid) >> + return -EBUSY; >> + >> + if (drvdata->pid == -1) { >> + smb_enable_hw(drvdata); >> + drvdata->pid = pid; >> + drvdata->mode = CS_MODE_PERF; >> + } >> + >> + return 0; >> +} >> + >> +static int smb_enable(struct coresight_device *csdev, u32 mode, void *data) >> +{ >> + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> + int ret = 0; >> + >> + mutex_lock(&drvdata->mutex); >> + >> + /* Do nothing, the trace data is reading by other interface now */ >> + if (local_read(&drvdata->reading)) { >> + ret = -EBUSY; >> + goto out; >> + } >> + >> + /* Do nothing, the SMB is already enabled as other mode */ >> + if (drvdata->mode != CS_MODE_DISABLED && drvdata->mode != mode) { >> + ret = -EBUSY; >> + goto out; >> + } >> + >> + switch (mode) { >> + case CS_MODE_SYSFS: >> + smb_enable_sysfs(csdev); >> + break; >> + case CS_MODE_PERF: >> + ret = smb_enable_perf(csdev, data); >> + break; >> + default: >> + ret = -EINVAL; >> + } >> + >> + if (ret) >> + goto out; >> + >> + atomic_inc(csdev->refcnt); >> + >> + dev_dbg(&csdev->dev, "Ultrasoc SMB enabled\n"); >> +out: >> + mutex_unlock(&drvdata->mutex); >> + >> + return ret; >> +} >> + >> +static int smb_disable(struct coresight_device *csdev) >> +{ >> + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> + int ret = 0; >> + >> + mutex_lock(&drvdata->mutex); >> + >> + if (local_read(&drvdata->reading)) { >> + ret = -EBUSY; >> + goto out; >> + } >> + >> + if (atomic_dec_return(csdev->refcnt)) { >> + ret = -EBUSY; >> + goto out; >> + } >> + >> + /* Complain if we (somehow) got out of sync */ >> + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); > Is there any conditions we can reach here? I see we always update > drvdata->mode within the mutex's protection. To be the same as other coresight sink driver. >> + >> + smb_disable_hw(drvdata); >> + smb_purge_data(drvdata); >> + >> + /* Dissociate from the target process. */ >> + drvdata->pid = -1; >> + drvdata->mode = CS_MODE_DISABLED; >> + >> + dev_dbg(&csdev->dev, "Ultrasoc SMB disabled\n"); >> +out: >> + mutex_unlock(&drvdata->mutex); >> + >> + return ret; >> +} >> + >> +static void *smb_alloc_buffer(struct coresight_device *csdev, >> + struct perf_event *event, void **pages, >> + int nr_pages, bool overwrite) >> +{ >> + struct cs_buffers *buf; >> + int node; >> + >> + node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); >> + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); >> + if (!buf) >> + return NULL; >> + >> + buf->snapshot = overwrite; >> + buf->nr_pages = nr_pages; >> + buf->data_pages = pages; >> + buf->pid = task_pid_nr(event->owner); >> + >> + return buf; >> +} >> + >> +static void smb_free_buffer(void *config) >> +{ >> + struct cs_buffers *buf = config; >> + >> + kfree(buf); >> +} >> + >> +static void smb_sync_perf_buffer(struct smb_drv_data *drvdata, >> + struct cs_buffers *buf, >> + unsigned long head, >> + unsigned long data_size) >> +{ >> + struct smb_data_buffer *sdb = &drvdata->sdb; >> + char **dst_pages = (char **)buf->data_pages; >> + unsigned long to_copy; >> + long pg_idx, pg_offset; >> + >> + pg_idx = head >> PAGE_SHIFT; >> + pg_offset = head & (PAGE_SIZE - 1); >> + >> + while (data_size) { >> + unsigned long pg_space = PAGE_SIZE - pg_offset; >> + >> + /* Copy parts of trace data when read pointer wrap around */ >> + if (sdb->rd_offset + pg_space > sdb->buf_size) >> + to_copy = sdb->buf_size - sdb->rd_offset; >> + else >> + to_copy = min(data_size, pg_space); >> + >> + memcpy(dst_pages[pg_idx] + pg_offset, >> + sdb->buf_base + sdb->rd_offset, to_copy); >> + >> + pg_offset += to_copy; >> + if (pg_offset >= PAGE_SIZE) { >> + pg_offset = 0; >> + pg_idx++; >> + pg_idx %= buf->nr_pages; >> + } >> + data_size -= to_copy; >> + sdb->rd_offset += to_copy; >> + sdb->rd_offset %= sdb->buf_size; >> + } >> + >> + sdb->data_size = 0; >> + writel(sdb->start_addr + sdb->rd_offset, drvdata->base + SMB_LB_RD_ADDR_REG); >> + >> + /* >> + * Data remained in link cannot be purged when SMB is full, so >> + * synchronize the read pointer to write pointer, to make sure >> + * these remained data won't influence next trace. >> + */ >> + if (sdb->full) { >> + smb_purge_data(drvdata); >> + writel(readl(drvdata->base + SMB_LB_WR_ADDR_REG), >> + drvdata->base + SMB_LB_RD_ADDR_REG); >> + } >> + smb_reset_buffer_status(drvdata); >> +} >> + >> +static unsigned long smb_update_buffer(struct coresight_device *csdev, >> + struct perf_output_handle *handle, >> + void *sink_config) >> +{ >> + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> + struct smb_data_buffer *sdb = &drvdata->sdb; >> + struct cs_buffers *buf = sink_config; >> + unsigned long data_size = 0; >> + bool lost = false; >> + >> + if (!buf) >> + return 0; >> + >> + mutex_lock(&drvdata->mutex); >> + >> + /* Don't do anything if another tracer is using this sink. */ >> + if (atomic_read(csdev->refcnt) != 1) >> + goto out; >> + >> + smb_disable_hw(drvdata); >> + smb_update_data_size(drvdata); >> + data_size = sdb->data_size; >> + >> + /* >> + * The SMB buffer may be bigger than the space available in the >> + * perf ring buffer (handle->size). If so advance the offset so >> + * that we get the latest trace data. >> + */ >> + if (data_size > handle->size) { >> + sdb->rd_offset += data_size - handle->size; >> + sdb->rd_offset %= sdb->buf_size; >> + data_size = handle->size; >> + lost = true; >> + } >> + >> + smb_sync_perf_buffer(drvdata, buf, handle->head, data_size); >> + if (!buf->snapshot && lost) >> + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); >> + >> + smb_enable_hw(drvdata); >> +out: >> + mutex_unlock(&drvdata->mutex); >> + >> + return data_size; >> +} >> + >> +static const struct coresight_ops_sink smb_cs_ops = { >> + .enable = smb_enable, >> + .disable = smb_disable, >> + .alloc_buffer = smb_alloc_buffer, >> + .free_buffer = smb_free_buffer, >> + .update_buffer = smb_update_buffer, >> +}; >> + >> +static const struct coresight_ops cs_ops = { >> + .sink_ops = &smb_cs_ops, >> +}; >> + >> +static int smb_init_data_buffer(struct platform_device *pdev, >> + struct smb_data_buffer *sdb) >> +{ >> + struct resource *res; >> + void __iomem *base; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, SMB_BUF_ADDR_RES); >> + if (IS_ERR(res)) { >> + dev_err(&pdev->dev, "SMB device failed to get resource\n"); >> + return -EINVAL; >> + } >> + >> + sdb->start_addr = FIELD_PREP(SMB_BUF_ADDR_LO_MSK, res->start); > also FIELD_GET()? Sure, Will fix in next version. >> + sdb->buf_size = resource_size(res); >> + if (sdb->buf_size == 0) >> + return -EINVAL; >> + >> + /* >> + * This is a chunk of memory, use classic mapping with better >> + * performance. >> + */ >> + base = devm_memremap(&pdev->dev, sdb->start_addr, sdb->buf_size, >> + MEMREMAP_WB); >> + if (IS_ERR(base)) >> + return PTR_ERR(base); >> + >> + sdb->buf_base = base; >> + >> + return 0; >> +} >> + >> +static void smb_init_hw(struct smb_drv_data *drvdata) >> +{ >> + /* First disable SMB and clear the status of SMB buffer */ >> + smb_reset_buffer_status(drvdata); >> + smb_disable_hw(drvdata); >> + smb_purge_data(drvdata); >> + >> + writel(SMB_LB_CFG_LO_DEFAULT, drvdata->base + SMB_LB_CFG_LO_REG); >> + writel(SMB_LB_CFG_HI_DEFAULT, drvdata->base + SMB_LB_CFG_HI_REG); >> + writel(SMB_GLB_CFG_DEFAULT, drvdata->base + SMB_GLB_CFG_REG); >> + writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLB_INT_REG); >> + writel(SMB_LB_INT_CTRL_CFG, drvdata->base + SMB_LB_INT_CTRL_REG); >> +} >> + >> +static int smb_register_sink(struct platform_device *pdev, >> + struct smb_drv_data *drvdata) >> +{ >> + struct coresight_platform_data *pdata = NULL; >> + struct coresight_desc desc = { 0 }; >> + int ret; >> + >> + pdata = coresight_get_platform_data(&pdev->dev); >> + if (IS_ERR(pdata)) >> + return PTR_ERR(pdata); >> + >> + desc.type = CORESIGHT_DEV_TYPE_SINK; >> + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; >> + desc.ops = &cs_ops; >> + desc.pdata = pdata; >> + desc.dev = &pdev->dev; >> + desc.groups = smb_sink_groups; >> + desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev); >> + if (!desc.name) { >> + dev_err(&pdev->dev, "Failed to alloc coresight device name"); >> + return -ENOMEM; >> + } >> + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); >> + >> + drvdata->csdev = coresight_register(&desc); >> + if (IS_ERR(drvdata->csdev)) >> + return PTR_ERR(drvdata->csdev); >> + >> + drvdata->miscdev.name = desc.name; >> + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; >> + drvdata->miscdev.fops = &smb_fops; >> + ret = misc_register(&drvdata->miscdev); >> + if (ret) { >> + coresight_unregister(drvdata->csdev); >> + dev_err(&pdev->dev, "Failed to register misc, ret=%d\n", ret); >> + } >> + >> + return ret; >> +} >> + >> +static void smb_unregister_sink(struct smb_drv_data *drvdata) >> +{ >> + misc_deregister(&drvdata->miscdev); >> + coresight_unregister(drvdata->csdev); >> +} >> + >> +static int smb_config_inport(struct device *dev, bool enable) >> +{ >> + u64 func = enable ? 1 : 0; >> + union acpi_object *obj; >> + guid_t guid; >> + u64 rev = 0; >> + >> + /* >> + * Using DSM calls to enable/disable ultrasoc hardwares on >> + * tracing path, to prevent ultrasoc packet format being exposed. >> + */ >> + if (guid_parse(ULTRASOC_SMB_DSM_UUID, &guid)) { >> + dev_err(dev, "Get GUID failed\n"); >> + return -EINVAL; >> + } >> + >> + obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, rev, func, NULL); >> + if (!obj) >> + dev_err(dev, "ACPI handle failed\n"); >> + else >> + ACPI_FREE(obj); >> + >> + return 0; >> +} >> + >> +static int smb_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + struct smb_drv_data *drvdata; >> + int ret; >> + >> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); >> + if (!drvdata) >> + return -ENOMEM; >> + >> + drvdata->base = devm_platform_ioremap_resource(pdev, SMB_REG_ADDR_RES); >> + if (IS_ERR(drvdata->base)) { >> + dev_err(dev, "Failed to ioremap resource\n"); >> + return PTR_ERR(drvdata->base); >> + } >> + >> + ret = smb_init_data_buffer(pdev, &drvdata->sdb); >> + if (ret) { >> + dev_err(dev, "Failed to init buffer, ret = %d\n", ret); >> + return ret; >> + } >> + >> + smb_init_hw(drvdata); >> + mutex_init(&drvdata->mutex); >> + drvdata->pid = -1; >> + >> + ret = smb_register_sink(pdev, drvdata); >> + if (ret) { >> + dev_err(dev, "Failed to register SMB sink\n"); >> + return ret; >> + } >> + >> + ret = smb_config_inport(dev, true); >> + if (ret) { >> + smb_unregister_sink(drvdata); >> + return ret; >> + } >> + >> + platform_set_drvdata(pdev, drvdata); >> + >> + return 0; >> +} >> + >> +static int smb_remove(struct platform_device *pdev) >> +{ >> + struct smb_drv_data *drvdata = platform_get_drvdata(pdev); >> + int ret; >> + >> + ret = smb_config_inport(&pdev->dev, false); >> + if (ret) >> + return ret; >> + >> + smb_unregister_sink(drvdata); >> + >> + return 0; >> +} >> + >> +static const struct acpi_device_id ultrasoc_smb_acpi_match[] = { >> + {"HISI03A1", 0}, >> + {} >> +}; >> +MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match); >> + >> +static struct platform_driver smb_driver = { >> + .driver = { >> + .name = "ultrasoc-smb", >> + .acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match), >> + .suppress_bind_attrs = true, >> + }, >> + .probe = smb_probe, >> + .remove = smb_remove, >> +}; >> +module_platform_driver(smb_driver); >> + >> +MODULE_DESCRIPTION("UltraSoc SMB CoreSight driver"); >> +MODULE_LICENSE("Dual MIT/GPL"); >> +MODULE_AUTHOR("Jonathan Zhou <jonathan.zhouwen(a)huawei.com>"); >> +MODULE_AUTHOR("Qi Liu <liuqi115(a)huawei.com>"); >> diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h >> new file mode 100644 >> index 000000000000..2e2f9f8fe54b >> --- /dev/null >> +++ b/drivers/hwtracing/coresight/ultrasoc-smb.h >> @@ -0,0 +1,116 @@ >> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ >> +/* >> + * Siemens System Memory Buffer driver. >> + * Copyright(c) 2022, HiSilicon Limited. >> + */ >> + >> +#ifndef _ULTRASOC_SMB_H >> +#define _ULTRASOC_SMB_H >> + >> +#include <linux/miscdevice.h> >> +#include <linux/mutex.h> >> + >> +/* Offset of SMB global registers */ >> +#define SMB_GLB_CFG_REG 0x00 >> +#define SMB_GLB_EN_REG 0x04 >> +#define SMB_GLB_INT_REG 0x08 >> + >> +/* Offset of SMB logical buffer registers */ >> +#define SMB_LB_CFG_LO_REG 0x40 >> +#define SMB_LB_CFG_HI_REG 0x44 >> +#define SMB_LB_INT_CTRL_REG 0x48 >> +#define SMB_LB_INT_STS_REG 0x4c >> +#define SMB_LB_RD_ADDR_REG 0x5c >> +#define SMB_LB_WR_ADDR_REG 0x60 >> +#define SMB_LB_PURGE_REG 0x64 >> + >> +/* Set global config register */ >> +#define SMB_CFG_BURST_LEN_MSK GENMASK(11, 4) >> +#define SMB_CFG_IDLE_PRD_MSK GENMASK(15, 12) >> +#define SMB_CFG_MEM_WR_MSK GENMASK(21, 16) >> +#define SMB_CFG_MEM_RD_MSK GENMASK(27, 22) >> +#define SMB_GLB_CFG_DEFAULT (FIELD_PREP(SMB_CFG_BURST_LEN_MSK, 0xf) | \ >> + FIELD_PREP(SMB_CFG_IDLE_PRD_MSK, 0xf) | \ >> + FIELD_PREP(SMB_CFG_MEM_WR_MSK, 0x3) | \ >> + FIELD_PREP(SMB_CFG_MEM_RD_MSK, 0x1b)) >> + >> +/* Set global interrupt control register */ >> +#define SMB_INT_EN BIT(0) >> +#define SMB_INT_PULSE BIT(1) /* Interrupt type: 1 - Pulse */ >> +#define SMB_INT_ACT_H BIT(2) /* Interrupt polarity: 1 - Active high */ >> +#define SMB_GLB_INT_CFG (SMB_INT_EN | SMB_INT_PULSE | SMB_INT_ACT_H) >> + >> +/* Set logical buffer config register lower 32 bits */ >> +#define SMB_CFG_LO_EN BIT(0) >> +#define SMB_CFG_LO_SINGLE_END BIT(1) >> +#define SMB_CFG_LO_INIT BIT(8) >> +#define SMB_CFG_LO_CONT BIT(11) >> +#define SMB_CFG_LO_FLOW_MSK GENMASK(19, 16) >> +#define SMB_LB_CFG_LO_DEFAULT (SMB_CFG_LO_EN | SMB_CFG_LO_SINGLE_END | \ >> + SMB_CFG_LO_INIT | SMB_CFG_LO_CONT | \ >> + FIELD_PREP(SMB_CFG_LO_FLOW_MSK, 0xf)) >> + >> +/* Set logical buffer config register upper 32 bits */ >> +#define SMB_CFG_HI_RANGE_UP_MSK GENMASK(15, 8) >> +#define SMB_LB_CFG_HI_DEFAULT FIELD_PREP(SMB_CFG_HI_RANGE_UP_MSK, 0xff) >> + >> +/* Set logical buffer interrupt control register */ >> +#define SMB_INT_CTRL_EN BIT(0) >> +#define SMB_INT_CTRL_BUF_NOTE_MSK GENMASK(11, 8) >> +#define SMB_LB_INT_CTRL_CFG (SMB_INT_CTRL_EN | \ >> + FIELD_PREP(SMB_INT_CTRL_BUF_NOTE_MSK, 0xf)) >> + >> +#define SMB_LB_INT_STS_NOT_EMPTY_MSK BIT(0) >> +#define SMB_LB_STS_RESET_MSK GENMASK(3, 0) >> +#define SMB_LB_INT_BUF_STS_RESET FIELD_PREP(SMB_LB_STS_RESET_MSK, 0xf) >> +#define SMB_LB_PURGE_PURGED BIT(0) >> +#define SMB_GLB_EN_HW_ENABLE BIT(0) >> + >> +#define SMB_REG_ADDR_RES 0 >> +#define SMB_BUF_ADDR_RES 1 >> +#define SMB_BUF_ADDR_LO_MSK GENMASK(31, 0) >> + >> +/** >> + * struct smb_data_buffer - Details of the buffer used by SMB >> + * @buf_base: Memory mapped base address of SMB. >> + * @start_addr: SMB buffer start Physical address. >> + * @buf_size: Size of the buffer. >> + * @data_size: Size of Trace data copy to userspace. >> + * @rd_offset: Offset of the read pointer in the buffer. >> + * @wr_offset: Offset of the write pointer in the buffer. >> + * @full: Trace data overflow. >> + */ >> +struct smb_data_buffer { >> + void __iomem *buf_base; > The backend of buffer is a chunk of memory, so I guess we don't need > this __iomem here. Sure, Will fix in next version. >> + u32 start_addr; > Is u32 enough if we're running on a 64bit platform? You can use phys_addr_t > instead since you comment it to be "start Physical address". The system buffer start physical address point is declared by ACPI using the _CRS method, and will holds to 32bit registers "..._RD_ADDR_REG" and "..._WRADDR_REG". The hardware specification limits the address range and does not need to be compatible with 64-bit addresses, and this address is guaranteed to be 32 bits in ACPI. So u32 can be used. >> + unsigned long buf_size; >> + unsigned long data_size; >> + unsigned long rd_offset; >> + unsigned long wr_offset; >> + bool full; >> +}; >> + >> +/** >> + * struct smb_drv_data - specifics associated to an SMB component >> + * @base: Memory mapped base address for SMB component. >> + * @csdev: Component vitals needed by the framework. >> + * @sdb: Data buffer for SMB. >> + * @miscdev: Specifics to handle "/dev/xyz.smb" entry. >> + * @mutex: Control data access to one at a time. >> + * @reading: Synchronise user space access to SMB buffer. >> + * @pid: Process ID of the process being monitored by the >> + * session that is using this component. >> + * @mode: how this SMB is being used, perf mode or sysfs mode. >> + */ >> +struct smb_drv_data { >> + void __iomem *base; >> + struct coresight_device *csdev; >> + struct smb_data_buffer sdb; >> + struct miscdevice miscdev; >> + struct mutex mutex; >> + local_t reading; > Why do we need to use local_t here? Considering the whole structure is > already protected by the mutex, maybe a boolean is enough? Yes, I will do that, the mutex already ensures "reading" consistency. > Thanks. > . > Best regards, Junhao.

2 years, 7 months

Re: [PATCH v12 2/2] Documentation: Add document for UltraSoc SMB drivers

by hejunhao

On 2022/11/10 0:57, Jonathan Cameron wrote: > On Wed, 9 Nov 2022 21:50:08 +0800 > Junhao He <hejunhao3(a)huawei.com> wrote: > >> From: Qi Liu <liuqi115(a)huawei.com> >> >> This patch bring in documentation for UltraSoc SMB drivers. >> It simply describes the device, sysfs interface and the >> firmware bindings. >> >> Signed-off-by: Qi Liu <liuqi115(a)huawei.com> >> Signed-off-by: Junhao He <hejunhao3(a)huawei.com> > LTGM > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> > > Thanks, > > Jonathan Hi Jonathan, Thanks for your review! Best regards, Junhao. >> --- >> .../sysfs-bus-coresight-devices-ultra_smb | 31 +++++++ >> .../trace/coresight/ultrasoc-smb.rst | 80 +++++++++++++++++++ >> 2 files changed, 111 insertions(+) >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> new file mode 100644 >> index 000000000000..deaefd508105 >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb >> @@ -0,0 +1,31 @@ >> +What: /sys/bus/coresight/devices/ultra_smb<N>/enable_sink >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (RW) Add/remove a SMB device from a trace path. There can be >> + multiple sources for a single SMB device. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_size >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the buffer size of each UltraSoc SMB device. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_status >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB status register. >> + BIT(0) is zero means buffer is empty. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/read_pos >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB Read Pointer register. >> + >> +What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/write_pos >> +Date: November 2022 >> +KernelVersion: 6.2 >> +Contact: Junhao He <hejunhao3(a)huawei.com> >> +Description: (Read) Shows the value held by UltraSoc SMB Write Pointer register. >> diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst >> new file mode 100644 >> index 000000000000..6d28ef0f6c88 >> --- /dev/null >> +++ b/Documentation/trace/coresight/ultrasoc-smb.rst >> @@ -0,0 +1,80 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +====================================== >> +UltraSoc - HW Assisted Tracing on SoC >> +====================================== >> + :Author: Qi Liu <liuqi115(a)huawei.com> >> + :Date: March 2022 >> + >> +Introduction >> +------------ >> + >> +UltraSoc SMB is a per SCCL(Super CPU Cluster) hardware, and it provides a >> +way to buffer and store CPU trace messages in a region of shared system >> +memory. SMB is plugged as a coresight sink device and the corresponding >> +trace generators (ETM) are plugged in as source devices. >> + >> +Sysfs files and directories >> +--------------------------- >> + >> +The SMB devices appear on the existing coresight bus alongside the other >> +coresight devices:: >> + >> + $# ls /sys/bus/coresight/devices/ >> + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 >> + >> +The ``ultra_smb<N>`` named SMB associated with SCCL.:: >> + >> + $# ls /sys/bus/coresight/devices/ultra_smb0 >> + enable_sink mgmt >> + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt >> + buf_size buf_status read_pos write_pos >> + >> +*Key file items are:-* >> + * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer register. >> + * ``write_pos``: Shows the value held by UltraSoc SMB Write Pointer register. >> + * ``buf_status``: Shows the value held by UltraSoc SMB status register. >> + BIT(0) is zero means buffer is empty. >> + * ``buf_size``: Shows the buffer size of each UltraSoc SMB device. >> + >> +Firmware Bindings >> +--------------------------- >> + >> +SMB device is only supported with ACPI, and ACPI binding of SMB device >> +describes SMB device indentifier, resource information and graph structure. >> + >> +SMB is identified by ACPI HID "HISI03A1", resource of device is declared using >> +the _CRS method. Each SMB must present two base address, the first one is the >> +configuration base address of SMB device, the second one is the base address of >> +shared system memory. >> + >> +examples:: >> + >> + Device(USMB) { \ >> + Name(_HID, "HISI03A1") \ >> + Name(_CRS, ResourceTemplate() { \ >> + MEM_RESRC(0x95100000, 0x951FFFFF, 0x100000) \ >> + MEM_RESRC(0x50000000, 0x53FFFFFF, 0x4000000) \ >> + }) \ >> + Name(_DSD, Package() { \ >> + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \ >> + /* Use CoreSight Graph ACPI bindings to describe connections topology */ >> + Package() { \ >> + 0, \ >> + 1, \ >> + Package() { \ >> + 1, \ >> + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \ >> + 8, \ >> + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \ >> + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \ >> + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \ >> + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \ >> + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \ >> + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \ >> + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \ >> + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \ >> + } \ >> + } \ >> + }) \ >> + } > . >

2 years, 7 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight