Re: [PATCH v5 3/9] coresight: tmc-etf: Add comment for store ordering

On 09/08/2021 12:14, Leo Yan wrote:

Since the function CS_LOCK() has contained memory barrier mb(), it ensures the visibility of the AUX trace data before updating the aux_head, thus it's needless to add any explicit barrier anymore.

Add comment to make clear for the barrier usage for ETF.

Signed-off-by: Leo Yan leo.yan@linaro.org

drivers/hwtracing/coresight/coresight-tmc-etf.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index cd0fb7bfba68..8debd4f40f06 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -553,6 +553,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, if (buf->snapshot) handle->head += to_read;

• /*

• * CS_LOCK() contains mb() so it can ensure visibility of the AUX trace
  

• * data before the aux_head is updated via perf_aux_output_end(), which
  

• * is expected by the perf ring buffer.
  

• */
  

  CS_LOCK(drvdata->base); out: spin_unlock_irqrestore(&drvdata->spinlock, flags);

I will queue this.

Thanks Suzuki