Dear Mathieu,
I will like to clarify more on the `mode` file found in the mgmt of one of the ETM drivers.
The following is from the Documentations found in Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
What: /sys/bus/coresight/devices/<memory_map>.etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing.
I am asking about the functionality of this file because I want to be able to see how my traces will differ when i change the mode.
I have tweaked different values in mode and I realized that if the value != 0, it will not trace my program instruction addresses. I will only retrieve instruction addresses from kernel symbols (CPU_do_idle is found to be the specific instruction delivered by the CPU)
This is the snippet of the decoded trace using ptm2human ( I am also trying to figure if the decoder is indeed decoding the correct instructions from the trace dumps):
Context - Context ID = 0x0, VMID = 0x0, Address - Instruction address 0xffffff800895af78, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff8008161594, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800898b3c0, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800898b3c4, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff80081615c8, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800895af80, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800895b024, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff80081260e0, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800855cbd0, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800855cbf4, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800855cbec, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff8008126104, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800855cbd0, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800855cbf4, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800855cbec, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800812611c, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800895b030, Instruction set Aarch32 (Thumb) Address - Instruction address 0xffffff800895b054, Instruction set Aarch32 (Thumb) Exception - exception type IRQ, address 0xffffff800895b054
I will also upload the decoded trace dumps of the above (mode manipulated dump) in ed002000_mode.log
On another topic, I find it extremely amusing that I am able to trace my simple program. However, according to the ETM options implemented, it should not be tracing any LDR/STR/conditional instructions yet I have found the decoded traces to only be tracing LDR and STR. I have attached the source code of my math program and both the decoded (ec036000.etf.log) and the trace dump (ec036000.etf.bin). To make viewing of the instructions better, please look at ec036000.etf_addr.log. A snippet of the decoded dump is found here:
Address - Instruction address 0x0000ffbefe7fc400, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555b9c, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555ba4, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bac, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bb4, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bbc, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bc4, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bcc, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bd4, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bdc, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555be4, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bec, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bf4, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555bfc, Instruction set Aarch32 (Thumb) Address - Instruction address 0x0000005555555c04, Instruction set Aarch32 (Thumb)
I am using gdb to compare the program instruction addresses against the trace instruction addresses.
I have also deactivated ASLR to ensure that the values are always comparable. A snippet of the instructions of my program using gdb is attached below:
|0x5555555b9c <main+500> add x8, x8, x10 |0x5555555ba0 <main+504> ldr x8, [x8] |0x5555555ba4 <main+508> ldr x10, [sp,#144] |0x5555555ba8 <main+512> and x10, x10, x13 |0x5555555bac <main+516> lsl x10, x12, x10 |0x5555555bb0 <main+520> and x8, x8, x10 |0x5555555bb4 <main+524> cmp x8, x9 |0x5555555bb8 <main+528> cset w15, ne |0x5555555bbc <main+532> orr w16, wzr, #0x1 |0x5555555bc0 <main+536> and w15, w15, w16 |0x5555555bc4 <main+540> str w15, [sp,#20] |0x5555555bc8 <main+544> b 0x5555555bd4 <main+556> |0x5555555bcc <main+548> mov w8, #0x0 // #0 |0x5555555bd0 <main+552> str w8, [sp,#20] |0x5555555bd4 <main+556> ldr w8, [sp,#20] |0x5555555bd8 <main+560> str w8, [sp,#140] |0x5555555bdc <main+564> ldr w8, [sp,#140] |0x5555555be0 <main+568> cbnz w8, 0x5555555be8 <main+576> |0x5555555be4 <main+572> b 0x5555555c80 <main+728> |0x5555555be8 <main+576> orr x0, xzr, #0x10 |0x5555555bec <main+580> orr w3, wzr, #0x4 |0x5555555bf0 <main+584> ldur w2, [x29,#-40] |0x5555555bf4 <main+588> ldr x8, [sp,#80] |0x5555555bf8 <main+592> str x0, [sp,#8] |0x5555555bfc <main+596> mov x0, x8 |0x5555555c00 <main+600> ldr x1, [sp,#72] |0x5555555c04 <main+604> bl 0x55555558d0 fprintf@plt
The following are the trcidr values of my ETM: trcidr0: 0x28000ea1 trcidr1: 0x4100f404 trcidr2: 0x488 trcidr3: 0xd7b00004 trcidr4: 0x11170004 trcidr5: 0x28c7081e trcidr8: 0x0 trcidr9: 0x0 trcidr10: 0x0 trcidr11: 0x0 trcidr12: 0x0 trcidr13: 0x0
Hope I have provided sufficient information. Please advise!
Yours Sincerely, Jeremy
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