On Tue, Aug 20, 2019 at 03:59:30PM -0600, Mathieu Poirier wrote:
On Fri, Aug 16, 2019 at 04:46:14PM +0100, Andrew Murray wrote:
Some coresight components, because of choices made during hardware integration, require their state to be saved and restored across CPU low power states.
The software has no reliable method of detecting when save/restore is required thus let's add a binding to inform the kernel.
Signed-off-by: Andrew Murray andrew.murray@arm.com
Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..d02c42d21f2f 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -87,6 +87,15 @@ its hardware characteristcs.
- port or ports: see "Graph bindings for Coresight" below.
+* Optional properties for all components:
- arm,coresight-loses-context-with-cpu : boolean. Indicates that the
hardware will lose register context on CPU power down (e.g. CPUIdle).An example of where this may be needed are systems which contain acoresight component and CPU in the same power domain. When the CPUpowers down the coresight component also powers down and loses itscontext. This property is currently only used for the ETM 4.x driver.Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
When you resend this set make sure to include the device tree mailing list as instructed by get_maintainer.pl. Since this set did not CC the DT list, none of the maintainers over there will look at your patches.
Sure I'll do that.
Thanks,
Andrew Murray
- Optional properties for ETM/PTMs:
- arm,cp14: must be present if the system accesses ETM/PTM management
-- 2.21.0