Common base class added for all the trace component configuration classes. Allows for baseline features plus generic manipulation of configuration register objects.
Separate commit to prevent git errors in thinking this is a rename
ETMv3, PTM, STM and ETMv4 configuration register classes now use common base class.
C-API struct now a member, rather than a base of the classes to improve encapsulation / allow for common base.
Minor mods to decoder code where access functions were needed in place of previous direct struct manipulation.
Update handling of STM, ETMv4 and PTM config objects in test program to reflect the changes to this set of classes - config struct no longer a base.
Signed-off-by: Mike Leach mike.leach@linaro.org --- decoder/include/common/trc_cs_config.h | 56 +++++++++++ decoder/include/etmv3/trc_cmp_cfg_etmv3.h | 6 +- decoder/include/etmv4/trc_cmp_cfg_etmv4.h | 102 +++++++++++---------- decoder/include/ptm/trc_cmp_cfg_ptm.h | 51 +++++++---- decoder/include/stm/trc_cmp_cfg_stm.h | 55 +++++++---- decoder/source/etmv4/trc_cmp_cfg_etmv4.cpp | 34 +++---- decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp | 2 +- decoder/source/ptm/trc_cmp_cfg_ptm.cpp | 17 ++-- decoder/source/ptm/trc_pkt_decode_ptm.cpp | 4 +- .../snapshot_parser_lib/source/ss_to_dcdtree.cpp | 24 +++-- 10 files changed, 232 insertions(+), 119 deletions(-) create mode 100644 decoder/include/common/trc_cs_config.h
diff --git a/decoder/include/common/trc_cs_config.h b/decoder/include/common/trc_cs_config.h new file mode 100644 index 0000000..58398f7 --- /dev/null +++ b/decoder/include/common/trc_cs_config.h @@ -0,0 +1,56 @@ +/* + * \file trc_cs_config.h + * \brief OpenCSD : Trace component config base class. + * + * \copyright Copyright (c) 2016, ARM Limited. All Rights Reserved. + */ +#ifndef ARM_TRC_CS_CONFIG_H_INCLUDED +#define ARM_TRC_CS_CONFIG_H_INCLUDED + + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @class CSConfig : Base class for configuration data on CoreSight trace component. + * + * Defines common access functionality, common to all components. + * (e.g. trace ID). + * + */ +class CSConfig +{ +public: + CSConfig() {}; + virtual ~CSConfig() {}; + + virtual const uint8_t getTraceID() const = 0; //!< CoreSight Trace ID for this device. +}; + +#endif // ARM_TRC_CS_CONFIG_H_INCLUDED + +/* End of File trc_cs_config.h */ \ No newline at end of file diff --git a/decoder/include/etmv3/trc_cmp_cfg_etmv3.h b/decoder/include/etmv3/trc_cmp_cfg_etmv3.h index f2da178..509de20 100644 --- a/decoder/include/etmv3/trc_cmp_cfg_etmv3.h +++ b/decoder/include/etmv3/trc_cmp_cfg_etmv3.h @@ -37,6 +37,8 @@ #define ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED
#include "trc_pkt_types_etmv3.h" +#include "common/trc_cs_config.h" +
/** @addtogroup ocsd_protocol_cfg @{*/ @@ -53,7 +55,7 @@ * Primarily inlined for efficient code. * */ -class EtmV3Config //: public ocsd_etmv3_cfg +class EtmV3Config : public CSConfig { public: EtmV3Config(); /**< Default constructor */ @@ -117,7 +119,7 @@ public: const bool isTSEnabled() const; //!< Timestamp trace is enabled. const bool TSPkt64() const; //!< timestamp packet is 64 bits in size.
- const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device. + virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device.
const ocsd_arch_version_t getArchVersion() const; //!< architecture version const ocsd_core_profile_t getCoreProfile() const; //!< core profile. diff --git a/decoder/include/etmv4/trc_cmp_cfg_etmv4.h b/decoder/include/etmv4/trc_cmp_cfg_etmv4.h index 48bb1af..a3f8835 100644 --- a/decoder/include/etmv4/trc_cmp_cfg_etmv4.h +++ b/decoder/include/etmv4/trc_cmp_cfg_etmv4.h @@ -37,7 +37,7 @@ #define ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
#include "trc_pkt_types_etmv4.h" - +#include "common/trc_cs_config.h"
/** @addtogroup ocsd_protocol_cfg @@ -53,17 +53,25 @@ * Provides quick value interpretation methods for the ETMv4 config register values. * Primarily inlined for efficient code. */ -class EtmV4Config : public ocsd_etmv4_cfg +class EtmV4Config : public CSConfig // public ocsd_etmv4_cfg { public: EtmV4Config(); /**< Default constructor */ + EtmV4Config(const ocsd_etmv4_cfg *cfg_regs); ~EtmV4Config() {}; /**< Default destructor */
+// operations to convert to and from C-API structure + //! copy assignment operator for base structure into class. EtmV4Config & operator=(const ocsd_etmv4_cfg *p_cfg);
- const ocsd_core_profile_t &coreProfile() const { return core_prof; }; - const ocsd_arch_version_t &archVersion() const { return arch_ver; }; + //! cast operator returning struct const reference + operator const ocsd_etmv4_cfg &() const { return m_cfg; }; + //! cast operator returning struct const pointer + operator const ocsd_etmv4_cfg *() const { return &m_cfg; }; + + const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; }; + const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; };
/* idr 0 */ const bool LSasInstP0() const; @@ -120,7 +128,7 @@ public: const uint32_t CondKeyMaxIncr() const;
/* trace idr */ - const uint8_t getTraceID() const; + virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device.
/* config R */ const bool enabledDVTrace() const; @@ -171,47 +179,49 @@ private:
bool m_condTraceCalc; CondITrace_t m_CondTrace; + + ocsd_etmv4_cfg m_cfg; };
/* idr 0 */ inline const bool EtmV4Config::LSasInstP0() const { - return (bool)((reg_idr0 & 0x6) == 0x6); + return (bool)((m_cfg.reg_idr0 & 0x6) == 0x6); }
inline const bool EtmV4Config::hasDataTrace() const { - return (bool)((reg_idr0 & 0x18) == 0x18); + return (bool)((m_cfg.reg_idr0 & 0x18) == 0x18); }
inline const bool EtmV4Config::hasBranchBroadcast() const { - return (bool)((reg_idr0 & 0x20) == 0x20); + return (bool)((m_cfg.reg_idr0 & 0x20) == 0x20); }
inline const bool EtmV4Config::hasCondTrace() const { - return (bool)((reg_idr0 & 0x40) == 0x40); + return (bool)((m_cfg.reg_idr0 & 0x40) == 0x40); }
inline const bool EtmV4Config::hasCycleCountI() const { - return (bool)((reg_idr0 & 0x80) == 0x80); + return (bool)((m_cfg.reg_idr0 & 0x80) == 0x80); }
inline const bool EtmV4Config::hasRetStack() const { - return (bool)((reg_idr0 & 0x200) == 0x200); + return (bool)((m_cfg.reg_idr0 & 0x200) == 0x200); }
inline const uint8_t EtmV4Config::numEvents() const { - return ((reg_idr0 >> 10) & 0x3) + 1; + return ((m_cfg.reg_idr0 >> 10) & 0x3) + 1; }
inline const EtmV4Config::condType EtmV4Config::hasCondType() const { - return ((reg_idr0 & 0x3000) == 0x1000) ? EtmV4Config::COND_HAS_ASPR : EtmV4Config::COND_PASS_FAIL; + return ((m_cfg.reg_idr0 & 0x3000) == 0x1000) ? EtmV4Config::COND_HAS_ASPR : EtmV4Config::COND_PASS_FAIL; }
inline const EtmV4Config::QSuppType EtmV4Config::getQSuppType() @@ -234,12 +244,12 @@ inline const bool EtmV4Config::hasQFilter()
inline const bool EtmV4Config::hasTrcExcpData() const { - return (bool)((reg_idr0 & 0x20000) == 0x20000); + return (bool)((m_cfg.reg_idr0 & 0x20000) == 0x20000); }
inline const uint32_t EtmV4Config::TimeStampSize() const { - uint32_t tsSizeF = (reg_idr0 >> 24) & 0x1F; + uint32_t tsSizeF = (m_cfg.reg_idr0 >> 24) & 0x1F; if(tsSizeF == 0x6) return 48; if(tsSizeF == 0x8) @@ -249,30 +259,30 @@ inline const uint32_t EtmV4Config::TimeStampSize() const
inline const bool EtmV4Config::commitOpt1() const { - return (bool)((reg_idr0 & 0x20000000) == 0x20000000) && hasCycleCountI(); + return (bool)((m_cfg.reg_idr0 & 0x20000000) == 0x20000000) && hasCycleCountI(); }
/* idr 1 */ inline const uint8_t EtmV4Config::MajVersion() const { - return (uint8_t)((reg_idr1 >> 8) & 0xF); + return (uint8_t)((m_cfg.reg_idr1 >> 8) & 0xF); }
inline const uint8_t EtmV4Config::MinVersion() const { - return (uint8_t)((reg_idr1 >> 4) & 0xF); + return (uint8_t)((m_cfg.reg_idr1 >> 4) & 0xF); }
/* idr 2 */ inline const uint32_t EtmV4Config::iaSizeMax() const { - return ((reg_idr2 & 0x1F) == 0x8) ? 64 : 32; + return ((m_cfg.reg_idr2 & 0x1F) == 0x8) ? 64 : 32; }
inline const uint32_t EtmV4Config::cidSize() const { - return (((reg_idr2 >> 5) & 0x1F) == 0x4) ? 32 : 0; + return (((m_cfg.reg_idr2 >> 5) & 0x1F) == 0x4) ? 32 : 0; }
inline const uint32_t EtmV4Config::vmidSize() @@ -286,81 +296,81 @@ inline const uint32_t EtmV4Config::vmidSize()
inline const uint32_t EtmV4Config::daSize() const { - uint32_t daSizeF = ((reg_idr2 >> 15) & 0x1F); + uint32_t daSizeF = ((m_cfg.reg_idr2 >> 15) & 0x1F); if(daSizeF) - return (((reg_idr2 >> 15) & 0x1F) == 0x8) ? 64 : 32; + return (((m_cfg.reg_idr2 >> 15) & 0x1F) == 0x8) ? 64 : 32; return 0; }
inline const uint32_t EtmV4Config::dvSize() const { - uint32_t dvSizeF = ((reg_idr2 >> 20) & 0x1F); + uint32_t dvSizeF = ((m_cfg.reg_idr2 >> 20) & 0x1F); if(dvSizeF) - return (((reg_idr2 >> 20) & 0x1F) == 0x8) ? 64 : 32; + return (((m_cfg.reg_idr2 >> 20) & 0x1F) == 0x8) ? 64 : 32; return 0; }
inline const uint32_t EtmV4Config::ccSize() const { - return ((reg_idr2 >> 25) & 0xF) + 12; + return ((m_cfg.reg_idr2 >> 25) & 0xF) + 12; }
inline const bool EtmV4Config::vmidOpt() const { - return (bool)((reg_idr2 & 0x20000000) == 0x20000000) && (MinVersion() > 0); + return (bool)((m_cfg.reg_idr2 & 0x20000000) == 0x20000000) && (MinVersion() > 0); }
/* id regs 8-13*/
inline const uint32_t EtmV4Config::MaxSpecDepth() const { - return reg_idr8; + return m_cfg.reg_idr8; }
inline const uint32_t EtmV4Config::P0_Key_Max() const { - return (reg_idr9 == 0) ? 1 : reg_idr9; + return (m_cfg.reg_idr9 == 0) ? 1 : m_cfg.reg_idr9; }
inline const uint32_t EtmV4Config::P1_Key_Max() const { - return reg_idr10; + return m_cfg.reg_idr10; }
inline const uint32_t EtmV4Config::P1_Spcl_Key_Max() const { - return reg_idr11; + return m_cfg.reg_idr11; }
inline const uint32_t EtmV4Config::CondKeyMax() const { - return reg_idr12; + return m_cfg.reg_idr12; }
inline const uint32_t EtmV4Config::CondSpecKeyMax() const { - return reg_idr13; + return m_cfg.reg_idr13; }
inline const uint32_t EtmV4Config::CondKeyMaxIncr() const { - return reg_idr12 - reg_idr13; + return m_cfg.reg_idr12 - m_cfg.reg_idr13; }
inline const uint8_t EtmV4Config::getTraceID() const { - return (uint8_t)(reg_traceidr & 0x7F); + return (uint8_t)(m_cfg.reg_traceidr & 0x7F); }
/* config R */ inline const bool EtmV4Config::enabledDVTrace() const { - return hasDataTrace() && enabledLSP0Trace() && ((reg_configr & (0x1 << 17)) != 0); + return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 17)) != 0); }
inline const bool EtmV4Config::enabledDATrace() const { - return hasDataTrace() && enabledLSP0Trace() && ((reg_configr & (0x1 << 16)) != 0); + return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 16)) != 0); }
inline const bool EtmV4Config::enabledDataTrace() const @@ -370,39 +380,39 @@ inline const bool EtmV4Config::enabledDataTrace() const
inline const bool EtmV4Config::enabledLSP0Trace() const { - return ((reg_configr & 0x6) != 0); + return ((m_cfg.reg_configr & 0x6) != 0); }
inline const EtmV4Config::LSP0_t EtmV4Config::LSP0Type() const { - return (LSP0_t)((reg_configr & 0x6) >> 1); + return (LSP0_t)((m_cfg.reg_configr & 0x6) >> 1); }
inline const bool EtmV4Config::enabledBrBroad() const { - return ((reg_configr & (0x1 << 3)) != 0); + return ((m_cfg.reg_configr & (0x1 << 3)) != 0); }
inline const bool EtmV4Config::enabledCCI() const { - return ((reg_configr & (0x1 << 4)) != 0); + return ((m_cfg.reg_configr & (0x1 << 4)) != 0); }
inline const bool EtmV4Config::enabledCID() const { - return ((reg_configr & (0x1 << 6)) != 0); + return ((m_cfg.reg_configr & (0x1 << 6)) != 0); }
inline const bool EtmV4Config::enabledVMID() const { - return ((reg_configr & (0x1 << 7)) != 0); + return ((m_cfg.reg_configr & (0x1 << 7)) != 0); }
inline const EtmV4Config::CondITrace_t EtmV4Config::enabledCondITrace() { if(!m_condTraceCalc) { - switch((reg_configr >> 8) & 0x7) + switch((m_cfg.reg_configr >> 8) & 0x7) { default: case 0: m_CondTrace = COND_TR_DIS; break; @@ -418,17 +428,17 @@ inline const EtmV4Config::CondITrace_t EtmV4Config::enabledCondITrace()
inline const bool EtmV4Config::enabledTS() const { - return ((reg_configr & (0x1 << 11)) != 0); + return ((m_cfg.reg_configr & (0x1 << 11)) != 0); }
inline const bool EtmV4Config::enabledRetStack() const { - return ((reg_configr & (0x1 << 12)) != 0); + return ((m_cfg.reg_configr & (0x1 << 12)) != 0); }
inline const bool EtmV4Config::enabledQE() const { - return ((reg_configr & (0x3 << 13)) != 0); + return ((m_cfg.reg_configr & (0x3 << 13)) != 0); }
/** @}*/ diff --git a/decoder/include/ptm/trc_cmp_cfg_ptm.h b/decoder/include/ptm/trc_cmp_cfg_ptm.h index e77f6aa..5a4dae2 100644 --- a/decoder/include/ptm/trc_cmp_cfg_ptm.h +++ b/decoder/include/ptm/trc_cmp_cfg_ptm.h @@ -37,6 +37,7 @@ #define ARM_TRC_CMP_CFG_PTM_H_INCLUDED
#include "trc_pkt_types_ptm.h" +#include "common/trc_cs_config.h"
/** @defgroup ocsd_protocol_cfg OpenCSD Library : Protcol Generator Configuration.
@@ -58,10 +59,11 @@ * Provides quick value interpretation methods for the PTM config register values. * Primarily inlined for efficient code. */ -class PtmConfig : public ocsd_ptm_cfg +class PtmConfig : public CSConfig // public ocsd_ptm_cfg { public: PtmConfig(); /**< Default constructor */ + PtmConfig(const ocsd_ptm_cfg *cfg_regs); ~PtmConfig() {}; /**< Default destructor */
/* register bit constants. */ @@ -79,9 +81,18 @@ public: static const uint32_t CCER_TS_ENC_NAT = (0x1 << 28); static const uint32_t CCER_TS_64BIT = (0x1 << 29);
+// operations to convert to and from C-API structure + //! copy assignment operator for base structure into class. PtmConfig & operator=(const ocsd_ptm_cfg *p_cfg);
+ //! cast operator returning struct const reference + operator const ocsd_ptm_cfg &() const { return m_cfg; }; + //! cast operator returning struct const pointer + operator const ocsd_ptm_cfg *() const { return &m_cfg; }; + +// access functions + const bool enaBranchBCast() const; //!< Branch broadcast enabled. const bool enaCycleAcc() const; //!< cycle accurate tracing enabled.
@@ -102,7 +113,13 @@ public: const bool dmsbGenTS() const; //!< TS generated for DMB and DSB const bool dmsbWayPt() const; //!< DMB and DSB are waypoint instructions.
- const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device. + virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device. + + const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; }; + const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; }; + +private: + ocsd_ptm_cfg m_cfg; };
/* inlines */ @@ -110,80 +127,80 @@ public: inline PtmConfig & PtmConfig::operator=(const ocsd_ptm_cfg *p_cfg) { // object of base class ocsd_ptm_cfg - *dynamic_cast<ocsd_ptm_cfg *>(this) = *p_cfg; + m_cfg = *p_cfg; return *this; }
inline const bool PtmConfig::enaBranchBCast() const { - return (bool)((reg_ctrl & CTRL_BRANCH_BCAST) != 0); + return (bool)((m_cfg.reg_ctrl & CTRL_BRANCH_BCAST) != 0); }
inline const bool PtmConfig::enaCycleAcc() const { - return (bool)((reg_ctrl & CTRL_CYCLEACC) != 0); + return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0); }
inline const bool PtmConfig::enaRetStack() const { - return (bool)((reg_ctrl & CTRL_RETSTACK_ENA) != 0); + return (bool)((m_cfg.reg_ctrl & CTRL_RETSTACK_ENA) != 0); }
inline const bool PtmConfig::hasRetStack() const { - return (bool)((reg_ccer & CCER_RESTACK_IMPL) != 0); + return (bool)((m_cfg.reg_ccer & CCER_RESTACK_IMPL) != 0); }
inline const int PtmConfig::MinorRev() const { - return ((int)reg_idr & 0xF0) >> 4; + return ((int)m_cfg.reg_idr & 0xF0) >> 4; }
inline const bool PtmConfig::hasTS() const { - return (bool)((reg_ccer & CCER_TS_IMPL) != 0); + return (bool)((m_cfg.reg_ccer & CCER_TS_IMPL) != 0); }
inline const bool PtmConfig::enaTS() const { - return (bool)((reg_ctrl & CTRL_TS_ENA) != 0); + return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0); }
inline const bool PtmConfig::TSPkt64() const { if(MinorRev() == 0) return false; - return (bool)((reg_ccer & CCER_TS_64BIT) != 0); + return (bool)((m_cfg.reg_ccer & CCER_TS_64BIT) != 0); }
inline const bool PtmConfig::TSBinEnc() const { if(MinorRev() == 0) return false; - return (bool)((reg_ccer & CCER_TS_ENC_NAT) != 0); + return (bool)((m_cfg.reg_ccer & CCER_TS_ENC_NAT) != 0); }
inline const bool PtmConfig::hasVirtExt() const { - return (bool)((reg_ccer & CCER_VIRTEXT) != 0); + return (bool)((m_cfg.reg_ccer & CCER_VIRTEXT) != 0); }
inline const bool PtmConfig::enaVMID() const { - return (bool)((reg_ctrl & CTRL_VMID_ENA) != 0); + return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0); }
inline const bool PtmConfig::dmsbGenTS() const { - return (bool)((reg_ccer & CCER_TS_DMSB) != 0); + return (bool)((m_cfg.reg_ccer & CCER_TS_DMSB) != 0); }
inline const bool PtmConfig::dmsbWayPt() const { - return (bool)((reg_ccer & CCER_DMSB_WPT) != 0); + return (bool)((m_cfg.reg_ccer & CCER_DMSB_WPT) != 0); }
inline const uint8_t PtmConfig::getTraceID() const { - return (uint8_t)(reg_trc_id & 0x7F); + return (uint8_t)(m_cfg.reg_trc_id & 0x7F); }
/** @}*/ diff --git a/decoder/include/stm/trc_cmp_cfg_stm.h b/decoder/include/stm/trc_cmp_cfg_stm.h index dbef0eb..41003ec 100644 --- a/decoder/include/stm/trc_cmp_cfg_stm.h +++ b/decoder/include/stm/trc_cmp_cfg_stm.h @@ -36,6 +36,7 @@ #define ARM_TRC_CMP_CFG_STM_H_INCLUDED
#include "trc_pkt_types_stm.h" +#include "common/trc_cs_config.h"
/** @addtogroup ocsd_protocol_cfg @{*/ @@ -56,17 +57,26 @@ * * Can also be initialised with a fully populated ocsd_stm_cfg structure. */ -class STMConfig : public ocsd_stm_cfg +class STMConfig : public CSConfig // public ocsd_stm_cfg { public: STMConfig(); //!< Constructor - creates a default configuration + STMConfig(const ocsd_stm_cfg *cfg_regs); ~STMConfig() {};
+// operations to convert to and from C-API structure + STMConfig & operator=(const ocsd_stm_cfg *p_cfg); //!< set from full configuration structure. + //! cast operator returning struct const reference + operator const ocsd_stm_cfg &() const { return m_cfg; }; + //! cast operator returning struct const pointer + operator const ocsd_stm_cfg *() const { return &m_cfg; }; + +// access functions void setTraceID(const uint8_t traceID); //!< Set the CoreSight trace ID. void setHWTraceFeat(const hw_event_feat_t hw_feat); //!< set usage of STM HW event trace.
- const uint8_t getTraceID() const; //!< Get the CoreSight trace ID. + virtual const uint8_t getTraceID() const; //!< Get the CoreSight trace ID. const uint8_t getMaxMasterIdx() const; //!< Get the maximum master index const uint16_t getMaxChannelIdx() const; //!< Get the maximum channel index. const uint16_t getHWTraceMasterIdx() const; //!< Get the master used for HW event trace. @@ -74,22 +84,29 @@ public:
private: bool m_bHWTraceEn; + ocsd_stm_cfg m_cfg; };
inline STMConfig::STMConfig() { - reg_tcsr = 0; - reg_devid = 0xFF; // default to 256 masters. - reg_feat3r = 0x10000; // default to 65536 channels. - reg_feat1r = 0x0; - reg_hwev_mast = 0; // default hwtrace master = 0; - hw_event = HwEvent_Unknown_Disabled; // default to not present / disabled. + m_cfg.reg_tcsr = 0; + m_cfg.reg_devid = 0xFF; // default to 256 masters. + m_cfg.reg_feat3r = 0x10000; // default to 65536 channels. + m_cfg.reg_feat1r = 0x0; + m_cfg.reg_hwev_mast = 0; // default hwtrace master = 0; + m_cfg.hw_event = HwEvent_Unknown_Disabled; // default to not present / disabled. m_bHWTraceEn = false; }
+inline STMConfig::STMConfig(const ocsd_stm_cfg *cfg_regs) +{ + m_cfg = *cfg_regs; + setHWTraceFeat(m_cfg.hw_event); +} + inline STMConfig & STMConfig::operator=(const ocsd_stm_cfg *p_cfg) { - *dynamic_cast<ocsd_stm_cfg *>(this) = *p_cfg; + m_cfg = *p_cfg; setHWTraceFeat(p_cfg->hw_event); return *this; } @@ -97,36 +114,36 @@ inline STMConfig & STMConfig::operator=(const ocsd_stm_cfg *p_cfg) inline void STMConfig::setTraceID(const uint8_t traceID) { uint32_t IDmask = 0x007F0000; - reg_tcsr &= ~IDmask; - reg_tcsr |= (((uint32_t)traceID) << 16) & IDmask; + m_cfg.reg_tcsr &= ~IDmask; + m_cfg.reg_tcsr |= (((uint32_t)traceID) << 16) & IDmask; }
inline void STMConfig::setHWTraceFeat(const hw_event_feat_t hw_feat) { - hw_event = hw_feat; - m_bHWTraceEn = (hw_event == HwEvent_Enabled); - if(hw_event == HwEvent_UseRegisters) - m_bHWTraceEn = (((reg_feat1r & 0xC0000) == 0x80000) && ((reg_tcsr & 0x8) == 0x8)); + m_cfg.hw_event = hw_feat; + m_bHWTraceEn = (m_cfg.hw_event == HwEvent_Enabled); + if(m_cfg.hw_event == HwEvent_UseRegisters) + m_bHWTraceEn = (((m_cfg.reg_feat1r & 0xC0000) == 0x80000) && ((m_cfg.reg_tcsr & 0x8) == 0x8)); }
inline const uint8_t STMConfig::getTraceID() const { - return (uint8_t)((reg_tcsr >> 16) & 0x7F); + return (uint8_t)((m_cfg.reg_tcsr >> 16) & 0x7F); }
inline const uint8_t STMConfig::getMaxMasterIdx() const { - return (uint8_t)(reg_devid & 0xFF); + return (uint8_t)(m_cfg.reg_devid & 0xFF); }
inline const uint16_t STMConfig::getMaxChannelIdx() const { - return (uint16_t)(reg_feat3r - 1); + return (uint16_t)(m_cfg.reg_feat3r - 1); }
inline const uint16_t STMConfig::getHWTraceMasterIdx() const { - return (uint16_t)(reg_hwev_mast & 0xFFFF); + return (uint16_t)(m_cfg.reg_hwev_mast & 0xFFFF); }
inline bool STMConfig::getHWTraceEn() const diff --git a/decoder/source/etmv4/trc_cmp_cfg_etmv4.cpp b/decoder/source/etmv4/trc_cmp_cfg_etmv4.cpp index 214d149..5703406 100644 --- a/decoder/source/etmv4/trc_cmp_cfg_etmv4.cpp +++ b/decoder/source/etmv4/trc_cmp_cfg_etmv4.cpp @@ -36,26 +36,26 @@
EtmV4Config::EtmV4Config() { - reg_idr0 = 0x28000EA1; - reg_idr1 = 0x4100F403; - reg_idr2 = 0x00000488; - reg_idr8 = 0; - reg_idr9 = 0; - reg_idr10 = 0; - reg_idr11 = 0; - reg_idr12 = 0; - reg_idr13 = 0; - reg_configr = 0xC1; - reg_traceidr = 0; - arch_ver = ARCH_V7; - core_prof = profile_CortexA; + m_cfg.reg_idr0 = 0x28000EA1; + m_cfg.reg_idr1 = 0x4100F403; + m_cfg.reg_idr2 = 0x00000488; + m_cfg.reg_idr8 = 0; + m_cfg.reg_idr9 = 0; + m_cfg.reg_idr10 = 0; + m_cfg.reg_idr11 = 0; + m_cfg.reg_idr12 = 0; + m_cfg.reg_idr13 = 0; + m_cfg.reg_configr = 0xC1; + m_cfg.reg_traceidr = 0; + m_cfg.arch_ver = ARCH_V7; + m_cfg.core_prof = profile_CortexA;
PrivateInit(); }
EtmV4Config & EtmV4Config::operator=(const ocsd_etmv4_cfg *p_cfg) { - *dynamic_cast<ocsd_etmv4_cfg *>(this) = *p_cfg; + m_cfg = *p_cfg; PrivateInit(); return *this; } @@ -79,15 +79,15 @@ void EtmV4Config::CalcQSupp() Q_NO_ICOUNT_ONLY, Q_FULL }; - uint8_t Qsupp = (reg_idr0 >> 15) & 0x3; + uint8_t Qsupp = (m_cfg.reg_idr0 >> 15) & 0x3; m_QSuppType = qtypes[Qsupp]; - m_QSuppFilter = (bool)((reg_idr0 & 0x4000) == 0x4000) && (m_QSuppType != Q_NONE); + m_QSuppFilter = (bool)((m_cfg.reg_idr0 & 0x4000) == 0x4000) && (m_QSuppType != Q_NONE); m_QSuppCalc = true; }
void EtmV4Config::CalcVMIDSize() { - uint32_t vmidszF = (reg_idr2 >> 10) & 0x1F; + uint32_t vmidszF = (m_cfg.reg_idr2 >> 10) & 0x1F; if(vmidszF == 1) m_VMIDSize = 8; else if(MinVersion() > 0) diff --git a/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp b/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp index 0bc2e59..8966504 100644 --- a/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp +++ b/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp @@ -515,7 +515,7 @@ void EtmV4IPktProcImpl::iPktException() uint16_t excep_type = (m_currPacketData[1] >> 1) & 0x1F; uint8_t addr_interp = (m_currPacketData[1] & 0x40) >> 5 | (m_currPacketData[1] & 0x1); uint8_t m_fault_pending = 0; - uint8_t m_type = (m_config.core_prof == profile_CortexM) ? 1 : 0; + uint8_t m_type = (m_config.coreProfile() == profile_CortexM) ? 1 : 0;
// extended exception packet (probably M class); if(m_currPacketData[1] & 0x80) diff --git a/decoder/source/ptm/trc_cmp_cfg_ptm.cpp b/decoder/source/ptm/trc_cmp_cfg_ptm.cpp index 8f51c2f..8028683 100644 --- a/decoder/source/ptm/trc_cmp_cfg_ptm.cpp +++ b/decoder/source/ptm/trc_cmp_cfg_ptm.cpp @@ -37,17 +37,22 @@ PtmConfig::PtmConfig() { // defaults set ETMv1.1, V7A - arch_ver = ARCH_V7; - core_prof = profile_CortexA; - reg_ccer = 0; - reg_idr = 0x4100F310; - reg_ctrl = 0; + m_cfg.arch_ver = ARCH_V7; + m_cfg.core_prof = profile_CortexA; + m_cfg.reg_ccer = 0; + m_cfg.reg_idr = 0x4100F310; + m_cfg.reg_ctrl = 0; +} + +PtmConfig::PtmConfig(const ocsd_ptm_cfg *cfg_regs) +{ + m_cfg = *cfg_regs; }
const int PtmConfig::CtxtIDBytes() const { int ctxtIdsizes[] = { 0, 1, 2, 4 }; - return ctxtIdsizes[(reg_ctrl >> 14) & 0x3]; + return ctxtIdsizes[(m_cfg.reg_ctrl >> 14) & 0x3]; }
diff --git a/decoder/source/ptm/trc_pkt_decode_ptm.cpp b/decoder/source/ptm/trc_pkt_decode_ptm.cpp index 9c5b16d..5381086 100644 --- a/decoder/source/ptm/trc_pkt_decode_ptm.cpp +++ b/decoder/source/ptm/trc_pkt_decode_ptm.cpp @@ -165,8 +165,8 @@ ocsd_err_t TrcPktDecodePtm::onProtocolConfig() m_CSID = m_config->getTraceID();
// config options affecting decode - m_instr_info.pe_type.profile = m_config->core_prof; - m_instr_info.pe_type.arch = m_config->arch_ver; + m_instr_info.pe_type.profile = m_config->coreProfile(); + m_instr_info.pe_type.arch = m_config->archVersion(); m_instr_info.dsb_dmb_waypoints = m_config->dmsbWayPt() ? 1 : 0; return err; } diff --git a/decoder/tests/snapshot_parser_lib/source/ss_to_dcdtree.cpp b/decoder/tests/snapshot_parser_lib/source/ss_to_dcdtree.cpp index 271b83b..0a31edd 100644 --- a/decoder/tests/snapshot_parser_lib/source/ss_to_dcdtree.cpp +++ b/decoder/tests/snapshot_parser_lib/source/ss_to_dcdtree.cpp @@ -243,7 +243,7 @@ bool CreateDcdTreeFromSnapShot::createETMv4Decoder(const std::string &coreName, bool configOK = true;
// generate the config data from the device data. - EtmV4Config config; + ocsd_etmv4_cfg config;
regs_to_access_t regs_to_access[] = { { ETMv4RegCfg, true, &config.reg_configr, 0 }, @@ -270,16 +270,18 @@ bool CreateDcdTreeFromSnapShot::createETMv4Decoder(const std::string &coreName, if(configOK) { ocsd_err_t err = OCSD_OK; + EtmV4Config configObj(&config); + if(m_bPacketProcOnly) { if(bDataChannel) - err = m_pDecodeTree->createETMv4DPktProcessor(&config); + err = m_pDecodeTree->createETMv4DPktProcessor(&configObj); else - err = m_pDecodeTree->createETMv4IPktProcessor(&config); + err = m_pDecodeTree->createETMv4IPktProcessor(&configObj); } else { - err = m_pDecodeTree->createETMv4Decoder(&config,bDataChannel); + err = m_pDecodeTree->createETMv4Decoder(&configObj,bDataChannel); } if(err == OCSD_OK) createdDecoder = true; @@ -337,7 +339,8 @@ bool CreateDcdTreeFromSnapShot::createPTMDecoder(const std::string &coreName, Pa bool configOK = true;
// generate the config data from the device data. - PtmConfig config; + + ocsd_ptm_cfg config;
regs_to_access_t regs_to_access[] = { { ETMv3PTMRegIDR, true, &config.reg_idr, 0 }, @@ -356,11 +359,12 @@ bool CreateDcdTreeFromSnapShot::createPTMDecoder(const std::string &coreName, Pa // good config - generate the decoder on the tree. if(configOK) { + PtmConfig configObj(&config); ocsd_err_t err = OCSD_OK; if(m_bPacketProcOnly) - err = m_pDecodeTree->createPTMPktProcessor(&config); + err = m_pDecodeTree->createPTMPktProcessor(&configObj); else - err = m_pDecodeTree->createPTMDecoder(&config); + err = m_pDecodeTree->createPTMDecoder(&configObj);
if(err == OCSD_OK) createdDecoder = true; @@ -395,7 +399,8 @@ bool CreateDcdTreeFromSnapShot::createSTMDecoder(Parser::Parsed *devSrc) bool configOK = true;
// generate the config data from the device data. - STMConfig config; + + ocsd_stm_cfg config;
regs_to_access_t regs_to_access[] = { { STMRegTCSR, true, &config.reg_tcsr, 0 } @@ -405,8 +410,9 @@ bool CreateDcdTreeFromSnapShot::createSTMDecoder(Parser::Parsed *devSrc) if(configOK) { ocsd_err_t err = OCSD_OK; + STMConfig configObj(&config); if(m_bPacketProcOnly) - err = m_pDecodeTree->createSTMPktProcessor(&config); + err = m_pDecodeTree->createSTMPktProcessor(&configObj); else err = OCSD_ERR_TEST_SS_TO_DECODER;