Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) for TPDM. It specifies the number of CMB MSR registers supported by the TDPM.
Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com --- .../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 691c7ba365aa..283dfb39d46f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -62,6 +62,15 @@ properties: minimum: 0 maximum: 32
+ qcom,cmb-msr-num: + description: + Specifies the number of CMB MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 128 + clocks: maxItems: 1
@@ -97,6 +106,7 @@ examples:
qcom,dsb-element-size = <32>; qcom,dsb_msr_num = <16>; + qcom,cmb-msr-num = <6>;
clocks = <&aoss_qmp>; clock-names = "apb_pclk";