On 25/07/2023 08:15, Tao Zhang wrote:
Add nodes to configure trigger pattern and trigger pattern mask. Each DSB subunit TPDM has maximum of n(n<7) XPR registers to configure trigger pattern match output. Eight 32 bit registers providing DSB interface trigger output pattern match comparison. And each DSB subunit TPDM has maximum of m(m<7) XPMR registers to configure trigger pattern mask match output. Eight 32 bit registers providing DSB interface trigger output pattern match mask.
Signed-off-by: Tao Zhang quic_taozha@quicinc.com
.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 34 +++++- drivers/hwtracing/coresight/coresight-tpdm.c | 118 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 10 ++ 3 files changed, 161 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index a4550c5..66f9582 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -98,4 +98,36 @@ Description: should be written first to configure the index number of the edge detection which needs to be masked.
Accepts only one of the 2 values - 0 or 1.\ No newline at end of file
Accepts only one of the 2 values - 0 or 1.+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt_idx +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:
Read/Write the index number of the trigger pattern value of DSBtpdm. Since there are at most 8 XPR and XPMR registers for thetrigger parttern, this value ranges from 0 to 7.+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:
Read a set of the trigger pattern values of the DSB TPDM.Write a data to configure the trigger pattern corresponding tothe index number. Before writing data to this sysfs file,"dsb_trig_patt_idx" should be written first to configure theindex number of the trigger pattern which needs to be configured.+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:
Read a set of the trigger pattern mask of the DSB TPDM.Write a data to configure the trigger pattern mask correspondingto the index number. Before writing data to this sysfs file,"dsb_trig_patt_idx" should be written first to configure theindex number of the trigger pattern mask which needs to beconfigured.\ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 98fd6ab..1c32d27 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -80,6 +80,13 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], drvdata->base + TPDM_DSB_EDCMR(i));
- for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
writel_relaxed(drvdata->dsb->trig_patt[i],drvdata->base + TPDM_DSB_XPR(i));writel_relaxed(drvdata->dsb->trig_patt_mask[i],drvdata->base + TPDM_DSB_XPMR(i));- }
- val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ if (drvdata->dsb->trig_ts)
@@ -455,6 +462,114 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_edge_ctrl_mask); +static ssize_t dsb_trig_patt_idx_show(struct device *dev,
struct device_attribute *attr,char *buf)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- return sysfs_emit(buf, "%u\n",
(unsigned int)drvdata->dsb->trig_patt_idx);+}
+static ssize_t dsb_trig_patt_idx_store(struct device *dev,
struct device_attribute *attr,const char *buf,size_t size)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- unsigned long index;
- if (kstrtoul(buf, 0, &index))
return -EINVAL;- if (index >= TPDM_DSB_MAX_PATT)
return -EPERM;- spin_lock(&drvdata->spinlock);
- drvdata->dsb->trig_patt_idx = index;
- spin_unlock(&drvdata->spinlock);
- return size;
+} +static DEVICE_ATTR_RW(dsb_trig_patt_idx);
+static ssize_t dsb_trig_patt_val_show(struct device *dev,
struct device_attribute *attr,char *buf)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- ssize_t size = 0;
- unsigned long bytes;
- int i = 0;
- spin_lock(&drvdata->spinlock);
- for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
bytes = sysfs_emit_at(buf, size,"Value: 0x%x\n", drvdata->dsb->trig_patt[i]);if (bytes <= 0)break;size += bytes;- }
- spin_unlock(&drvdata->spinlock);
- return size;
+}
+static ssize_t dsb_trig_patt_val_store(struct device *dev,
struct device_attribute *attr,const char *buf,size_t size)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- unsigned long val;
- if (kstrtoul(buf, 0, &val))
return -EINVAL;- spin_lock(&drvdata->spinlock);
- drvdata->dsb->trig_patt[drvdata->dsb->trig_patt_idx] = val;
- spin_unlock(&drvdata->spinlock);
- return size;
+} +static DEVICE_ATTR_RW(dsb_trig_patt_val);
+static ssize_t dsb_trig_patt_mask_show(struct device *dev,
struct device_attribute *attr,char *buf)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- ssize_t size = 0;
- unsigned long bytes;
- int i = 0;
- spin_lock(&drvdata->spinlock);
- for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
bytes = sysfs_emit_at(buf, size,"Value: 0x%x\n", drvdata->dsb->trig_patt_mask[i]);
As mentioned above, please stick to single value. In this case, we could simply expose :
dsb_trig_patt_mask0..7 as RW and directly let the user set/get the values and get rid of the idx.
You may be able to use an device_ext_attribute to store the index and use a single function to support all registers.
Suzuki