On Thu, 5 Sep 2019 at 11:22, Linu Cherian lcherian@marvell.com wrote:
Hi,
-----Original Message----- From: Mathieu Poirier mathieu.poirier@linaro.org Sent: Wednesday, September 4, 2019 8:39 PM To: Linu Cherian lcherian@marvell.com Cc: Al Grant Al.Grant@arm.com; coresight@lists.linaro.org; Sunil Kovvuri Goutham sgoutham@marvell.com Subject: [EXT] Re: Tracing and decoding support for trace hardware without trace formatter
[...]
But in general, any ETR that can deal with multiple trace sources should support formatting, otherwise the trace will be corrupt if more than one trace source is enabled. Practically the only reason ever to have an ETR that doesn't support formatting is if the ETR is specific to a single trace source (e.g. one ETR
per
CPU).
Yes. We have one ETR per CPU.
I am very surprised (and thrilled) to see such topology emerging. Unfortunately it also means you will not be able to use the current coresight infrastructure (kernel and user space) without _serious_ refactoring. Your platform wouldn't happen to be in the public domain by any chance? Or perhaps Marvell would be interested in shipping a board to a selected group of people? That would help with both development and testing.
Thanks for the help Mathieu. At this point of time, due to some internal reasons we may not be able to ship the board or provide access to them. But we would be happy to test any patches if any.
The problem here is that refactoring is so extensive that it would be impossible for me to send you patches. To be efficient I would need a board to work with. Please let me know if and when the boards become available. Note that it would also be possible to sign an exclusive NDA with Marvell if need be.
Thanks, Mathieu