compute_trbe_buffer_limit() only returned the next TRBE limit pointer, leaving __arm_trbe_enable() to derive the remaining buffer state and detect the -ENOSPC case.
Replace it with trbe_compute_next(), which computes the next TRBE buffer state as one operation. Let the snapshot and normal paths set buf->trbe_limit directly and return 0 or an errno, then update trbe_write and trbe_hw_base after a successful limit calculation. The normal path now reports -ENOSPC directly when no writable area is available.
This refactoring is for future extensions, such as calculating additional values (e.g., the trigger count). No functional changes are intended.
Signed-off-by: Leo Yan leo.yan@arm.com --- drivers/hwtracing/coresight/coresight-trbe.c | 44 +++++++++++++++++----------- 1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index ada4794c51f3eb9142cd62f4209affe308142d1b..09ed9bcf4a70479169094697dcc3d445629cfaae 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -349,7 +349,7 @@ static void trbe_pad_buf(struct perf_output_handle *handle, int len) perf_aux_output_skip(handle, len); }
-static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle) +static int trbe_snapshot_offset(struct perf_output_handle *handle) { struct trbe_buf *buf = etm_perf_sink_config(handle);
@@ -358,7 +358,8 @@ static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle) * the decoder to reset in case of an overflow or corruption. * So we can use the entire buffer for the snapshot mode. */ - return buf->nr_pages * PAGE_SIZE; + buf->trbe_limit = buf->trbe_base + buf->nr_pages * PAGE_SIZE; + return 0; }
static u64 trbe_min_trace_buf_size(struct perf_output_handle *handle) @@ -527,7 +528,7 @@ static unsigned long __trbe_normal_offset(struct perf_output_handle *handle) return 0; }
-static unsigned long trbe_normal_offset(struct perf_output_handle *handle) +static int trbe_normal_offset(struct perf_output_handle *handle) { struct trbe_buf *buf = etm_perf_sink_config(handle); u64 limit = __trbe_normal_offset(handle); @@ -546,19 +547,34 @@ static unsigned long trbe_normal_offset(struct perf_output_handle *handle) limit = __trbe_normal_offset(handle); head = PERF_IDX2OFF(handle->head, buf); } - return limit; + + if (!limit) + return -ENOSPC; + + buf->trbe_limit = buf->trbe_base + limit; + return 0; }
-static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle) +static int trbe_compute_next(struct perf_output_handle *handle) { struct trbe_buf *buf = etm_perf_sink_config(handle); - unsigned long offset; + int ret; + + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
if (buf->snapshot) - offset = trbe_snapshot_offset(handle); + ret = trbe_snapshot_offset(handle); else - offset = trbe_normal_offset(handle); - return buf->trbe_base + offset; + ret = trbe_normal_offset(handle); + + if (ret) + return ret; + + buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf); + + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; + return 0; }
static void clr_trbe_status(void) @@ -1022,15 +1038,9 @@ static int __arm_trbe_enable(struct trbe_buf *buf, { int ret = 0;
- perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); - buf->trbe_limit = compute_trbe_buffer_limit(handle); - buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf); - if (buf->trbe_limit == buf->trbe_base) { - ret = -ENOSPC; + ret = trbe_compute_next(handle); + if (ret) goto err; - } - /* Set the base of the TRBE to the buffer base */ - buf->trbe_hw_base = buf->trbe_base;
ret = trbe_apply_work_around_before_enable(buf); if (ret)