Expose the TRCDEVARCH register via the sysfs for component detection. Given that the TRCIDR1 may not completely identify the ETM component and instead need to use TRCDEVARCH, expose this via sysfs for tools to use it for identification.
Cc: Mike Leach mike.leach@linaro.org Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com --- Changes since v5: - Move the trcdevarch to mgmt/ instead of the trcidr (Mike L) - Add sysfs documentation for the new register (Mike L) --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 8 ++++++++ drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 ++ 2 files changed, 10 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 881f0cd99ce4..8e53a32f8150 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -371,6 +371,14 @@ Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (Read) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW.
+What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch +Date: January 2021 +KernelVersion: 5.12 +Contact: Mathieu Poirier mathieu.poirier@linaro.org +Description: (Read) Print the content of the Device Architecture Register + (offset 0xFBC). The value is taken directly read + from the HW. + What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 009818675928..b590b042dca3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2357,6 +2357,7 @@ coresight_etm4x_cross_read(trclsr, TRCLSR); coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS); coresight_etm4x_cross_read(trcdevid, TRCDEVID); coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE); +coresight_etm4x_cross_read(trcdevarch, TRCDEVARCH); coresight_etm4x_cross_read(trcpidr0, TRCPIDR0); coresight_etm4x_cross_read(trcpidr1, TRCPIDR1); coresight_etm4x_cross_read(trcpidr2, TRCPIDR2); @@ -2375,6 +2376,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { &dev_attr_trcauthstatus.attr, &dev_attr_trcdevid.attr, &dev_attr_trcdevtype.attr, + &dev_attr_trcdevarch.attr, &dev_attr_trcpidr0.attr, &dev_attr_trcpidr1.attr, &dev_attr_trcpidr2.attr,