Hi,
I'm trying to run Coresight on XIlinx Zynq Ultrascale+ with ZCU104 board. I have already made some progress, however I'm stuck on getting valid timestamp packets in the decoded trace.
I'm using mainline Linux forked at v5.0-rc4. So far, I manually added Coresight nodes to DTS basing on the Ultrascale+ datasheet, since neither mainline Linux nor the Xilinx fork seem to have it. Looks like this step went fine, since I can see drivers reporting in dmesg and related sysfs nodes being registered:
root@zynq:~# dmesg | grep -i coresight [ 3.745681] coresight-etm4x fec40000.etm0: CPU0: ETM v4.0 initialized [ 3.752318] coresight-etm4x fed40000.etm1: CPU1: ETM v4.0 initialized [ 3.758952] coresight-etm4x fee40000.etm2: CPU2: ETM v4.0 initialized [ 3.765587] coresight-etm4x fef40000.etm3: CPU3: ETM v4.0 initialized [ 3.772190] coresight-stm fe9c0000.stm: stm_register_device failed, probing deferred [ 3.780004] coresight-cpu-debug fec10000.debug0: Coresight debug-CPU0 initialized [ 3.787531] coresight-cpu-debug fed10000.debug1: Coresight debug-CPU1 initialized [ 3.795058] coresight-cpu-debug fee10000.debug2: Coresight debug-CPU2 initialized [ 3.802587] coresight-cpu-debug fef10000.debug3: Coresight debug-CPU3 initialized [ 3.917423] coresight-stm fe9c0000.stm: STM500 initialized
root@zynq:~# ls /sys/bus/coresight/devices/ fe920000.funnel1 fe940000.etf1 fe970000.etr fe9c0000.stm fed40000.etm1 fef40000.etm3 fe930000.funnel2 fe950000.etf2 fe980000.tpiu fec40000.etm0 fee40000.etm2 replicator
Overall trace acquisition and decoding with perf+OpenCSD also looks good, apart from timestamp packets. When I request timestamping, the value is constant 0x0:
root@zynq:~/cs_test# perf record -e cs_etm/timestamp,@fe940000.etf1/u --filter 'filter 0x764/0x2c@./sum' --per-thread ./sum Val: 20 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.002 MB perf.data ] root@zynq:~/cs_test# perf report --dump | grep TIMESTAMP Idx:231; ID:12; I_TIMESTAMP : Timestamp.; Updated val = 0x0 Idx:254; ID:12; I_TIMESTAMP : Timestamp.; Updated val = 0x0 Idx:279; ID:12; I_TIMESTAMP : Timestamp.; Updated val = 0x0
According to the datasheet, Ultrascale+ has a timestamp generator. Perf confirms it in the registers values dump:
root@zynq:~/cs_test# perf report --dump | grep 'TRCCONFIGR|TRCIDR0' TRCCONFIGR 800 TRCIDR0 28000ea1 TRCCONFIGR 800 TRCIDR0 28000ea1 TRCCONFIGR 800 TRCIDR0 28000ea1 TRCCONFIGR 800 TRCIDR0 28000ea1
These value match what ETMv4 architecture specs says: - bit 11 (TS) of TRCCONFIGR is 1, what indicates global timestamping is enabled - bits 24:28 (TSSIZE) of TRCIDR0 are 0b1000, what indicates support for 64-bit-long timestamps
In the kernel source code I can see that the ETMv4 driver writes the EVENT bits (0:7) of the TRCTSCTLR register. I didn't thoroughly analyze this code, but I take it as another hint that timestamping is actually supported.
At this point I wonder if anybody has witnessed timestamps working on this platform, whether under Linux or baremetal. I would appreciate even the tiniest suggestions where should I look next to get them working.
Thanks and best regards, Wojciech