On 11/04/2024 23:30, Yabin Cui wrote:
On Thu, Apr 11, 2024 at 4:31 AM Suzuki K Poulose suzuki.poulose@arm.com wrote:
When we restore the register state for ETM4x, while coming back from CPU idle, we hardcode IOMEM access. This is wrong and could blow up for an ETM with system instructions access (and for ETE).
Fixes: f5bd523690d2f ("coresight: etm4x: Convert all register accesses") Reported-by: Yabin Cui yabinc@google.com Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com
drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c2ca4a02dfce..fae96151cdaf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1843,8 +1843,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) { int i; struct etmv4_save_state *state = drvdata->save_state;
struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);struct csdev_access *csa = &tmp_csa;
struct csdev_access *csa = &drvdata->csdev->access;if (!WARN_ON(!drvdata->csdev))COMMENT: Remove ! before WARN_ON? WARN_ON returns 1 when the warning happens.
Yikes! Well spotted, I will fix this.
Suzuki
return; etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);-- 2.34.1