Configure ETM to generate a trigger on Ext out [0] on panic. This is achieved by configuring a single address comparator with the address of "panic" and by configuring Ext out [0] to trigger on the comparator event.
This trigger can be used by the sinks to stop capture on panic.
Signed-off-by: Linu Cherian lcherian@marvell.com --- .../coresight/coresight-etm4x-core.c | 17 +++++++++--- drivers/hwtracing/coresight/coresight-etm4x.h | 26 +++++++++++++++++++ 2 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4c15fae534f3..7047a384d91f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -62,6 +62,7 @@ static void etm4_set_default_config(struct etmv4_config *config); static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, struct perf_event *event); static u64 etm4_get_access_type(struct etmv4_config *config); +static u64 etm4_get_comparator_access_type(struct etmv4_config *config);
static enum cpuhp_state hp_online;
@@ -1290,9 +1291,8 @@ static void etm4_set_victlr_access(struct etmv4_config *config)
static void etm4_set_default_config(struct etmv4_config *config) { - /* disable all events tracing */ - config->eventctrl0 = 0x0; - config->eventctrl1 = 0x0; + int rselector = 2; /* 0 and 1 are reserved */ + int comp_idx = 0;
/* disable stalling */ config->stall_ctrl = 0x0; @@ -1308,6 +1308,17 @@ static void etm4_set_default_config(struct etmv4_config *config)
/* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ etm4_set_victlr_access(config); + + /* Configure the comparator with kernel panic address */ + config->addr_val[comp_idx] = (u64)panic; + config->addr_acc[comp_idx] = etm4_get_comparator_access_type(config); + config->addr_type[comp_idx] = ETM_ADDR_TYPE_STOP; + config->res_ctrl[rselector] = ETM_RESGRP_SADDRCMP << 16 | BIT(comp_idx); + + /* Connect external output [0] with comparator out */ + config->eventctrl0 = 0x0 << 7 | rselector; + + config->eventctrl1 = 0x0; }
static u64 etm4_get_ns_access_type(struct etmv4_config *config) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 27c8a9901868..6ac5d5ee1877 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -612,6 +612,32 @@ #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f
+/* ETM resource group encoding */ +#define ETM_RESGRP_EXTIN 0x0 +#define ETM_RESGRP_PECMP 0x1 +#define ETM_RESGRP_CNTRSEQ 0x2 +#define ETM_RESGRP_SSCMP 0x3 +#define ETM_RESGRP_SADDRCMP 0x4 +#define ETM_RESGRP_ADDRRANGECMP 0x5 +#define ETM_RESGRP_CIDCMP 0x6 +#define ETM_RESGRP_VCIDCMP 0x7 + +#define ETM_EXTIN_0 0x0 + + +/* ETM resource group encoding */ +#define ETM_RESGRP_EXTIN 0x0 +#define ETM_RESGRP_PECMP 0x1 +#define ETM_RESGRP_CNTRSEQ 0x2 +#define ETM_RESGRP_SSCMP 0x3 +#define ETM_RESGRP_SADDRCMP 0x4 +#define ETM_RESGRP_ADDRRANGECMP 0x5 +#define ETM_RESGRP_CIDCMP 0x6 +#define ETM_RESGRP_VCIDCMP 0x7 + +#define ETM_EXTIN_0 0x0 + + /* ETMv4 programming modes */ #define ETM_MODE_EXCLUDE BIT(0) #define ETM_MODE_LOAD BIT(1)