This series converts TRBE registers to automatic generation, after renaming their fields as per the auto-gen tools format. Although the following field still renames in arch/arm64/include/asm/sysreg.h, as it cannot be converted (shares bits with other fields) in the tools format.
#define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0
This series applies on v6.4-rc4.
Changes in V2:
- Renamed each individual TRBE register fields as per auto-gen tools - Converted each individual TRBE registers as per auto-gen tools - Added new register fields as per DDI0601 2023-03
Changes in V1:
https://lore.kernel.org/all/20230531055524.16562-1-anshuman.khandual@arm.com...
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org
Anshuman Khandual (14): arm64/sysreg: Rename TRBLIMITR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBBASER_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBSR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBTRG_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBIDR_EL1 fields per auto-gen tools format arm64/sysreg: Convert TRBLIMITR_EL1 register to automatic generation arm64/sysreg: Convert TRBPTR_EL1 register to automatic generation arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation arm64/sysreg: Convert TRBSR_EL1 register to automatic generation arm64/sysreg: Convert TRBMAR_EL1 register to automatic generation arm64/sysreg: Convert TRBTRG_EL1 register to automatic generation arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation
arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 50 +-------------- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- arch/arm64/tools/sysreg | 64 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.c | 33 +++++----- drivers/hwtracing/coresight/coresight-trbe.h | 38 +++++------- 7 files changed, 101 insertions(+), 90 deletions(-)
This renames TRBLIMITR_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 16 +++++++-------- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 21 ++++++++++---------- drivers/hwtracing/coresight/coresight-trbe.h | 7 ++++--- 4 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e72d9aaab6b1..b2b67ae7525b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -246,14 +246,14 @@ #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
-#define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0) -#define TRBLIMITR_LIMIT_SHIFT 12 -#define TRBLIMITR_NVM BIT(5) -#define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0) -#define TRBLIMITR_TRIG_MODE_SHIFT 3 -#define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0) -#define TRBLIMITR_FILL_MODE_SHIFT 1 -#define TRBLIMITR_ENABLE BIT(0) +#define TRBLIMITR_EL1_LIMIT_MASK GENMASK_ULL(63, 12) +#define TRBLIMITR_EL1_LIMIT_SHIFT 12 +#define TRBLIMITR_EL1_nVM BIT(5) +#define TRBLIMITR_EL1_TM_MASK GENMASK(4, 3) +#define TRBLIMITR_EL1_TM_SHIFT 3 +#define TRBLIMITR_EL1_FM_MASK GENMASK(2, 1) +#define TRBLIMITR_EL1_FM_SHIFT 1 +#define TRBLIMITR_EL1_E BIT(0) #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) #define TRBPTR_PTR_SHIFT 0 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c index d756b939f296..4558c02eb352 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -56,7 +56,7 @@ static void __debug_save_trace(u64 *trfcr_el1) *trfcr_el1 = 0;
/* Check if the TRBE is enabled */ - if (!(read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_ENABLE)) + if (!(read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_EL1_E)) return; /* * Prohibit trace generation while we are in guest. diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 1fc4fd79a1c6..1d9d141c62e9 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -218,7 +218,7 @@ static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) * Enable the TRBE without clearing LIMITPTR which * might be required for fetching the buffer limits. */ - trblimitr |= TRBLIMITR_ENABLE; + trblimitr |= TRBLIMITR_EL1_E; write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
/* Synchronize the TRBE enable event */ @@ -236,7 +236,7 @@ static inline void set_trbe_disabled(struct trbe_cpudata *cpudata) * Disable the TRBE without clearing LIMITPTR which * might be required for fetching the buffer limits. */ - trblimitr &= ~TRBLIMITR_ENABLE; + trblimitr &= ~TRBLIMITR_EL1_E; write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
if (trbe_needs_drain_after_disable(cpudata)) @@ -596,13 +596,13 @@ static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); unsigned long addr = buf->trbe_limit;
- WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT))); + WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_EL1_LIMIT_SHIFT))); WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
- trblimitr &= ~TRBLIMITR_NVM; - trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT); - trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT); - trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT); + trblimitr &= ~TRBLIMITR_EL1_nVM; + trblimitr &= ~TRBLIMITR_EL1_FM_MASK; + trblimitr &= ~TRBLIMITR_EL1_TM_MASK; + trblimitr &= ~TRBLIMITR_EL1_LIMIT_MASK;
/* * Fill trace buffer mode is used here while configuring the @@ -613,14 +613,15 @@ static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) * trace data in the interrupt handler, before reconfiguring * the TRBE. */ - trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT; + trblimitr |= (TRBLIMITR_EL1_FM_FILL << TRBLIMITR_EL1_FM_SHIFT) & + TRBLIMITR_EL1_FM_MASK;
/* * Trigger mode is not used here while configuring the TRBE for * the trace capture. Hence just keep this in the ignore mode. */ - trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << - TRBLIMITR_TRIG_MODE_SHIFT; + trblimitr |= (TRBLIMITR_EL1_TM_IGNR << TRBLIMITR_EL1_TM_SHIFT) & + TRBLIMITR_EL1_TM_MASK; trblimitr |= (addr & PAGE_MASK); set_trbe_enabled(buf->cpudata, trblimitr); } diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 98ff1b17ad07..8ea7079d60bb 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -30,7 +30,7 @@ static inline bool is_trbe_enabled(void) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
- return trblimitr & TRBLIMITR_ENABLE; + return trblimitr & TRBLIMITR_EL1_E; }
#define TRBE_EC_OTHERS 0 @@ -86,8 +86,9 @@ static inline bool is_trbe_running(u64 trbsr)
#define TRBE_TRIG_MODE_STOP 0 #define TRBE_TRIG_MODE_IRQ 1 -#define TRBE_TRIG_MODE_IGNORE 3 +#define TRBLIMITR_EL1_TM_IGNR 3
+#define TRBLIMITR_EL1_FM_FILL 0 #define TRBE_FILL_MODE_FILL 0 #define TRBE_FILL_MODE_WRAP 1 #define TRBE_FILL_MODE_CIRCULAR_BUFFER 3 @@ -121,7 +122,7 @@ static inline void set_trbe_write_pointer(unsigned long addr) static inline unsigned long get_trbe_limit_pointer(void) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); - unsigned long addr = trblimitr & (TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT); + unsigned long addr = trblimitr & TRBLIMITR_EL1_LIMIT_MASK;
WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); return addr;
This renames TRBPTR_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b2b67ae7525b..2cb1078bc67f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -254,8 +254,8 @@ #define TRBLIMITR_EL1_FM_MASK GENMASK(2, 1) #define TRBLIMITR_EL1_FM_SHIFT 1 #define TRBLIMITR_EL1_E BIT(0) -#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) -#define TRBPTR_PTR_SHIFT 0 +#define TRBPTR_EL1_PTR_MASK GENMASK_ULL(63, 0) +#define TRBPTR_EL1_PTR_SHIFT 0 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) #define TRBBASER_BASE_SHIFT 12 #define TRBSR_EC_MASK GENMASK(5, 0)
This renames TRBBASER_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 4 ++-- drivers/hwtracing/coresight/coresight-trbe.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2cb1078bc67f..9b2d1c6faf13 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -256,8 +256,8 @@ #define TRBLIMITR_EL1_E BIT(0) #define TRBPTR_EL1_PTR_MASK GENMASK_ULL(63, 0) #define TRBPTR_EL1_PTR_SHIFT 0 -#define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) -#define TRBBASER_BASE_SHIFT 12 +#define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12) +#define TRBBASER_EL1_BASE_SHIFT 12 #define TRBSR_EC_MASK GENMASK(5, 0) #define TRBSR_EC_SHIFT 26 #define TRBSR_IRQ BIT(22) diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 8ea7079d60bb..0b73d9d10aa8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -131,7 +131,7 @@ static inline unsigned long get_trbe_limit_pointer(void) static inline unsigned long get_trbe_base_pointer(void) { u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1); - unsigned long addr = trbbaser & (TRBBASER_BASE_MASK << TRBBASER_BASE_SHIFT); + unsigned long addr = trbbaser & TRBBASER_EL1_BASE_MASK;
WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); return addr; @@ -140,7 +140,7 @@ static inline unsigned long get_trbe_base_pointer(void) static inline void set_trbe_base_pointer(unsigned long addr) { WARN_ON(is_trbe_enabled()); - WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_BASE_SHIFT))); + WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_EL1_BASE_SHIFT))); WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); write_sysreg_s(addr, SYS_TRBBASER_EL1); }
This renames TRBSR_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 26 ++++++++++---------- drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++----- drivers/hwtracing/coresight/coresight-trbe.h | 16 ++++++------ 3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9b2d1c6faf13..af9e93ca1905 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -258,19 +258,19 @@ #define TRBPTR_EL1_PTR_SHIFT 0 #define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12) #define TRBBASER_EL1_BASE_SHIFT 12 -#define TRBSR_EC_MASK GENMASK(5, 0) -#define TRBSR_EC_SHIFT 26 -#define TRBSR_IRQ BIT(22) -#define TRBSR_TRG BIT(21) -#define TRBSR_WRAP BIT(20) -#define TRBSR_ABORT BIT(18) -#define TRBSR_STOP BIT(17) -#define TRBSR_MSS_MASK GENMASK(15, 0) -#define TRBSR_MSS_SHIFT 0 -#define TRBSR_BSC_MASK GENMASK(5, 0) -#define TRBSR_BSC_SHIFT 0 -#define TRBSR_FSC_MASK GENMASK(5, 0) -#define TRBSR_FSC_SHIFT 0 +#define TRBSR_EL1_EC_MASK GENMASK(31, 26) +#define TRBSR_EL1_EC_SHIFT 26 +#define TRBSR_EL1_IRQ BIT(22) +#define TRBSR_EL1_TRG BIT(21) +#define TRBSR_EL1_WRAP BIT(20) +#define TRBSR_EL1_EA BIT(18) +#define TRBSR_EL1_S BIT(17) +#define TRBSR_EL1_MSS_MASK GENMASK(15, 0) +#define TRBSR_EL1_MSS_SHIFT 0 +#define TRBSR_EL1_BSC_MASK GENMASK(5, 0) +#define TRBSR_EL1_BSC_SHIFT 0 +#define TRBSR_EL1_FSC_MASK GENMASK(5, 0) +#define TRBSR_EL1_FSC_SHIFT 0 #define TRBMAR_SHARE_MASK GENMASK(1, 0) #define TRBMAR_SHARE_SHIFT 8 #define TRBMAR_OUTER_MASK GENMASK(3, 0) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 1d9d141c62e9..1bab91ce8e95 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -582,12 +582,12 @@ static void clr_trbe_status(void) u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
WARN_ON(is_trbe_enabled()); - trbsr &= ~TRBSR_IRQ; - trbsr &= ~TRBSR_TRG; - trbsr &= ~TRBSR_WRAP; - trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT); - trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT); - trbsr &= ~TRBSR_STOP; + trbsr &= ~TRBSR_EL1_IRQ; + trbsr &= ~TRBSR_EL1_TRG; + trbsr &= ~TRBSR_EL1_WRAP; + trbsr &= ~TRBSR_EL1_EC_MASK; + trbsr &= ~TRBSR_EL1_BSC_MASK; + trbsr &= ~TRBSR_EL1_S; write_sysreg_s(trbsr, SYS_TRBSR_EL1); }
diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 0b73d9d10aa8..3743d9085355 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -39,7 +39,7 @@ static inline bool is_trbe_enabled(void)
static inline int get_trbe_ec(u64 trbsr) { - return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK; + return (trbsr & TRBSR_EL1_EC_MASK) >> TRBSR_EL1_EC_SHIFT; }
#define TRBE_BSC_NOT_STOPPED 0 @@ -48,40 +48,40 @@ static inline int get_trbe_ec(u64 trbsr)
static inline int get_trbe_bsc(u64 trbsr) { - return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK; + return (trbsr & TRBSR_EL1_BSC_MASK) >> TRBSR_EL1_BSC_SHIFT; }
static inline void clr_trbe_irq(void) { u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
- trbsr &= ~TRBSR_IRQ; + trbsr &= ~TRBSR_EL1_IRQ; write_sysreg_s(trbsr, SYS_TRBSR_EL1); }
static inline bool is_trbe_irq(u64 trbsr) { - return trbsr & TRBSR_IRQ; + return trbsr & TRBSR_EL1_IRQ; }
static inline bool is_trbe_trg(u64 trbsr) { - return trbsr & TRBSR_TRG; + return trbsr & TRBSR_EL1_TRG; }
static inline bool is_trbe_wrap(u64 trbsr) { - return trbsr & TRBSR_WRAP; + return trbsr & TRBSR_EL1_WRAP; }
static inline bool is_trbe_abort(u64 trbsr) { - return trbsr & TRBSR_ABORT; + return trbsr & TRBSR_EL1_EA; }
static inline bool is_trbe_running(u64 trbsr) { - return !(trbsr & TRBSR_STOP); + return !(trbsr & TRBSR_EL1_S); }
#define TRBE_TRIG_MODE_STOP 0
This renames TRBMAR_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index af9e93ca1905..58cc9fd1935e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -271,12 +271,10 @@ #define TRBSR_EL1_BSC_SHIFT 0 #define TRBSR_EL1_FSC_MASK GENMASK(5, 0) #define TRBSR_EL1_FSC_SHIFT 0 -#define TRBMAR_SHARE_MASK GENMASK(1, 0) -#define TRBMAR_SHARE_SHIFT 8 -#define TRBMAR_OUTER_MASK GENMASK(3, 0) -#define TRBMAR_OUTER_SHIFT 4 -#define TRBMAR_INNER_MASK GENMASK(3, 0) -#define TRBMAR_INNER_SHIFT 0 +#define TRBMAR_EL1_SH_MASK GENMASK(9, 8) +#define TRBMAR_EL1_SH_SHIFT 8 +#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) +#define TRBMAR_EL1_Attr_SHIFT 0 #define TRBTRG_TRG_MASK GENMASK(31, 0) #define TRBTRG_TRG_SHIFT 0 #define TRBIDR_FLAG BIT(5)
This renames TRBTRG_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 58cc9fd1935e..f1de473ff027 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -275,8 +275,8 @@ #define TRBMAR_EL1_SH_SHIFT 8 #define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) #define TRBMAR_EL1_Attr_SHIFT 0 -#define TRBTRG_TRG_MASK GENMASK(31, 0) -#define TRBTRG_TRG_SHIFT 0 +#define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) +#define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_FLAG BIT(5) #define TRBIDR_PROG BIT(4) #define TRBIDR_ALIGN_MASK GENMASK(3, 0)
This renames TRBIDR_EL1 register fields per auto-gen tools format without causing any functional change in the TRBE driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: kvmarm@lists.linux.dev Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 8 ++++---- arch/arm64/kvm/debug.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.h | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 037724b19c5c..63ea1ef6c99e 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -69,7 +69,7 @@ cbz x0, .Lskip_trace_@ // Skip if TraceBuffer is not present
mrs_s x0, SYS_TRBIDR_EL1 - and x0, x0, TRBIDR_PROG + and x0, x0, TRBIDR_EL1_P cbnz x0, .Lskip_trace_@ // If TRBE is available at EL2
mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index f1de473ff027..114d38acdca5 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -277,10 +277,10 @@ #define TRBMAR_EL1_Attr_SHIFT 0 #define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) #define TRBTRG_EL1_TRG_SHIFT 0 -#define TRBIDR_FLAG BIT(5) -#define TRBIDR_PROG BIT(4) -#define TRBIDR_ALIGN_MASK GENMASK(3, 0) -#define TRBIDR_ALIGN_SHIFT 0 +#define TRBIDR_EL1_F BIT(5) +#define TRBIDR_EL1_P BIT(4) +#define TRBIDR_EL1_Align_MASK GENMASK(3, 0) +#define TRBIDR_EL1_Align_SHIFT 0
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 55f80fb93925..8725291cb00a 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -333,7 +333,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu)
/* Check if we have TRBE implemented and available at the host */ if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && - !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_PROG)) + !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); }
diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 3743d9085355..d661b062293f 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -95,17 +95,17 @@ static inline bool is_trbe_running(u64 trbsr)
static inline bool get_trbe_flag_update(u64 trbidr) { - return trbidr & TRBIDR_FLAG; + return trbidr & TRBIDR_EL1_F; }
static inline bool is_trbe_programmable(u64 trbidr) { - return !(trbidr & TRBIDR_PROG); + return !(trbidr & TRBIDR_EL1_P); }
static inline int get_trbe_address_align(u64 trbidr) { - return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK; + return (trbidr & TRBIDR_EL1_Align_MASK) >> TRBIDR_EL1_Align_SHIFT; }
static inline unsigned long get_trbe_write_pointer(void)
This converts TRBLIMITR_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 12 ------------ arch/arm64/tools/sysreg | 18 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.h | 9 --------- 3 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 114d38acdca5..643b7ccf6172 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,10 +235,6 @@
/*** End of Statistical Profiling Extension ***/
-/* - * TRBE Registers - */ -#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0) #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) @@ -246,14 +242,6 @@ #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
-#define TRBLIMITR_EL1_LIMIT_MASK GENMASK_ULL(63, 12) -#define TRBLIMITR_EL1_LIMIT_SHIFT 12 -#define TRBLIMITR_EL1_nVM BIT(5) -#define TRBLIMITR_EL1_TM_MASK GENMASK(4, 3) -#define TRBLIMITR_EL1_TM_SHIFT 3 -#define TRBLIMITR_EL1_FM_MASK GENMASK(2, 1) -#define TRBLIMITR_EL1_FM_SHIFT 1 -#define TRBLIMITR_EL1_E BIT(0) #define TRBPTR_EL1_PTR_MASK GENMASK_ULL(63, 0) #define TRBPTR_EL1_PTR_SHIFT 0 #define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c9a0d1fa3209..a43309607d42 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2200,3 +2200,21 @@ Sysreg ICC_NMIAR1_EL1 3 0 12 9 5 Res0 63:24 Field 23:0 INTID EndSysreg + +Sysreg TRBLIMITR_EL1 3 0 9 11 0 +Field 63:12 LIMIT +Res0 11:7 +Field 6 XE +Field 5 nVM +Enum 4:3 TM + 0b00 STOP + 0b01 IRQ + 0b11 IGNR +EndEnum +Enum 2:1 FM + 0b00 FILL + 0b01 WRAP + 0b11 CBUF +EndEnum +Field 0 E +EndSysreg diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index d661b062293f..77cbb5c63878 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -84,15 +84,6 @@ static inline bool is_trbe_running(u64 trbsr) return !(trbsr & TRBSR_EL1_S); }
-#define TRBE_TRIG_MODE_STOP 0 -#define TRBE_TRIG_MODE_IRQ 1 -#define TRBLIMITR_EL1_TM_IGNR 3 - -#define TRBLIMITR_EL1_FM_FILL 0 -#define TRBE_FILL_MODE_FILL 0 -#define TRBE_FILL_MODE_WRAP 1 -#define TRBE_FILL_MODE_CIRCULAR_BUFFER 3 - static inline bool get_trbe_flag_update(u64 trbidr) { return trbidr & TRBIDR_EL1_F;
This converts TRBPTR_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 3 --- arch/arm64/tools/sysreg | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 643b7ccf6172..13b144075381 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,15 +235,12 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
-#define TRBPTR_EL1_PTR_MASK GENMASK_ULL(63, 0) -#define TRBPTR_EL1_PTR_SHIFT 0 #define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12) #define TRBBASER_EL1_BASE_SHIFT 12 #define TRBSR_EL1_EC_MASK GENMASK(31, 26) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a43309607d42..ad6da3ea1cd5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2218,3 +2218,7 @@ Enum 2:1 FM EndEnum Field 0 E EndSysreg + +Sysreg TRBPTR_EL1 3 0 9 11 1 +Field 63:0 PTR +EndSysreg
This converts TRBBASER_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 3 --- arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 13b144075381..27d89b7ea0fa 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,14 +235,11 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
-#define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12) -#define TRBBASER_EL1_BASE_SHIFT 12 #define TRBSR_EL1_EC_MASK GENMASK(31, 26) #define TRBSR_EL1_EC_SHIFT 26 #define TRBSR_EL1_IRQ BIT(22) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ad6da3ea1cd5..c58731f69467 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2222,3 +2222,8 @@ EndSysreg Sysreg TRBPTR_EL1 3 0 9 11 1 Field 63:0 PTR EndSysreg + +Sysreg TRBBASER_EL1 3 0 9 11 2 +Field 63:12 BASE +Res0 11:0 +EndSysreg
This converts TRBSR_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 12 ------------ arch/arm64/tools/sysreg | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 27d89b7ea0fa..768d12fc4834 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,24 +235,12 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
-#define TRBSR_EL1_EC_MASK GENMASK(31, 26) -#define TRBSR_EL1_EC_SHIFT 26 -#define TRBSR_EL1_IRQ BIT(22) -#define TRBSR_EL1_TRG BIT(21) -#define TRBSR_EL1_WRAP BIT(20) -#define TRBSR_EL1_EA BIT(18) -#define TRBSR_EL1_S BIT(17) -#define TRBSR_EL1_MSS_MASK GENMASK(15, 0) -#define TRBSR_EL1_MSS_SHIFT 0 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBSR_EL1_FSC_MASK GENMASK(5, 0) -#define TRBSR_EL1_FSC_SHIFT 0 #define TRBMAR_EL1_SH_MASK GENMASK(9, 8) #define TRBMAR_EL1_SH_SHIFT 8 #define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c58731f69467..6d12980f01c7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2227,3 +2227,19 @@ Sysreg TRBBASER_EL1 3 0 9 11 2 Field 63:12 BASE Res0 11:0 EndSysreg + +Sysreg TRBSR_EL1 3 0 9 11 3 +Res0 63:56 +Field 55:32 MSS2 +Field 31:26 EC +Res0 25:24 +Field 23 DAT +Field 22 IRQ +Field 21 TRG +Field 20 WRAP +Res0 19 +Field 18 EA +Field 17 S +Res0 16 +Field 15:0 MSS +EndSysreg
This converts TRBMAR_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 5 ----- arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 768d12fc4834..131442f850dd 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,16 +235,11 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
#define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBMAR_EL1_SH_MASK GENMASK(9, 8) -#define TRBMAR_EL1_SH_SHIFT 8 -#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) -#define TRBMAR_EL1_Attr_SHIFT 0 #define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) #define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_EL1_F BIT(5) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6d12980f01c7..b3f9a545e1e7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2243,3 +2243,10 @@ Field 17 S Res0 16 Field 15:0 MSS EndSysreg + +Sysreg TRBMAR_EL1 3 0 9 11 4 +Res0 63:12 +Field 11:10 PAS +Field 9:8 SH +Field 7:0 Attr +EndSysreg
This converts TRBTRG_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 3 --- arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 131442f850dd..b3a32a67088f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,13 +235,10 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
#define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) -#define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_EL1_F BIT(5) #define TRBIDR_EL1_P BIT(4) #define TRBIDR_EL1_Align_MASK GENMASK(3, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b3f9a545e1e7..98dff7010b86 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2250,3 +2250,8 @@ Field 11:10 PAS Field 9:8 SH Field 7:0 Attr EndSysreg + +Sysreg TRBTRG_EL1 3 0 9 11 6 +Res0 63:32 +Field 31:0 TRG +EndSysreg
This converts TRBIDR_EL1 register to automatic generation without causing any functional change.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Marc Zyngier maz@kernel.org Cc: Mark Brown broonie@kernel.org Cc: Rob Herring robh@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: James Morse james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/include/asm/sysreg.h | 6 ------ arch/arm64/tools/sysreg | 9 +++++++++ 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b3a32a67088f..4f6e60f6c7cf 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -235,14 +235,8 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) - #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBIDR_EL1_F BIT(5) -#define TRBIDR_EL1_P BIT(4) -#define TRBIDR_EL1_Align_MASK GENMASK(3, 0) -#define TRBIDR_EL1_Align_SHIFT 0
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 98dff7010b86..af823803eca2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2255,3 +2255,12 @@ Sysreg TRBTRG_EL1 3 0 9 11 6 Res0 63:32 Field 31:0 TRG EndSysreg + +Sysreg TRBIDR_EL1 3 0 9 11 7 +Res0 63:12 +Field 11:8 EA +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 Align +EndSysreg
-
Anshuman Khandual