On 21/11/2023 02:24, Tao Zhang wrote:

Add property "qcom,cmb-elem-size" to support CMB(Continuous Multi-Bit) element for TPDM. The associated aggregator will read this size before it is enabled. CMB element size currently only supports 32-bit and 64-bit.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

.../bindings/arm/qcom,coresight-tpdm.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b5b247..0d9fe01a8b15 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64]

• qcom,cmb-element-size:
• description:

•  Specifies the CMB(Continuous Multi-Bit) element size supported by
  

•  the monitor. The associated aggregator will read this size before it
  

•  is enabled. CMB element size currently only supports 8-bit, 32-bit
  

•  and 64-bit.
  

• $ref: /schemas/types.yaml#/definitions/uint8
• enum: [8, 32, 64]
• qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)

@@ -110,4 +119,23 @@ examples: }; };

• tpdm@6c29000 {

•  compatible = "qcom,coresight-tpdm", "arm,primecell";
  

•  reg = <0x06c29000 0x1000>;
  

•  reg-names = "tpdm-base";
  

I think this one gives this error:

$ make dt_binding_check DT_SCHEMA_FILES=arm/qcom,coresight

DTC_CHK Documentation/devicetree/bindings/arm/qcom,coresight- tpdm.example.dtb qcom,coresight-tpdm.example.dtb: tpdm@6c29000: 'reg-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas /arm/qcom,coresight-tpdm.yaml#

•  qcom,cmb-element-size = /bits/ 8 <64>;
  

•  clocks = <&aoss_qmp>;
  

•  clock-names = "apb_pclk";
  

•  out-ports {
  

•    port {
  

•      tpdm_ipcc_out_funnel_center: endpoint {
  

•        remote-endpoint =
  

•          <&funnel_center_in_tpdm_ipcc>;
  

•      };
  

•    };
  

•  };
  

• };

...

On 21/11/2023 02:24, Tao Zhang wrote:

Read the CMB element size from the device tree. Set the register bit that controls the CMB element size of the corresponding port.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

drivers/hwtracing/coresight/coresight-tpda.c | 117 +++++++++++-------- drivers/hwtracing/coresight/coresight-tpda.h | 6 + 2 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 5f82737c37bb..e3762f38abb3 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -28,24 +28,54 @@ static bool coresight_device_is_tpdm(struct coresight_device *csdev) CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); } +static void tpdm_clear_element_size(struct coresight_device *csdev) +{

• struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
• if (drvdata->dsb_esize)

• drvdata->dsb_esize = 0;
  

• if (drvdata->cmb_esize)

• drvdata->cmb_esize = 0;
  

Why do we need the if (...) check here ?

+}

+static void tpda_set_element_size(struct tpda_drvdata *drvdata, u32 *val) +{

• if (drvdata->dsb_esize == 64)

• *val |= TPDA_Pn_CR_DSBSIZE;
  

• else if (drvdata->dsb_esize == 32)

• *val &= ~TPDA_Pn_CR_DSBSIZE;
  

• if (drvdata->cmb_esize == 64)

• *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2);
  

• else if (drvdata->cmb_esize == 32)

• *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1);
  

• else if (drvdata->cmb_esize == 8)

• *val &= ~TPDA_Pn_CR_CMBSIZE;
  

+}

/*

• • Read the DSB element size from the TPDM device

• • Read the element size from the TPDM device
  • Returns

• • The dsb element size read from the devicetree if available.

• • The element size read from the devicetree if available.
  • 0 - Otherwise, with a warning once.

This doesn't match the function ? It return 0 on success and error (-EINVAL) on failure ?

*/ -static int tpdm_read_dsb_element_size(struct coresight_device *csdev) +static int tpdm_read_element_size(struct tpda_drvdata *drvdata,

• 		  struct coresight_device *csdev)
  

  {

• int rc = 0;
• u8 size = 0;
• rc = fwnode_property_read_u8(dev_fwnode(csdev->dev.parent),

• 	"qcom,dsb-element-size", &size);
  

• int rc = -EINVAL;
• if (!fwnode_property_read_u8(dev_fwnode(csdev->dev.parent),

• 	"qcom,dsb-element-size", &drvdata->dsb_esize))
  

• rc = 0;
  

• if (!fwnode_property_read_u8(dev_fwnode(csdev->dev.parent),

• 	"qcom,cmb-element-size", &drvdata->cmb_esize))
  

• rc = 0;
  

Are we not silently resetting the error if the former failed ?

Could we not :

rc |= fwnode_...

rc |= fwnode_...

instead ?

Also what is the expectation here ? Are these properties a MUST for TPDM ?

if (rc) dev_warn_once(&csdev->dev,

• 	"Failed to read TPDM DSB Element size: %d\n", rc);
  

• 	"Failed to read TPDM Element size: %d\n", rc);
  

• return size;

• return rc; }

/* @@ -56,11 +86,12 @@ static int tpdm_read_dsb_element_size(struct coresight_device *csdev)

• Parameter "inport" is used to pass in the input port number
• of TPDA, and it is set to -1 in the recursize call.

*/ -static int tpda_get_element_size(struct coresight_device *csdev, +static int tpda_get_element_size(struct tpda_drvdata *drvdata,

• 		 struct coresight_device *csdev,
  	 int inport)
  

  {

• int dsb_size = -ENOENT;
• int i, size;

• int rc = 0;
• int i; struct coresight_device *in;

for (i = 0; i < csdev->pdata->nr_inconns; i++) { @@ -74,25 +105,21 @@ static int tpda_get_element_size(struct coresight_device *csdev, continue; if (coresight_device_is_tpdm(in)) {

• 	size = tpdm_read_dsb_element_size(in);
  

• 	if ((drvdata->dsb_esize) || (drvdata->cmb_esize))
  

• 		return -EEXIST;
  

• 	rc = tpdm_read_element_size(drvdata, in);
  

• 	if (rc)
  

• 		return rc;
  

  } else { /* Recurse down the path */

• 	size = tpda_get_element_size(in, -1);
  

• }
  

• if (size < 0)
  

• 	return size;
  

• if (dsb_size < 0) {
  

• 	/* Found a size, save it. */
  

• 	dsb_size = size;
  

• } else {
  

• 	/* Found duplicate TPDMs */
  

• 	return -EEXIST;
  

• 	rc = tpda_get_element_size(drvdata, in, -1);
  

• 	if (rc)
  

• 		return rc;
  

  } }

• return dsb_size;

• return rc; }

/* Settings pre enabling port control register */ @@ -109,7 +136,7 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) { u32 val;

• int size;

• int rc;

val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); /* @@ -117,29 +144,21 @@ static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) * Set the bit to 0 if the size is 32 * Set the bit to 1 if the size is 64 */

• size = tpda_get_element_size(drvdata->csdev, port);
• switch (size) {
• case 32:

• val &= ~TPDA_Pn_CR_DSBSIZE;
  

• break;
  

• case 64:

• val |= TPDA_Pn_CR_DSBSIZE;
  

• break;
  

• case 0:

• return -EEXIST;
  

• case -EEXIST:

• tpdm_clear_element_size(drvdata->csdev);
• rc = tpda_get_element_size(drvdata, drvdata->csdev, port);
• if (!rc && ((drvdata->dsb_esize) || (drvdata->cmb_esize))) {

• tpda_set_element_size(drvdata, &val);
  

• /* Enable the port */
  

• val |= TPDA_Pn_CR_ENA;
  

• writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
  

• } else if (rc == -EEXIST) dev_warn_once(&drvdata->csdev->dev,

• 	"Detected multiple TPDMs on port %d", -EEXIST);
  

• return -EEXIST;
  

• default:

• return -EINVAL;
  

• }
• /* Enable the port */
• val |= TPDA_Pn_CR_ENA;
• writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));

• 	      "Detected multiple TPDMs on port %d", -EEXIST);
  

• else

• dev_warn_once(&drvdata->csdev->dev,
  

• 	      "Didn't find TPDM elem size");
  

"element size"

• return 0;

• return rc; }

static int __tpda_enable(struct tpda_drvdata *drvdata, int port) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index b3b38fd41b64..29164fd9711f 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) +/* Aggregator port CMB data set element size bit */ +#define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) @@ -25,6 +27,8 @@

• @csdev: component vitals needed by the framework.
• @spinlock: lock for the drvdata value.
• @enable: enable status of the component.

• • @dsb_esize Record the DSB element size.
• • @cmb_esize Record the CMB element size.
  */ struct tpda_drvdata { void __iomem *base;

@@ -32,6 +36,8 @@ struct tpda_drvdata { struct coresight_device *csdev; spinlock_t spinlock; u8 atid;

• u8 dsb_esize;
• u8 cmb_esize; };

#endif /* _CORESIGHT_CORESIGHT_TPDA_H */

Suzuki

On 19/12/2023 02:13, Tao Zhang wrote:

On 12/18/2023 6:27 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote:

...

Read the CMB element size from the device tree. Set the register bit that controls the CMB element size of the corresponding port.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

drivers/hwtracing/coresight/coresight-tpda.c | 117 +++++++++++--------   drivers/hwtracing/coresight/coresight-tpda.h |   6 +   2 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 5f82737c37bb..e3762f38abb3 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -28,24 +28,54 @@ static bool coresight_device_is_tpdm(struct coresight_device *csdev)               CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM);   }   +static void tpdm_clear_element_size(struct coresight_device *csdev) +{ +    struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

+    if (drvdata->dsb_esize) +        drvdata->dsb_esize = 0; +    if (drvdata->cmb_esize) +        drvdata->cmb_esize = 0;

Why do we need the if (...) check here ?

The element size of all the TPDM sub-unit should be set to 0 here.

I will update this in the next patch series.

...

...

+}

+static void tpda_set_element_size(struct tpda_drvdata *drvdata, u32 *val) +{

+    if (drvdata->dsb_esize == 64) +        *val |= TPDA_Pn_CR_DSBSIZE; +    else if (drvdata->dsb_esize == 32) +        *val &= ~TPDA_Pn_CR_DSBSIZE;

+    if (drvdata->cmb_esize == 64) +        *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2); +    else if (drvdata->cmb_esize == 32) +        *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1); +    else if (drvdata->cmb_esize == 8) +        *val &= ~TPDA_Pn_CR_CMBSIZE; +}

...

/*

• • Read the DSB element size from the TPDM device

• • Read the element size from the TPDM device

* Returns

• *    The dsb element size read from the devicetree if available.

• *    The element size read from the devicetree if available.

*    0 - Otherwise, with a warning once.

This doesn't match the function ? It return 0 on success and error (-EINVAL) on failure ?

0 means the element size property is found from the devicetree.

Otherwise, it will return error(-EINVAL).

I will update this in the next patch series.

...

...

*/ -static int tpdm_read_dsb_element_size(struct coresight_device *csdev) +static int tpdm_read_element_size(struct tpda_drvdata *drvdata, +                  struct coresight_device *csdev)   { -    int rc = 0; -    u8 size = 0;

-    rc = fwnode_property_read_u8(dev_fwnode(csdev->dev.parent), -            "qcom,dsb-element-size", &size); +    int rc = -EINVAL;

+    if (!fwnode_property_read_u8(dev_fwnode(csdev->dev.parent), +            "qcom,dsb-element-size", &drvdata->dsb_esize)) +        rc = 0; +    if (!fwnode_property_read_u8(dev_fwnode(csdev->dev.parent), +            "qcom,cmb-element-size", &drvdata->cmb_esize)) +        rc = 0;

Are we not silently resetting the error if the former failed ?

Could we not :

rc |= fwnode_...

rc |= fwnode_...

instead ?

Also what is the expectation here ? Are these properties a MUST for TPDM ?

The TPDM must have one of the element size property. As long as one

Please add a comment in the function. Someone else might try to "fix" it otherwise.

Suzuki

can be found, this TPDM configuration can be considered valid. So this

function will return 0 if one of the element size property is found.

Best,

Tao

...

...

if (rc)           dev_warn_once(&csdev->dev, -            "Failed to read TPDM DSB Element size: %d\n", rc); +            "Failed to read TPDM Element size: %d\n", rc);   -    return size; +    return rc;   }     /* @@ -56,11 +86,12 @@ static int tpdm_read_dsb_element_size(struct coresight_device *csdev)    * Parameter "inport" is used to pass in the input port number    * of TPDA, and it is set to -1 in the recursize call.    */ -static int tpda_get_element_size(struct coresight_device *csdev, +static int tpda_get_element_size(struct tpda_drvdata *drvdata, +                 struct coresight_device *csdev,                    int inport)   { -    int dsb_size = -ENOENT; -    int i, size; +    int rc = 0; +    int i;       struct coresight_device *in;         for (i = 0; i < csdev->pdata->nr_inconns; i++) { @@ -74,25 +105,21 @@ static int tpda_get_element_size(struct coresight_device *csdev,               continue;             if (coresight_device_is_tpdm(in)) { -            size = tpdm_read_dsb_element_size(in); +            if ((drvdata->dsb_esize) || (drvdata->cmb_esize)) +                return -EEXIST; +            rc = tpdm_read_element_size(drvdata, in); +            if (rc) +                return rc;           } else {               /* Recurse down the path */ -            size = tpda_get_element_size(in, -1); -        }

-        if (size < 0) -            return size;

-        if (dsb_size < 0) { -            /* Found a size, save it. */ -            dsb_size = size; -        } else { -            /* Found duplicate TPDMs */ -            return -EEXIST; +            rc = tpda_get_element_size(drvdata, in, -1); +            if (rc) +                return rc;           }       }   -    return dsb_size;

+    return rc;   }     /* Settings pre enabling port control register */ @@ -109,7 +136,7 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)   static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)   {       u32 val; -    int size; +    int rc;         val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));       /* @@ -117,29 +144,21 @@ static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)        * Set the bit to 0 if the size is 32        * Set the bit to 1 if the size is 64        */ -    size = tpda_get_element_size(drvdata->csdev, port); -    switch (size) { -    case 32: -        val &= ~TPDA_Pn_CR_DSBSIZE; -        break; -    case 64: -        val |= TPDA_Pn_CR_DSBSIZE; -        break; -    case 0: -        return -EEXIST; -    case -EEXIST: +    tpdm_clear_element_size(drvdata->csdev); +    rc = tpda_get_element_size(drvdata, drvdata->csdev, port); +    if (!rc && ((drvdata->dsb_esize) || (drvdata->cmb_esize))) { +        tpda_set_element_size(drvdata, &val); +        /* Enable the port */ +        val |= TPDA_Pn_CR_ENA; +        writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +    } else if (rc == -EEXIST)           dev_warn_once(&drvdata->csdev->dev, -            "Detected multiple TPDMs on port %d", -EEXIST); -        return -EEXIST; -    default: -        return -EINVAL; -    }

-    /* Enable the port */ -    val |= TPDA_Pn_CR_ENA; -    writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +                  "Detected multiple TPDMs on port %d", -EEXIST); +    else +        dev_warn_once(&drvdata->csdev->dev, +                  "Didn't find TPDM elem size");

"element size"

...

-    return 0; +    return rc;   }     static int __tpda_enable(struct tpda_drvdata *drvdata, int port) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index b3b38fd41b64..29164fd9711f 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@   #define TPDA_Pn_CR(n)        (0x004 + (n * 4))   /* Aggregator port enable bit */   #define TPDA_Pn_CR_ENA        BIT(0) +/* Aggregator port CMB data set element size bit */ +#define TPDA_Pn_CR_CMBSIZE        GENMASK(7, 6)   /* Aggregator port DSB data set element size bit */   #define TPDA_Pn_CR_DSBSIZE        BIT(8)   @@ -25,6 +27,8 @@    * @csdev:      component vitals needed by the framework.    * @spinlock:   lock for the drvdata value.    * @enable:     enable status of the component.

• • @dsb_esize   Record the DSB element size.
• • @cmb_esize   Record the CMB element size.

*/   struct tpda_drvdata {       void __iomem        *base; @@ -32,6 +36,8 @@ struct tpda_drvdata {       struct coresight_device    *csdev;       spinlock_t        spinlock;       u8            atid; +    u8            dsb_esize; +    u8            cmb_esize;   };     #endif  /* _CORESIGHT_CORESIGHT_TPDA_H */

Suzuki

On 18/12/2023 10:27, Suzuki K Poulose wrote:

On 21/11/2023 02:24, Tao Zhang wrote:

...

Read the CMB element size from the device tree. Set the register bit that controls the CMB element size of the corresponding port.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

drivers/hwtracing/coresight/coresight-tpda.c | 117 +++++++++++--------   drivers/hwtracing/coresight/coresight-tpda.h |   6 +   2 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 5f82737c37bb..e3762f38abb3 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -28,24 +28,54 @@ static bool coresight_device_is_tpdm(struct coresight_device *csdev)               CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM);   } +static void tpdm_clear_element_size(struct coresight_device *csdev) +{ +    struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

+    if (drvdata->dsb_esize) +        drvdata->dsb_esize = 0; +    if (drvdata->cmb_esize) +        drvdata->cmb_esize = 0;

Why do we need the if (...) check here ?

...

+}

+static void tpda_set_element_size(struct tpda_drvdata *drvdata, u32 *val) +{

+    if (drvdata->dsb_esize == 64) +        *val |= TPDA_Pn_CR_DSBSIZE; +    else if (drvdata->dsb_esize == 32) +        *val &= ~TPDA_Pn_CR_DSBSIZE;

+    if (drvdata->cmb_esize == 64) +        *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2); +    else if (drvdata->cmb_esize == 32) +        *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1); +    else if (drvdata->cmb_esize == 8) +        *val &= ~TPDA_Pn_CR_CMBSIZE; +}

...

/*

• • Read the DSB element size from the TPDM device

• • Read the element size from the TPDM device

* Returns

• *    The dsb element size read from the devicetree if available.

• *    The element size read from the devicetree if available.

*    0 - Otherwise, with a warning once.

This doesn't match the function ? It return 0 on success and error (-EINVAL) on failure ?

...

*/ -static int tpdm_read_dsb_element_size(struct coresight_device *csdev) +static int tpdm_read_element_size(struct tpda_drvdata *drvdata, +                  struct coresight_device *csdev)   { -    int rc = 0; -    u8 size = 0;

-    rc = fwnode_property_read_u8(dev_fwnode(csdev->dev.parent), -            "qcom,dsb-element-size", &size); +    int rc = -EINVAL;

+    if (!fwnode_property_read_u8(dev_fwnode(csdev->dev.parent), +            "qcom,dsb-element-size", &drvdata->dsb_esize)) +        rc = 0; +    if (!fwnode_property_read_u8(dev_fwnode(csdev->dev.parent), +            "qcom,cmb-element-size", &drvdata->cmb_esize))

At this point we have the csdev->dev.parent as the TPDM device and with:

#include <coresight-tpdm.h>

struct tpdm_drvdata *tpdm_data = get_drvdata(csdev->dev.parent);

if (tpdm_has_cmb(tpdm_data)) { rc = fwnode_...(... "qcom,cmb-element-size"...) }

if (tpdm_has_dsb(tpdm_data)) { rc = fwnode_...(..., "qcom,dsb-element-size"..) }

Suzuki

...

+        rc = 0;

Are we not silently resetting the error if the former failed ?

Could we not :

rc |= fwnode_...

rc |= fwnode_...

instead ?

Also what is the expectation here ? Are these properties a MUST for TPDM ?

...

if (rc)           dev_warn_once(&csdev->dev, -            "Failed to read TPDM DSB Element size: %d\n", rc); +            "Failed to read TPDM Element size: %d\n", rc); -    return size; +    return rc;   }   /* @@ -56,11 +86,12 @@ static int tpdm_read_dsb_element_size(struct coresight_device *csdev)    * Parameter "inport" is used to pass in the input port number    * of TPDA, and it is set to -1 in the recursize call.    */ -static int tpda_get_element_size(struct coresight_device *csdev, +static int tpda_get_element_size(struct tpda_drvdata *drvdata, +                 struct coresight_device *csdev,                    int inport)   { -    int dsb_size = -ENOENT; -    int i, size; +    int rc = 0; +    int i;       struct coresight_device *in;       for (i = 0; i < csdev->pdata->nr_inconns; i++) { @@ -74,25 +105,21 @@ static int tpda_get_element_size(struct coresight_device *csdev,               continue;           if (coresight_device_is_tpdm(in)) { -            size = tpdm_read_dsb_element_size(in); +            if ((drvdata->dsb_esize) || (drvdata->cmb_esize)) +                return -EEXIST; +            rc = tpdm_read_element_size(drvdata, in); +            if (rc) +                return rc;           } else {               /* Recurse down the path */ -            size = tpda_get_element_size(in, -1); -        }

-        if (size < 0) -            return size;

-        if (dsb_size < 0) { -            /* Found a size, save it. */ -            dsb_size = size; -        } else { -            /* Found duplicate TPDMs */ -            return -EEXIST; +            rc = tpda_get_element_size(drvdata, in, -1); +            if (rc) +                return rc;           }       } -    return dsb_size;

+    return rc;   }   /* Settings pre enabling port control register */ @@ -109,7 +136,7 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)   static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)   {       u32 val; -    int size; +    int rc;       val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));       /* @@ -117,29 +144,21 @@ static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)        * Set the bit to 0 if the size is 32        * Set the bit to 1 if the size is 64        */ -    size = tpda_get_element_size(drvdata->csdev, port); -    switch (size) { -    case 32: -        val &= ~TPDA_Pn_CR_DSBSIZE; -        break; -    case 64: -        val |= TPDA_Pn_CR_DSBSIZE; -        break; -    case 0: -        return -EEXIST; -    case -EEXIST: +    tpdm_clear_element_size(drvdata->csdev); +    rc = tpda_get_element_size(drvdata, drvdata->csdev, port); +    if (!rc && ((drvdata->dsb_esize) || (drvdata->cmb_esize))) { +        tpda_set_element_size(drvdata, &val); +        /* Enable the port */ +        val |= TPDA_Pn_CR_ENA; +        writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +    } else if (rc == -EEXIST)           dev_warn_once(&drvdata->csdev->dev, -            "Detected multiple TPDMs on port %d", -EEXIST); -        return -EEXIST; -    default: -        return -EINVAL; -    }

-    /* Enable the port */ -    val |= TPDA_Pn_CR_ENA; -    writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +                  "Detected multiple TPDMs on port %d", -EEXIST); +    else +        dev_warn_once(&drvdata->csdev->dev, +                  "Didn't find TPDM elem size");

"element size"

...

-    return 0; +    return rc;   }   static int __tpda_enable(struct tpda_drvdata *drvdata, int port) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index b3b38fd41b64..29164fd9711f 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@   #define TPDA_Pn_CR(n)        (0x004 + (n * 4))   /* Aggregator port enable bit */   #define TPDA_Pn_CR_ENA        BIT(0) +/* Aggregator port CMB data set element size bit */ +#define TPDA_Pn_CR_CMBSIZE        GENMASK(7, 6)   /* Aggregator port DSB data set element size bit */   #define TPDA_Pn_CR_DSBSIZE        BIT(8) @@ -25,6 +27,8 @@    * @csdev:      component vitals needed by the framework.    * @spinlock:   lock for the drvdata value.    * @enable:     enable status of the component.

• • @dsb_esize   Record the DSB element size.
• • @cmb_esize   Record the CMB element size.

*/   struct tpda_drvdata {       void __iomem        *base; @@ -32,6 +36,8 @@ struct tpda_drvdata {       struct coresight_device    *csdev;       spinlock_t        spinlock;       u8            atid; +    u8            dsb_esize; +    u8            cmb_esize;   };   #endif  /* _CORESIGHT_CORESIGHT_TPDA_H */

Suzuki

On 12/18/2023 6:34 PM, Suzuki K Poulose wrote:

On 21/11/2023 02:24, Tao Zhang wrote:

...

CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit can be enabled for data collection by writing 1 to the first bit of CMB_CR register. This change is to add enable/disable function for CMB dataset by writing CMB_CR register.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com

---

drivers/hwtracing/coresight/coresight-tpdm.c | 31 ++++++++++++++++++++   drivers/hwtracing/coresight/coresight-tpdm.h |  8 +++++   2 files changed, 39 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 97654aa4b772..c8bb38822e08 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -131,6 +131,11 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)       return (drvdata->datasets & TPDM_PIDR0_DS_DSB);   }   +static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata) +{ +    return (drvdata->datasets & TPDM_PIDR0_DS_CMB); +}

static umode_t tpdm_dsb_is_visible(struct kobject *kobj,                      struct attribute *attr, int n)   { @@ -267,6 +272,17 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);   }   +static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) +{ +    u32 val;

+    val = readl_relaxed(drvdata->base + TPDM_CMB_CR); +    val |= TPDM_CMB_CR_ENA;

+    /* Set the enable bit of CMB control register to 1 */ +    writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +}

/*    * TPDM enable operations    * The TPDM or Monitor serves as data collection component for various @@ -281,6 +297,8 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata)         if (tpdm_has_dsb_dataset(drvdata))           tpdm_enable_dsb(drvdata); +    if (tpdm_has_cmb_dataset(drvdata)) +        tpdm_enable_cmb(drvdata);

Don't we need to add this check in the "property read" section ? Otherwise, we could generate warnings unnecessarily ?

i.e, if (tpdm_has_cmb_..())       rc |= fwnode_..read_property(cmb-elem-size...)

Similarly for DSB.

TPDM and TPDA are two independent hardware. If you want to modify them in this way, the

two independent drivers will be coupled to each other. At the same time, this configuration

is manually set in the devicetree by the users, and this check cannot avoid manual setting errors.

Even if the configuration is wrong, it will not cause the driver to stop working, it will only cause

the data to be lost from the TPDM.

...

CS_LOCK(drvdata->base);   } @@ -314,6 +332,17 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);   }   +static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) +{ +    u32 val;

+    val = readl_relaxed(drvdata->base + TPDM_CMB_CR); +    val &= ~TPDM_CMB_CR_ENA;

+    /* Set the enable bit of CMB control register to 0 */ +    writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +}

/* TPDM disable operations */   static void __tpdm_disable(struct tpdm_drvdata *drvdata)   { @@ -321,6 +350,8 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata)         if (tpdm_has_dsb_dataset(drvdata))           tpdm_disable_dsb(drvdata); +    if (tpdm_has_cmb_dataset(drvdata)) +        tpdm_disable_cmb(drvdata);

minor nit: Instead of having these :

if (tpdm_has_XY_()         tpdm_{enable/disable}_XY_() I prefer :

tpdm_{enable/disable}_XY_

and the helper take care of returning early if the feature is not present.

Does the following sample modification meet your expectation? static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) {     u32 val;

if (tpdm_has_dsb_dataset(drvdata)) {         /* Set the enable bit of DSB control register to 0 */         val = readl_relaxed(drvdata->base + TPDM_DSB_CR);         val &= ~TPDM_DSB_CR_ENA;         writel_relaxed(val, drvdata->base + TPDM_DSB_CR);     } }

static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) {     u32 val;

if (tpdm_has_cmb_dataset(drvdata)) {         val = readl_relaxed(drvdata->base + TPDM_CMB_CR);         val &= ~TPDM_CMB_CR_ENA;

/* Set the enable bit of CMB control register to 0 */         writel_relaxed(val, drvdata->base + TPDM_CMB_CR);     } }

/* TPDM disable operations */ static void __tpdm_disable(struct tpdm_drvdata *drvdata) {     CS_UNLOCK(drvdata->base);

tpdm_disable_dsb(drvdata);     tpdm_disable_cmb(drvdata);

CS_LOCK(drvdata->base);

}

Best,

Tao

Suzuki

...

CS_LOCK(drvdata->base);   } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4115b2a17b8d..0098c58dfdd6 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -9,6 +9,12 @@   /* The max number of the datasets that TPDM supports */   #define TPDM_DATASETS       7   +/* CMB Subunit Registers */ +#define TPDM_CMB_CR        (0xA00)

+/* Enable bit for CMB subunit */ +#define TPDM_CMB_CR_ENA        BIT(0)

/* DSB Subunit Registers */   #define TPDM_DSB_CR        (0x780)   #define TPDM_DSB_TIER        (0x784) @@ -79,10 +85,12 @@    *    * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0    * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0

• • PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0

*/     #define TPDM_PIDR0_DS_IMPDEF    BIT(0)   #define TPDM_PIDR0_DS_DSB    BIT(1) +#define TPDM_PIDR0_DS_CMB    BIT(2)     #define TPDM_DSB_MAX_LINES    256   /* MAX number of EDCR registers */

On 12/19/2023 9:56 PM, Suzuki K Poulose wrote:

On 19/12/2023 09:22, Tao Zhang wrote:

...

On 12/18/2023 6:34 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote:

...

CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit can be enabled for data collection by writing 1 to the first bit of CMB_CR register. This change is to add enable/disable function for CMB dataset by writing CMB_CR register.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com

---

drivers/hwtracing/coresight/coresight-tpdm.c | 31 ++++++++++++++++++++   drivers/hwtracing/coresight/coresight-tpdm.h |  8 +++++   2 files changed, 39 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 97654aa4b772..c8bb38822e08 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -131,6 +131,11 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)       return (drvdata->datasets & TPDM_PIDR0_DS_DSB);   }   +static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata) +{ +    return (drvdata->datasets & TPDM_PIDR0_DS_CMB); +}

static umode_t tpdm_dsb_is_visible(struct kobject *kobj,                      struct attribute *attr, int n)   { @@ -267,6 +272,17 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);   }   +static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) +{ +    u32 val;

+    val = readl_relaxed(drvdata->base + TPDM_CMB_CR); +    val |= TPDM_CMB_CR_ENA;

+    /* Set the enable bit of CMB control register to 1 */ +    writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +}

/*    * TPDM enable operations    * The TPDM or Monitor serves as data collection component for various @@ -281,6 +297,8 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata)         if (tpdm_has_dsb_dataset(drvdata))           tpdm_enable_dsb(drvdata); +    if (tpdm_has_cmb_dataset(drvdata)) +        tpdm_enable_cmb(drvdata);

Don't we need to add this check in the "property read" section ? Otherwise, we could generate warnings unnecessarily ?

i.e, if (tpdm_has_cmb_..())       rc |= fwnode_..read_property(cmb-elem-size...)

Similarly for DSB.

TPDM and TPDA are two independent hardware. If you want to modify them in this way, the

You don't have to, as long as the header files are included ?

Read my response in the other patch, where it applies.

Got it. I will update in the next patch series.

Best,

Tao

Suzuki

...

two independent drivers will be coupled to each other. At the same time, this configuration

is manually set in the devicetree by the users, and this check cannot avoid manual setting errors.

Even if the configuration is wrong, it will not cause the driver to stop working, it will only cause

the data to be lost from the TPDM.

...

...

CS_LOCK(drvdata->base);   } @@ -314,6 +332,17 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);   }   +static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) +{ +    u32 val;

+    val = readl_relaxed(drvdata->base + TPDM_CMB_CR); +    val &= ~TPDM_CMB_CR_ENA;

+    /* Set the enable bit of CMB control register to 0 */ +    writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +}

/* TPDM disable operations */   static void __tpdm_disable(struct tpdm_drvdata *drvdata)   { @@ -321,6 +350,8 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata)         if (tpdm_has_dsb_dataset(drvdata))           tpdm_disable_dsb(drvdata); +    if (tpdm_has_cmb_dataset(drvdata)) +        tpdm_disable_cmb(drvdata);

minor nit: Instead of having these :

if (tpdm_has_XY_()         tpdm_{enable/disable}_XY_() I prefer :

tpdm_{enable/disable}_XY_

and the helper take care of returning early if the feature is not present.

Does the following sample modification meet your expectation? static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) {      u32 val;

if (tpdm_has_dsb_dataset(drvdata)) {          /* Set the enable bit of DSB control register to 0 */          val = readl_relaxed(drvdata->base + TPDM_DSB_CR);          val &= ~TPDM_DSB_CR_ENA;          writel_relaxed(val, drvdata->base + TPDM_DSB_CR);      } }

static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) {      u32 val;

if (tpdm_has_cmb_dataset(drvdata)) {          val = readl_relaxed(drvdata->base + TPDM_CMB_CR);          val &= ~TPDM_CMB_CR_ENA;

/* Set the enable bit of CMB control register to 0 */          writel_relaxed(val, drvdata->base + TPDM_CMB_CR);      } }

/* TPDM disable operations */ static void __tpdm_disable(struct tpdm_drvdata *drvdata) {      CS_UNLOCK(drvdata->base);

tpdm_disable_dsb(drvdata);      tpdm_disable_cmb(drvdata);

Yes, thats exactly I was looking for.

Got it. I will update in the next patch series.

Best,

Tao

...

CS_LOCK(drvdata->base);

}

Best,

Tao

...

Suzuki

...

CS_LOCK(drvdata->base);   } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4115b2a17b8d..0098c58dfdd6 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -9,6 +9,12 @@   /* The max number of the datasets that TPDM supports */   #define TPDM_DATASETS       7   +/* CMB Subunit Registers */ +#define TPDM_CMB_CR        (0xA00)

+/* Enable bit for CMB subunit */ +#define TPDM_CMB_CR_ENA        BIT(0)

/* DSB Subunit Registers */   #define TPDM_DSB_CR        (0x780)   #define TPDM_DSB_TIER        (0x784) @@ -79,10 +85,12 @@    *    * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0    * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0

• • PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0

*/     #define TPDM_PIDR0_DS_IMPDEF    BIT(0)   #define TPDM_PIDR0_DS_DSB    BIT(1) +#define TPDM_PIDR0_DS_CMB    BIT(2)     #define TPDM_DSB_MAX_LINES    256   /* MAX number of EDCR registers */

On 21/11/2023 02:24, Tao Zhang wrote:

CMB_TIER register is CMB subunit timestamp insertion enable register. Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB CTI timestamp request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp for all packets.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com

---

.../testing/sysfs-bus-coresight-devices-tpdm | 35 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 116 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++ 3 files changed, 162 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 53662ce7c2d0..e0b77107be13 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -214,3 +214,38 @@ KernelVersion 6.7 Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com Description: (RW) Set/Get the mask of the pattern for the CMB subunit TPDM.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts +Date: September 2023 +KernelVersion 6.7 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (Write) Set the pattern timestamp of CMB tpdm. Read
  

• the pattern timestamp of CMB tpdm.
  

• Accepts only one of the 2 values -  0 or 1.
  

• 0 : Disable CMB pattern timestamp.
  

• 1 : Enable CMB pattern timestamp.
  

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts +Date: September 2023 +KernelVersion 6.7 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the trigger timestamp of the CMB for tpdm.
  

• Accepts only one of the 2 values -  0 or 1.
  

• 0 : Set the CMB trigger type to false
  

• 1 : Set the CMB trigger type to true
  

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all +Date: September 2023 +KernelVersion 6.7 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Read or write the status of timestamp upon all interface.
  

• Only value 0 and 1  can be written to this node. Set this node to 1 to requeset
  

• timestamp to all trace packet.
  

• Accepts only one of the 2 values -  0 or 1.
  

• 0 : Disable the timestamp of all trace packets.
  

• 1 : Enable the timestamp of all trace packets.
  

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 894d4309f1c7..f6cda5616e84 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -331,6 +331,36 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void set_cmb_tier(struct tpdm_drvdata *drvdata) +{

• u32 val;
• val = readl_relaxed(drvdata->base + TPDM_CMB_TIER);
• /* Clear all relevant fields */
• val &= ~(TPDM_CMB_TIER_PATT_TSENAB | TPDM_CMB_TIER_TS_ALL |

•  TPDM_CMB_TIER_XTRIG_TSENAB);
  

• /* Set pattern timestamp type and enablement */
• if (drvdata->cmb->patt_ts)

• val |= TPDM_CMB_TIER_PATT_TSENAB;
  

-- cut --

• else

• val &= ~TPDM_CMB_TIER_PATT_TSENAB;
  

All the else cases in this function are superfluous. Please remove all of them.

• /* Set trigger timestamp */
• if (drvdata->cmb->trig_ts)

• val |= TPDM_CMB_TIER_XTRIG_TSENAB;
  

• else

• val &= ~TPDM_CMB_TIER_XTRIG_TSENAB;
  

• /* Set all timestamp enablement*/
• if (drvdata->cmb->ts_all)

• val |= TPDM_CMB_TIER_TS_ALL;
  

• else

• val &= ~TPDM_CMB_TIER_TS_ALL;
  

• writel_relaxed(val, drvdata->base + TPDM_CMB_TIER);

+}

• static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) { u32 val, i;

@@ -347,6 +377,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) drvdata->base + TPDM_CMB_XPMR(i)); }

• set_cmb_tier(drvdata);
• val = readl_relaxed(drvdata->base + TPDM_CMB_CR); /*
  • Set to 0 for continuous CMB collection mode,

@@ -695,9 +727,17 @@ static ssize_t enable_ts_show(struct device *dev, char *buf) { struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

• ssize_t size = 0;

• return sysfs_emit(buf, "%u\n",

• 	 (unsigned int)drvdata->dsb->patt_ts);
  

• if (tpdm_has_dsb_dataset(drvdata))

• size = sysfs_emit(buf, "%u\n",
  

• 		 (unsigned int)drvdata->dsb->patt_ts);
  

• if (tpdm_has_cmb_dataset(drvdata))

• size = sysfs_emit(buf, "%u\n",
  

• 		 (unsigned int)drvdata->cmb->patt_ts);
  

Why does this need to show two values ? This must only show ONE value. How you deduce that might be based on the availability of the feature set. Or store the TS value in the drvdata and use that instead for controlling CMB/DSB.

Also, the sysfs documentation needs update, if this is going to control the CMB.

Suzuki

• return size; }

/* @@ -715,8 +755,13 @@ static ssize_t enable_ts_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock);

• drvdata->dsb->patt_ts = !!val;

• if (tpdm_has_dsb_dataset(drvdata))

• drvdata->dsb->patt_ts = !!val;
  

• if (tpdm_has_cmb_dataset(drvdata))

• drvdata->cmb->patt_ts = !!val;
  

  spin_unlock(&drvdata->spinlock);
• return size; } static DEVICE_ATTR_RW(enable_ts);

@@ -851,6 +896,68 @@ static ssize_t cmb_mode_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_mode); +static ssize_t cmb_ts_all_show(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       char *buf)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sysfs_emit(buf, "%u\n",

• 	  (unsigned int)drvdata->cmb->ts_all);
  

+}

+static ssize_t cmb_ts_all_store(struct device *dev,

• 		struct device_attribute *attr,
  

• 		const char *buf,
  

• 		size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• if (val)

• drvdata->cmb->ts_all = true;
  

• else

• drvdata->cmb->ts_all = false;
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(cmb_ts_all);

+static ssize_t cmb_trig_ts_show(struct device *dev,

• 		struct device_attribute *attr,
  

• 		char *buf)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sysfs_emit(buf, "%u\n",

• 	  (unsigned int)drvdata->cmb->trig_ts);
  

+}

+static ssize_t cmb_trig_ts_store(struct device *dev,

• 		 struct device_attribute *attr,
  

• 		 const char *buf,
  

• 		 size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• if (val)

• drvdata->cmb->trig_ts = true;
  

• else

• drvdata->cmb->trig_ts = false;
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(cmb_trig_ts);

• static struct attribute *tpdm_dsb_edge_attrs[] = { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr,

@@ -973,6 +1080,7 @@ static struct attribute *tpdm_cmb_patt_attrs[] = { CMB_PATT_ATTR(1), CMB_PATT_MASK_ATTR(0), CMB_PATT_MASK_ATTR(1),

• &dev_attr_enable_ts.attr, NULL, };

@@ -985,6 +1093,8 @@ static struct attribute *tpdm_dsb_attrs[] = { static struct attribute *tpdm_cmb_attrs[] = { &dev_attr_cmb_mode.attr,

• &dev_attr_cmb_ts_all.attr,
• &dev_attr_cmb_trig_ts.attr, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index e90d008c1cb2..65b7ca6c4077 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -11,6 +11,8 @@ /* CMB Subunit Registers */ #define TPDM_CMB_CR (0xA00) +/*CMB subunit timestamp insertion enable register*/ +#define TPDM_CMB_TIER (0xA04) /*CMB subunit timestamp pattern registers*/ #define TPDM_CMB_TPR(n) (0xA08 + (n * 4)) /*CMB subunit timestamp pattern mask registers*/ @@ -24,6 +26,12 @@ #define TPDM_CMB_CR_ENA BIT(0) /* Trace collection mode for CMB subunit */ #define TPDM_CMB_CR_MODE BIT(1) +/* Timestamp control for pattern match */ +#define TPDM_CMB_TIER_PATT_TSENAB BIT(0) +/* CMB CTI timestamp request */ +#define TPDM_CMB_TIER_XTRIG_TSENAB BIT(1) +/* For timestamp fo all trace */ +#define TPDM_CMB_TIER_TS_ALL BIT(2) /*Patten register number*/ #define TPDM_CMB_MAX_PATT 2 @@ -217,6 +225,9 @@ struct dsb_dataset {

• @patt_mask: Save value for pattern mask
• @trig_patt: Save value for trigger pattern
• @trig_patt_mask: Save value for trigger pattern mask

• • @patt_ts: Indicates if pattern match for timestamp is enabled.
• • @trig_ts: Indicates if CTI trigger for timestamp is enabled.
• • @ts_all: Indicates if timestamp is enabled for all packets.
  */ struct cmb_dataset { u32 trace_mode;

@@ -224,6 +235,9 @@ struct cmb_dataset { u32 patt_mask[TPDM_CMB_MAX_PATT]; u32 trig_patt[TPDM_CMB_MAX_PATT]; u32 trig_patt_mask[TPDM_CMB_MAX_PATT];

• bool patt_ts;
• bool trig_ts;
• bool ts_all; };

/**

On 19/12/2023 02:43, Tao Zhang wrote:

On 12/18/2023 6:46 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote:

...

CMB_TIER register is CMB subunit timestamp insertion enable register. Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB CTI timestamp request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp for all packets.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com

---

.../testing/sysfs-bus-coresight-devices-tpdm  |  35 ++++++   drivers/hwtracing/coresight/coresight-tpdm.c  | 116 +++++++++++++++++-   drivers/hwtracing/coresight/coresight-tpdm.h  |  14 +++   3 files changed, 162 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 53662ce7c2d0..e0b77107be13 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -214,3 +214,38 @@ KernelVersion    6.7   Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com   Description:           (RW) Set/Get the mask of the pattern for the CMB subunit TPDM.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (Write) Set the pattern timestamp of CMB tpdm. Read +        the pattern timestamp of CMB tpdm.

+        Accepts only one of the 2 values -  0 or 1. +        0 : Disable CMB pattern timestamp. +        1 : Enable CMB pattern timestamp.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the trigger timestamp of the CMB for tpdm.

+        Accepts only one of the 2 values -  0 or 1. +        0 : Set the CMB trigger type to false +        1 : Set the CMB trigger type to true

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Read or write the status of timestamp upon all interface. +        Only value 0 and 1  can be written to this node. Set this node to 1 to requeset +        timestamp to all trace packet. +        Accepts only one of the 2 values -  0 or 1. +        0 : Disable the timestamp of all trace packets. +        1 : Enable the timestamp of all trace packets. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 894d4309f1c7..f6cda5616e84 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -331,6 +331,36 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);   }   +static void set_cmb_tier(struct tpdm_drvdata *drvdata) +{ +    u32 val;

+    val = readl_relaxed(drvdata->base + TPDM_CMB_TIER);

+    /* Clear all relevant fields */ +    val &= ~(TPDM_CMB_TIER_PATT_TSENAB | TPDM_CMB_TIER_TS_ALL | +         TPDM_CMB_TIER_XTRIG_TSENAB);

+    /* Set pattern timestamp type and enablement */ +    if (drvdata->cmb->patt_ts) +        val |= TPDM_CMB_TIER_PATT_TSENAB;

-- cut --

...

+    else +        val &= ~TPDM_CMB_TIER_PATT_TSENAB;

All the else cases in this function are superfluous. Please remove all of them.

I will update this in the next patch.

...

...

+    /* Set trigger timestamp */ +    if (drvdata->cmb->trig_ts) +        val |= TPDM_CMB_TIER_XTRIG_TSENAB; +    else +        val &= ~TPDM_CMB_TIER_XTRIG_TSENAB;

+    /* Set all timestamp enablement*/ +    if (drvdata->cmb->ts_all) +        val |= TPDM_CMB_TIER_TS_ALL; +    else +        val &= ~TPDM_CMB_TIER_TS_ALL; +    writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); +}

static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)   {       u32 val, i; @@ -347,6 +377,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)                   drvdata->base + TPDM_CMB_XPMR(i));       }   +    set_cmb_tier(drvdata);

val = readl_relaxed(drvdata->base + TPDM_CMB_CR);       /*        * Set to 0 for continuous CMB collection mode, @@ -695,9 +727,17 @@ static ssize_t enable_ts_show(struct device *dev,                     char *buf)   {       struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    ssize_t size = 0;   -    return sysfs_emit(buf, "%u\n", -             (unsigned int)drvdata->dsb->patt_ts); +    if (tpdm_has_dsb_dataset(drvdata)) +        size = sysfs_emit(buf, "%u\n", +                 (unsigned int)drvdata->dsb->patt_ts);

+    if (tpdm_has_cmb_dataset(drvdata)) +        size = sysfs_emit(buf, "%u\n", +                 (unsigned int)drvdata->cmb->patt_ts);

Why does this need to show two values ? This must only show ONE value. How you deduce that might be based on the availability of the feature set. Or store the TS value in the drvdata and use that instead for controlling CMB/DSB.

Since both of CMB/DSB need to have "enable_ts" SysFs file, can I separate them

The question really is, do we need fine grained control. i.e.,

enable TS for DSB but not for CMB or vice versa.

I am not an expert on the usage scenario of the same. So, if you/Qcomm thinks the users need separate, fine grained control for timestamp for the DSB and CMB, then yes, follow your recommendation below. i.e., tpdm.../dsb_patt/enable_ts

as "enable_dsb_ts" and "enable_cmb_ts"? The path will be like below.

tpdm0/dsb_patt/enable_dsb_ts

You don't need enable_dsb_ts. It could be "enable_ts"

tpdm1/cmb_patt/enable_cmb_ts

Is this design appropriate?

Otherwise, stick to single enable_ts : which enables the ts for both CMB/DSB. And it only ever show one value : 0 (TS is disabled for both CMB/DSB) 1 : TS enabled for both.

Suzuki

...

...

Also, the sysfs documentation needs update, if this is going to control the CMB.

Sure. I will update the SysFs documentation according to the modification in the

next patch series.

Best,

Tao

...

Suzuki

...

+    return size;   }     /* @@ -715,8 +755,13 @@ static ssize_t enable_ts_store(struct device *dev,           return -EINVAL;         spin_lock(&drvdata->spinlock); -    drvdata->dsb->patt_ts = !!val; +    if (tpdm_has_dsb_dataset(drvdata)) +        drvdata->dsb->patt_ts = !!val;

+    if (tpdm_has_cmb_dataset(drvdata)) +        drvdata->cmb->patt_ts = !!val;       spin_unlock(&drvdata->spinlock);

return size;   }   static DEVICE_ATTR_RW(enable_ts); @@ -851,6 +896,68 @@ static ssize_t cmb_mode_store(struct device *dev,   }   static DEVICE_ATTR_RW(cmb_mode);   +static ssize_t cmb_ts_all_show(struct device *dev, +                   struct device_attribute *attr, +                   char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +              (unsigned int)drvdata->cmb->ts_all); +}

+static ssize_t cmb_ts_all_store(struct device *dev, +                struct device_attribute *attr, +                const char *buf, +                size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    if (val) +        drvdata->cmb->ts_all = true; +    else +        drvdata->cmb->ts_all = false; +    spin_unlock(&drvdata->spinlock); +    return size; +} +static DEVICE_ATTR_RW(cmb_ts_all);

+static ssize_t cmb_trig_ts_show(struct device *dev, +                struct device_attribute *attr, +                char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +              (unsigned int)drvdata->cmb->trig_ts); +}

+static ssize_t cmb_trig_ts_store(struct device *dev, +                 struct device_attribute *attr, +                 const char *buf, +                 size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    if (val) +        drvdata->cmb->trig_ts = true; +    else +        drvdata->cmb->trig_ts = false; +    spin_unlock(&drvdata->spinlock); +    return size; +} +static DEVICE_ATTR_RW(cmb_trig_ts);

static struct attribute *tpdm_dsb_edge_attrs[] = {       &dev_attr_ctrl_idx.attr,       &dev_attr_ctrl_val.attr, @@ -973,6 +1080,7 @@ static struct attribute *tpdm_cmb_patt_attrs[] = {       CMB_PATT_ATTR(1),       CMB_PATT_MASK_ATTR(0),       CMB_PATT_MASK_ATTR(1), +    &dev_attr_enable_ts.attr,       NULL,   };   @@ -985,6 +1093,8 @@ static struct attribute *tpdm_dsb_attrs[] = {     static struct attribute *tpdm_cmb_attrs[] = {       &dev_attr_cmb_mode.attr, +    &dev_attr_cmb_ts_all.attr, +    &dev_attr_cmb_trig_ts.attr,       NULL,   };   diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index e90d008c1cb2..65b7ca6c4077 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -11,6 +11,8 @@     /* CMB Subunit Registers */   #define TPDM_CMB_CR        (0xA00) +/*CMB subunit timestamp insertion enable register*/ +#define TPDM_CMB_TIER        (0xA04)   /*CMB subunit timestamp pattern registers*/   #define TPDM_CMB_TPR(n)        (0xA08 + (n * 4))   /*CMB subunit timestamp pattern mask registers*/ @@ -24,6 +26,12 @@   #define TPDM_CMB_CR_ENA        BIT(0)   /* Trace collection mode for CMB subunit */   #define TPDM_CMB_CR_MODE    BIT(1) +/* Timestamp control for pattern match */ +#define TPDM_CMB_TIER_PATT_TSENAB    BIT(0) +/* CMB CTI timestamp request */ +#define TPDM_CMB_TIER_XTRIG_TSENAB    BIT(1) +/* For timestamp fo all trace */ +#define TPDM_CMB_TIER_TS_ALL        BIT(2)     /*Patten register number*/   #define TPDM_CMB_MAX_PATT        2 @@ -217,6 +225,9 @@ struct dsb_dataset {    * @patt_mask:        Save value for pattern mask    * @trig_patt:        Save value for trigger pattern    * @trig_patt_mask:   Save value for trigger pattern mask

• • @patt_ts:          Indicates if pattern match for timestamp is

enabled.

• • @trig_ts:          Indicates if CTI trigger for timestamp is

enabled.

• • @ts_all:           Indicates if timestamp is enabled for all

packets.    */   struct cmb_dataset {       u32            trace_mode; @@ -224,6 +235,9 @@ struct cmb_dataset {       u32            patt_mask[TPDM_CMB_MAX_PATT];       u32            trig_patt[TPDM_CMB_MAX_PATT];       u32            trig_patt_mask[TPDM_CMB_MAX_PATT]; +    bool            patt_ts; +    bool            trig_ts; +    bool            ts_all;   };     /**

On 20/12/2023 09:51, Tao Zhang wrote:

On 12/19/2023 9:51 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 02:43, Tao Zhang wrote:

...

On 12/18/2023 6:46 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote:

...

CMB_TIER register is CMB subunit timestamp insertion enable register. Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB CTI timestamp request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp for all packets.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com

---

.../testing/sysfs-bus-coresight-devices-tpdm  |  35 ++++++   drivers/hwtracing/coresight/coresight-tpdm.c  | 116 +++++++++++++++++-   drivers/hwtracing/coresight/coresight-tpdm.h  |  14 +++   3 files changed, 162 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 53662ce7c2d0..e0b77107be13 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -214,3 +214,38 @@ KernelVersion    6.7   Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com   Description:           (RW) Set/Get the mask of the pattern for the CMB subunit TPDM.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (Write) Set the pattern timestamp of CMB tpdm. Read +        the pattern timestamp of CMB tpdm.

+        Accepts only one of the 2 values -  0 or 1. +        0 : Disable CMB pattern timestamp. +        1 : Enable CMB pattern timestamp.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the trigger timestamp of the CMB for tpdm.

+        Accepts only one of the 2 values -  0 or 1. +        0 : Set the CMB trigger type to false +        1 : Set the CMB trigger type to true

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Read or write the status of timestamp upon all interface. +        Only value 0 and 1  can be written to this node. Set this node to 1 to requeset +        timestamp to all trace packet. +        Accepts only one of the 2 values -  0 or 1. +        0 : Disable the timestamp of all trace packets. +        1 : Enable the timestamp of all trace packets. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 894d4309f1c7..f6cda5616e84 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -331,6 +331,36 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);   }   +static void set_cmb_tier(struct tpdm_drvdata *drvdata) +{ +    u32 val;

+    val = readl_relaxed(drvdata->base + TPDM_CMB_TIER);

+    /* Clear all relevant fields */ +    val &= ~(TPDM_CMB_TIER_PATT_TSENAB | TPDM_CMB_TIER_TS_ALL | +         TPDM_CMB_TIER_XTRIG_TSENAB);

+    /* Set pattern timestamp type and enablement */ +    if (drvdata->cmb->patt_ts) +        val |= TPDM_CMB_TIER_PATT_TSENAB;

-- cut --

...

+    else +        val &= ~TPDM_CMB_TIER_PATT_TSENAB;

All the else cases in this function are superfluous. Please remove all of them.

I will update this in the next patch.

...

...

+    /* Set trigger timestamp */ +    if (drvdata->cmb->trig_ts) +        val |= TPDM_CMB_TIER_XTRIG_TSENAB; +    else +        val &= ~TPDM_CMB_TIER_XTRIG_TSENAB;

+    /* Set all timestamp enablement*/ +    if (drvdata->cmb->ts_all) +        val |= TPDM_CMB_TIER_TS_ALL; +    else +        val &= ~TPDM_CMB_TIER_TS_ALL; +    writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); +}

static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)   {       u32 val, i; @@ -347,6 +377,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)                   drvdata->base + TPDM_CMB_XPMR(i));       }   +    set_cmb_tier(drvdata);

val = readl_relaxed(drvdata->base + TPDM_CMB_CR);       /*        * Set to 0 for continuous CMB collection mode, @@ -695,9 +727,17 @@ static ssize_t enable_ts_show(struct device *dev,                     char *buf)   {       struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    ssize_t size = 0;   -    return sysfs_emit(buf, "%u\n", -             (unsigned int)drvdata->dsb->patt_ts); +    if (tpdm_has_dsb_dataset(drvdata)) +        size = sysfs_emit(buf, "%u\n", +                 (unsigned int)drvdata->dsb->patt_ts);

+    if (tpdm_has_cmb_dataset(drvdata)) +        size = sysfs_emit(buf, "%u\n", +                 (unsigned int)drvdata->cmb->patt_ts);

Why does this need to show two values ? This must only show ONE value. How you deduce that might be based on the availability of the feature set. Or store the TS value in the drvdata and use that instead for controlling CMB/DSB.

Since both of CMB/DSB need to have "enable_ts" SysFs file, can I separate them

The question really is, do we need fine grained control. i.e.,

enable TS for DSB but not for CMB or vice versa.

I am not an expert on the usage scenario of the same. So, if you/Qcomm thinks the users need separate, fine grained control for timestamp for the DSB and CMB, then yes, follow your recommendation below. i.e., tpdm.../dsb_patt/enable_ts

...

as "enable_dsb_ts" and "enable_cmb_ts"? The path will be like below.

tpdm0/dsb_patt/enable_dsb_ts

You don't need enable_dsb_ts. It could be "enable_ts"

...

tpdm1/cmb_patt/enable_cmb_ts

Is this design appropriate?

Otherwise, stick to single enable_ts : which enables the ts for both CMB/DSB. And it only ever show one value : 0 (TS is disabled for both CMB/DSB) 1 : TS enabled for both.

We have a very special case, such as the TPDM supporting both CMB and

DSB datasets. Although this case is very rare, it still exists.

Can I use the data bit to instruct whether timestamp is enabled for CMB/DSB or not? For example,

size = sysfs_emit(buf, "%u\n",                 (unsigned int)(drvdata->dsb->patt_ts << 1 | drvdata->cmb->patt_ts));

Thus, this value can instruct the following situations.

0 - TS is disabled for both CMB/DSB

1 - TS is enabled for CMB

2 - TS is enabled for DSB

3 - TS is enabled for both

Is this approach acceptable?

No, please stick to separate controls for TS. Do not complicate the user interface.

i.e., tpdm0/dsb_patt/enable_ts tpdm0/cmb_patt/enable_ts

Suzuki

Best,

Tao

...

Suzuki

...

...

...

...

Also, the sysfs documentation needs update, if this is going to control the CMB.

Sure. I will update the SysFs documentation according to the modification in the

next patch series.

Best,

Tao

...

Suzuki

...

+    return size;   }     /* @@ -715,8 +755,13 @@ static ssize_t enable_ts_store(struct device *dev,           return -EINVAL;         spin_lock(&drvdata->spinlock); -    drvdata->dsb->patt_ts = !!val; +    if (tpdm_has_dsb_dataset(drvdata)) +        drvdata->dsb->patt_ts = !!val;

+    if (tpdm_has_cmb_dataset(drvdata)) +        drvdata->cmb->patt_ts = !!val;       spin_unlock(&drvdata->spinlock);

return size;   }   static DEVICE_ATTR_RW(enable_ts); @@ -851,6 +896,68 @@ static ssize_t cmb_mode_store(struct device *dev,   }   static DEVICE_ATTR_RW(cmb_mode);   +static ssize_t cmb_ts_all_show(struct device *dev, +                   struct device_attribute *attr, +                   char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +              (unsigned int)drvdata->cmb->ts_all); +}

+static ssize_t cmb_ts_all_store(struct device *dev, +                struct device_attribute *attr, +                const char *buf, +                size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    if (val) +        drvdata->cmb->ts_all = true; +    else +        drvdata->cmb->ts_all = false; +    spin_unlock(&drvdata->spinlock); +    return size; +} +static DEVICE_ATTR_RW(cmb_ts_all);

+static ssize_t cmb_trig_ts_show(struct device *dev, +                struct device_attribute *attr, +                char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +              (unsigned int)drvdata->cmb->trig_ts); +}

+static ssize_t cmb_trig_ts_store(struct device *dev, +                 struct device_attribute *attr, +                 const char *buf, +                 size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    if (val) +        drvdata->cmb->trig_ts = true; +    else +        drvdata->cmb->trig_ts = false; +    spin_unlock(&drvdata->spinlock); +    return size; +} +static DEVICE_ATTR_RW(cmb_trig_ts);

static struct attribute *tpdm_dsb_edge_attrs[] = {       &dev_attr_ctrl_idx.attr,       &dev_attr_ctrl_val.attr, @@ -973,6 +1080,7 @@ static struct attribute *tpdm_cmb_patt_attrs[] = {       CMB_PATT_ATTR(1),       CMB_PATT_MASK_ATTR(0),       CMB_PATT_MASK_ATTR(1), +    &dev_attr_enable_ts.attr,       NULL,   };   @@ -985,6 +1093,8 @@ static struct attribute *tpdm_dsb_attrs[] = {     static struct attribute *tpdm_cmb_attrs[] = {       &dev_attr_cmb_mode.attr, +    &dev_attr_cmb_ts_all.attr, +    &dev_attr_cmb_trig_ts.attr,       NULL,   };   diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index e90d008c1cb2..65b7ca6c4077 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -11,6 +11,8 @@     /* CMB Subunit Registers */   #define TPDM_CMB_CR        (0xA00) +/*CMB subunit timestamp insertion enable register*/ +#define TPDM_CMB_TIER        (0xA04)   /*CMB subunit timestamp pattern registers*/   #define TPDM_CMB_TPR(n)        (0xA08 + (n * 4))   /*CMB subunit timestamp pattern mask registers*/ @@ -24,6 +26,12 @@   #define TPDM_CMB_CR_ENA        BIT(0)   /* Trace collection mode for CMB subunit */   #define TPDM_CMB_CR_MODE    BIT(1) +/* Timestamp control for pattern match */ +#define TPDM_CMB_TIER_PATT_TSENAB    BIT(0) +/* CMB CTI timestamp request */ +#define TPDM_CMB_TIER_XTRIG_TSENAB    BIT(1) +/* For timestamp fo all trace */ +#define TPDM_CMB_TIER_TS_ALL        BIT(2)     /*Patten register number*/   #define TPDM_CMB_MAX_PATT        2 @@ -217,6 +225,9 @@ struct dsb_dataset {    * @patt_mask:        Save value for pattern mask    * @trig_patt:        Save value for trigger pattern    * @trig_patt_mask:   Save value for trigger pattern mask

• • @patt_ts:          Indicates if pattern match for timestamp is

enabled.

• • @trig_ts:          Indicates if CTI trigger for timestamp is

enabled.

• • @ts_all:           Indicates if timestamp is enabled for all

packets.    */   struct cmb_dataset {       u32            trace_mode; @@ -224,6 +235,9 @@ struct cmb_dataset {       u32            patt_mask[TPDM_CMB_MAX_PATT];       u32            trig_patt[TPDM_CMB_MAX_PATT];       u32            trig_patt_mask[TPDM_CMB_MAX_PATT]; +    bool            patt_ts; +    bool            trig_ts; +    bool            ts_all;   };     /**

---

CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org

On 25/12/2023 01:55, Tao Zhang wrote:

On 12/20/2023 7:07 PM, Suzuki K Poulose wrote:

...

On 20/12/2023 09:51, Tao Zhang wrote:

...

On 12/19/2023 9:51 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 02:43, Tao Zhang wrote:

...

On 12/18/2023 6:46 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote: > CMB_TIER register is CMB subunit timestamp insertion enable > register. > Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp > following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit. > Set this bit to 1 to request a timestamp following a CMB CTI > timestamp > request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp > for all packets. > > Reviewed-by: James Clark james.clark@arm.com > Signed-off-by: Tao Zhang quic_taozha@quicinc.com > Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com > --- >   .../testing/sysfs-bus-coresight-devices-tpdm  |  35 ++++++ >   drivers/hwtracing/coresight/coresight-tpdm.c  | 116 > +++++++++++++++++- >   drivers/hwtracing/coresight/coresight-tpdm.h  |  14 +++ >   3 files changed, 162 insertions(+), 3 deletions(-) > > diff --git > a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index 53662ce7c2d0..e0b77107be13 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -214,3 +214,38 @@ KernelVersion    6.7 >   Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao > Zhang (QUIC) quic_taozha@quicinc.com >   Description: >           (RW) Set/Get the mask of the pattern for the CMB > subunit TPDM. > + > +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts > +Date:        September 2023 > +KernelVersion    6.7 > +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao > Zhang (QUIC) quic_taozha@quicinc.com > +Description: > +        (Write) Set the pattern timestamp of CMB tpdm. Read > +        the pattern timestamp of CMB tpdm. > + > +        Accepts only one of the 2 values -  0 or 1. > +        0 : Disable CMB pattern timestamp. > +        1 : Enable CMB pattern timestamp. > + > +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts > +Date:        September 2023 > +KernelVersion    6.7 > +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao > Zhang (QUIC) quic_taozha@quicinc.com > +Description: > +        (RW) Set/Get the trigger timestamp of the CMB for tpdm. > + > +        Accepts only one of the 2 values -  0 or 1. > +        0 : Set the CMB trigger type to false > +        1 : Set the CMB trigger type to true > + > +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all > +Date:        September 2023 > +KernelVersion    6.7 > +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao > Zhang (QUIC) quic_taozha@quicinc.com > +Description: > +        (RW) Read or write the status of timestamp upon all > interface. > +        Only value 0 and 1  can be written to this node. Set > this node to 1 to requeset > +        timestamp to all trace packet. > +        Accepts only one of the 2 values -  0 or 1. > +        0 : Disable the timestamp of all trace packets. > +        1 : Enable the timestamp of all trace packets. > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c > b/drivers/hwtracing/coresight/coresight-tpdm.c > index 894d4309f1c7..f6cda5616e84 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -331,6 +331,36 @@ static void tpdm_enable_dsb(struct > tpdm_drvdata *drvdata) >       writel_relaxed(val, drvdata->base + TPDM_DSB_CR); >   } >   +static void set_cmb_tier(struct tpdm_drvdata *drvdata) > +{ > +    u32 val; > + > +    val = readl_relaxed(drvdata->base + TPDM_CMB_TIER); > + > +    /* Clear all relevant fields */ > +    val &= ~(TPDM_CMB_TIER_PATT_TSENAB | TPDM_CMB_TIER_TS_ALL | > +         TPDM_CMB_TIER_XTRIG_TSENAB); > + > +    /* Set pattern timestamp type and enablement */ > +    if (drvdata->cmb->patt_ts) > +        val |= TPDM_CMB_TIER_PATT_TSENAB;

-- cut -- > +    else > +        val &= ~TPDM_CMB_TIER_PATT_TSENAB;

All the else cases in this function are superfluous. Please remove all of them.

I will update this in the next patch.

...

> + > +    /* Set trigger timestamp */ > +    if (drvdata->cmb->trig_ts) > +        val |= TPDM_CMB_TIER_XTRIG_TSENAB; > +    else > +        val &= ~TPDM_CMB_TIER_XTRIG_TSENAB; > + > +    /* Set all timestamp enablement*/ > +    if (drvdata->cmb->ts_all) > +        val |= TPDM_CMB_TIER_TS_ALL; > +    else > +        val &= ~TPDM_CMB_TIER_TS_ALL; > +    writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); > +} > + >   static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) >   { >       u32 val, i; > @@ -347,6 +377,8 @@ static void tpdm_enable_cmb(struct > tpdm_drvdata *drvdata) >                   drvdata->base + TPDM_CMB_XPMR(i)); >       } >   +    set_cmb_tier(drvdata); > + >       val = readl_relaxed(drvdata->base + TPDM_CMB_CR); >       /* >        * Set to 0 for continuous CMB collection mode, > @@ -695,9 +727,17 @@ static ssize_t enable_ts_show(struct device > *dev, >                     char *buf) >   { >       struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > +    ssize_t size = 0; >   -    return sysfs_emit(buf, "%u\n", > -             (unsigned int)drvdata->dsb->patt_ts); > +    if (tpdm_has_dsb_dataset(drvdata)) > +        size = sysfs_emit(buf, "%u\n", > +                 (unsigned int)drvdata->dsb->patt_ts); > + > +    if (tpdm_has_cmb_dataset(drvdata)) > +        size = sysfs_emit(buf, "%u\n", > +                 (unsigned int)drvdata->cmb->patt_ts);

Why does this need to show two values ? This must only show ONE value. How you deduce that might be based on the availability of the feature set. Or store the TS value in the drvdata and use that instead for controlling CMB/DSB.

Since both of CMB/DSB need to have "enable_ts" SysFs file, can I separate them

The question really is, do we need fine grained control. i.e.,

enable TS for DSB but not for CMB or vice versa.

I am not an expert on the usage scenario of the same. So, if you/Qcomm thinks the users need separate, fine grained control for timestamp for the DSB and CMB, then yes, follow your recommendation below. i.e., tpdm.../dsb_patt/enable_ts

...

as "enable_dsb_ts" and "enable_cmb_ts"? The path will be like below.

tpdm0/dsb_patt/enable_dsb_ts

You don't need enable_dsb_ts. It could be "enable_ts"

...

tpdm1/cmb_patt/enable_cmb_ts

Is this design appropriate?

Otherwise, stick to single enable_ts : which enables the ts for both CMB/DSB. And it only ever show one value : 0 (TS is disabled for both CMB/DSB) 1 : TS enabled for both.

We have a very special case, such as the TPDM supporting both CMB and

DSB datasets. Although this case is very rare, it still exists.

Can I use the data bit to instruct whether timestamp is enabled for CMB/DSB or not? For example,

size = sysfs_emit(buf, "%u\n",                  (unsigned int)(drvdata->dsb->patt_ts << 1 | drvdata->cmb->patt_ts));

Thus, this value can instruct the following situations.

0 - TS is disabled for both CMB/DSB

1 - TS is enabled for CMB

2 - TS is enabled for DSB

3 - TS is enabled for both

Is this approach acceptable?

No, please stick to separate controls for TS. Do not complicate the user interface.

i.e., tpdm0/dsb_patt/enable_ts tpdm0/cmb_patt/enable_ts

We need to be able to control/show dsb and cmb timestamp enablement independently.

Can we achieve this requirement if we use a sysfs file with the same name?

They are independent and in their respective directory (group) for CMB and DSB. What am I missing ? e.g., if you want to enable TS for DSB, you do :

$ echo 1 > dsb_patt/enable_ts

And that only works for DSB not for CMB.

Suzuki

I'm not able to find a good way to achieve it. Do you have any suggestions for this?

Best,

Tao

...

Suzuki

...

Best,

Tao

...

Suzuki

...

...

...

...

Also, the sysfs documentation needs update, if this is going to control the CMB.

Sure. I will update the SysFs documentation according to the modification in the

next patch series.

Best,

Tao

...

Suzuki

> + > +    return size; >   } >     /* > @@ -715,8 +755,13 @@ static ssize_t enable_ts_store(struct device > *dev, >           return -EINVAL; >         spin_lock(&drvdata->spinlock); > -    drvdata->dsb->patt_ts = !!val; > +    if (tpdm_has_dsb_dataset(drvdata)) > +        drvdata->dsb->patt_ts = !!val; > + > +    if (tpdm_has_cmb_dataset(drvdata)) > +        drvdata->cmb->patt_ts = !!val; >       spin_unlock(&drvdata->spinlock); > + >       return size; >   } >   static DEVICE_ATTR_RW(enable_ts); > @@ -851,6 +896,68 @@ static ssize_t cmb_mode_store(struct device > *dev, >   } >   static DEVICE_ATTR_RW(cmb_mode); >   +static ssize_t cmb_ts_all_show(struct device *dev, > +                   struct device_attribute *attr, > +                   char *buf) > +{ > +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > +    return sysfs_emit(buf, "%u\n", > +              (unsigned int)drvdata->cmb->ts_all); > +} > + > +static ssize_t cmb_ts_all_store(struct device *dev, > +                struct device_attribute *attr, > +                const char *buf, > +                size_t size) > +{ > +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > +    unsigned long val; > + > +    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) > +        return -EINVAL; > + > +    spin_lock(&drvdata->spinlock); > +    if (val) > +        drvdata->cmb->ts_all = true; > +    else > +        drvdata->cmb->ts_all = false; > +    spin_unlock(&drvdata->spinlock); > +    return size; > +} > +static DEVICE_ATTR_RW(cmb_ts_all); > + > +static ssize_t cmb_trig_ts_show(struct device *dev, > +                struct device_attribute *attr, > +                char *buf) > +{ > +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > +    return sysfs_emit(buf, "%u\n", > +              (unsigned int)drvdata->cmb->trig_ts); > +} > + > +static ssize_t cmb_trig_ts_store(struct device *dev, > +                 struct device_attribute *attr, > +                 const char *buf, > +                 size_t size) > +{ > +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > +    unsigned long val; > + > +    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) > +        return -EINVAL; > + > +    spin_lock(&drvdata->spinlock); > +    if (val) > +        drvdata->cmb->trig_ts = true; > +    else > +        drvdata->cmb->trig_ts = false; > +    spin_unlock(&drvdata->spinlock); > +    return size; > +} > +static DEVICE_ATTR_RW(cmb_trig_ts); > + >   static struct attribute *tpdm_dsb_edge_attrs[] = { >       &dev_attr_ctrl_idx.attr, >       &dev_attr_ctrl_val.attr, > @@ -973,6 +1080,7 @@ static struct attribute > *tpdm_cmb_patt_attrs[] = { >       CMB_PATT_ATTR(1), >       CMB_PATT_MASK_ATTR(0), >       CMB_PATT_MASK_ATTR(1), > +    &dev_attr_enable_ts.attr, >       NULL, >   }; >   @@ -985,6 +1093,8 @@ static struct attribute *tpdm_dsb_attrs[] = { >     static struct attribute *tpdm_cmb_attrs[] = { >       &dev_attr_cmb_mode.attr, > +    &dev_attr_cmb_ts_all.attr, > +    &dev_attr_cmb_trig_ts.attr, >       NULL, >   }; >   diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h > b/drivers/hwtracing/coresight/coresight-tpdm.h > index e90d008c1cb2..65b7ca6c4077 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -11,6 +11,8 @@ >     /* CMB Subunit Registers */ >   #define TPDM_CMB_CR        (0xA00) > +/*CMB subunit timestamp insertion enable register*/ > +#define TPDM_CMB_TIER        (0xA04) >   /*CMB subunit timestamp pattern registers*/ >   #define TPDM_CMB_TPR(n)        (0xA08 + (n * 4)) >   /*CMB subunit timestamp pattern mask registers*/ > @@ -24,6 +26,12 @@ >   #define TPDM_CMB_CR_ENA        BIT(0) >   /* Trace collection mode for CMB subunit */ >   #define TPDM_CMB_CR_MODE    BIT(1) > +/* Timestamp control for pattern match */ > +#define TPDM_CMB_TIER_PATT_TSENAB    BIT(0) > +/* CMB CTI timestamp request */ > +#define TPDM_CMB_TIER_XTRIG_TSENAB    BIT(1) > +/* For timestamp fo all trace */ > +#define TPDM_CMB_TIER_TS_ALL        BIT(2) >     /*Patten register number*/ >   #define TPDM_CMB_MAX_PATT        2 > @@ -217,6 +225,9 @@ struct dsb_dataset { >    * @patt_mask:        Save value for pattern mask >    * @trig_patt:        Save value for trigger pattern >    * @trig_patt_mask:   Save value for trigger pattern mask > + * @patt_ts:          Indicates if pattern match for timestamp > is enabled. > + * @trig_ts:          Indicates if CTI trigger for timestamp is > enabled. > + * @ts_all:           Indicates if timestamp is enabled for all > packets. >    */ >   struct cmb_dataset { >       u32            trace_mode; > @@ -224,6 +235,9 @@ struct cmb_dataset { >       u32            patt_mask[TPDM_CMB_MAX_PATT]; >       u32            trig_patt[TPDM_CMB_MAX_PATT]; >       u32            trig_patt_mask[TPDM_CMB_MAX_PATT]; > +    bool            patt_ts; > +    bool            trig_ts; > +    bool            ts_all; >   }; >     /**

---

CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org

---

CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org

On 05/01/2024 07:49, Tao Zhang wrote:

On 12/30/2023 5:39 PM, Suzuki K Poulose wrote:

...

On 25/12/2023 01:55, Tao Zhang wrote:

...

On 12/20/2023 7:07 PM, Suzuki K Poulose wrote:

...

On 20/12/2023 09:51, Tao Zhang wrote:

...

On 12/19/2023 9:51 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 02:43, Tao Zhang wrote: > > On 12/18/2023 6:46 PM, Suzuki K Poulose wrote: >> On 21/11/2023 02:24, Tao Zhang wrote: >>> CMB_TIER register is CMB subunit timestamp insertion enable >>> register. >>> Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp >>> following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB >>> bit. >>> Set this bit to 1 to request a timestamp following a CMB CTI >>> timestamp >>> request. Bit 2 is TS_ALL bit. Set this bit to 1 to request >>> timestamp >>> for all packets. >>> >>> Reviewed-by: James Clark james.clark@arm.com >>> Signed-off-by: Tao Zhang quic_taozha@quicinc.com >>> Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com >>> --- >>>   .../testing/sysfs-bus-coresight-devices-tpdm  | 35 ++++++ >>>   drivers/hwtracing/coresight/coresight-tpdm.c  | 116 >>> +++++++++++++++++- >>>   drivers/hwtracing/coresight/coresight-tpdm.h  | 14 +++ >>>   3 files changed, 162 insertions(+), 3 deletions(-) >>> >>> diff --git >>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> index 53662ce7c2d0..e0b77107be13 100644 >>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> @@ -214,3 +214,38 @@ KernelVersion    6.7 >>>   Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, >>> Tao Zhang (QUIC) quic_taozha@quicinc.com >>>   Description: >>>           (RW) Set/Get the mask of the pattern for the CMB >>> subunit TPDM. >>> + >>> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts >>> +Date:        September 2023 >>> +KernelVersion    6.7 >>> +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao >>> Zhang (QUIC) quic_taozha@quicinc.com >>> +Description: >>> +        (Write) Set the pattern timestamp of CMB tpdm. Read >>> +        the pattern timestamp of CMB tpdm. >>> + >>> +        Accepts only one of the 2 values -  0 or 1. >>> +        0 : Disable CMB pattern timestamp. >>> +        1 : Enable CMB pattern timestamp. >>> + >>> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts >>> +Date:        September 2023 >>> +KernelVersion    6.7 >>> +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao >>> Zhang (QUIC) quic_taozha@quicinc.com >>> +Description: >>> +        (RW) Set/Get the trigger timestamp of the CMB for tpdm. >>> + >>> +        Accepts only one of the 2 values -  0 or 1. >>> +        0 : Set the CMB trigger type to false >>> +        1 : Set the CMB trigger type to true >>> + >>> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all >>> +Date:        September 2023 >>> +KernelVersion    6.7 >>> +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao >>> Zhang (QUIC) quic_taozha@quicinc.com >>> +Description: >>> +        (RW) Read or write the status of timestamp upon all >>> interface. >>> +        Only value 0 and 1  can be written to this node. Set >>> this node to 1 to requeset >>> +        timestamp to all trace packet. >>> +        Accepts only one of the 2 values -  0 or 1. >>> +        0 : Disable the timestamp of all trace packets. >>> +        1 : Enable the timestamp of all trace packets. >>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c >>> b/drivers/hwtracing/coresight/coresight-tpdm.c >>> index 894d4309f1c7..f6cda5616e84 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >>> @@ -331,6 +331,36 @@ static void tpdm_enable_dsb(struct >>> tpdm_drvdata *drvdata) >>>       writel_relaxed(val, drvdata->base + TPDM_DSB_CR); >>>   } >>>   +static void set_cmb_tier(struct tpdm_drvdata *drvdata) >>> +{ >>> +    u32 val; >>> + >>> +    val = readl_relaxed(drvdata->base + TPDM_CMB_TIER); >>> + >>> +    /* Clear all relevant fields */ >>> +    val &= ~(TPDM_CMB_TIER_PATT_TSENAB | TPDM_CMB_TIER_TS_ALL | >>> +         TPDM_CMB_TIER_XTRIG_TSENAB); >>> + >>> +    /* Set pattern timestamp type and enablement */ >>> +    if (drvdata->cmb->patt_ts) >>> +        val |= TPDM_CMB_TIER_PATT_TSENAB; >> >>  -- cut -- >>> +    else >>> +        val &= ~TPDM_CMB_TIER_PATT_TSENAB; >> >> >> All the else cases in this function are superfluous. Please >> remove all >> of them. > I will update this in the next patch. >> >>> + >>> +    /* Set trigger timestamp */ >>> +    if (drvdata->cmb->trig_ts) >>> +        val |= TPDM_CMB_TIER_XTRIG_TSENAB; >>> +    else >>> +        val &= ~TPDM_CMB_TIER_XTRIG_TSENAB; >>> + >>> +    /* Set all timestamp enablement*/ >>> +    if (drvdata->cmb->ts_all) >>> +        val |= TPDM_CMB_TIER_TS_ALL; >>> +    else >>> +        val &= ~TPDM_CMB_TIER_TS_ALL; >>> +    writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); >>> +} >>> + >>>   static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) >>>   { >>>       u32 val, i; >>> @@ -347,6 +377,8 @@ static void tpdm_enable_cmb(struct >>> tpdm_drvdata *drvdata) >>>                   drvdata->base + TPDM_CMB_XPMR(i)); >>>       } >>>   +    set_cmb_tier(drvdata); >>> + >>>       val = readl_relaxed(drvdata->base + TPDM_CMB_CR); >>>       /* >>>        * Set to 0 for continuous CMB collection mode, >>> @@ -695,9 +727,17 @@ static ssize_t enable_ts_show(struct >>> device *dev, >>>                     char *buf) >>>   { >>>       struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> +    ssize_t size = 0; >>>   -    return sysfs_emit(buf, "%u\n", >>> -             (unsigned int)drvdata->dsb->patt_ts); >>> +    if (tpdm_has_dsb_dataset(drvdata)) >>> +        size = sysfs_emit(buf, "%u\n", >>> +                 (unsigned int)drvdata->dsb->patt_ts); >>> + >>> +    if (tpdm_has_cmb_dataset(drvdata)) >>> +        size = sysfs_emit(buf, "%u\n", >>> +                 (unsigned int)drvdata->cmb->patt_ts); >> >> Why does this need to show two values ? This must only show ONE >> value. >> How you deduce that might be based on the availability of the >> feature >> set. Or store the TS value in the drvdata and use that instead for >> controlling CMB/DSB. > > Since both of CMB/DSB need to have "enable_ts" SysFs file, can I > separate them

The question really is, do we need fine grained control. i.e.,

enable TS for DSB but not for CMB or vice versa.

I am not an expert on the usage scenario of the same. So, if you/Qcomm thinks the users need separate, fine grained control for timestamp for the DSB and CMB, then yes, follow your recommendation below. i.e., tpdm.../dsb_patt/enable_ts

> as "enable_dsb_ts" and "enable_cmb_ts"? The path will be like below. > > tpdm0/dsb_patt/enable_dsb_ts

You don't need enable_dsb_ts. It could be "enable_ts"

> > tpdm1/cmb_patt/enable_cmb_ts > > Is this design appropriate?

Otherwise, stick to single enable_ts : which enables the ts for both CMB/DSB. And it only ever show one value : 0 (TS is disabled for both CMB/DSB) 1 : TS enabled for both.

We have a very special case, such as the TPDM supporting both CMB and

DSB datasets. Although this case is very rare, it still exists.

Can I use the data bit to instruct whether timestamp is enabled for CMB/DSB or not? For example,

size = sysfs_emit(buf, "%u\n",                  (unsigned int)(drvdata->dsb->patt_ts << 1 | drvdata->cmb->patt_ts));

Thus, this value can instruct the following situations.

0 - TS is disabled for both CMB/DSB

1 - TS is enabled for CMB

2 - TS is enabled for DSB

3 - TS is enabled for both

Is this approach acceptable?

No, please stick to separate controls for TS. Do not complicate the user interface.

i.e., tpdm0/dsb_patt/enable_ts tpdm0/cmb_patt/enable_ts

We need to be able to control/show dsb and cmb timestamp enablement independently.

Can we achieve this requirement if we use a sysfs file with the same name?

They are independent and in their respective directory (group) for CMB and DSB. What am I missing ? e.g., if you want to enable TS for DSB, you do :

$ echo 1 > dsb_patt/enable_ts

And that only works for DSB not for CMB.

We have a special case that the TPDM supports both DSB and CMB dataset. In this special case, when we

issue this command to enable timestamp, it will call enable_ts_store API, right?

if (tpdm_has_dsb_dataset(drvdata))         drvdata->dsb->patt_ts = !!val;

if (tpdm_has_cmb_dataset(drvdata))         drvdata->cmb->patt_ts = !!val;

I don't understand. If they both are under different subgroups, why should they be conflicting ? Are you not able to distinguish them, when you creat those attributes ? i.e., create two different "attributes" ?

See below.

Since this special TPDM supports both DSB and CMB dataset, both DSB patt_ts and CMB patt_ts will be set

in this case even if I only configure the file in the DSB directory, right?

This is the problem we have now.

...

...

...

...

...

>> >> >>> + >>> +    return size; >>>   } >>>     /* >>> @@ -715,8 +755,13 @@ static ssize_t enable_ts_store(struct >>> device *dev, >>>           return -EINVAL; >>>         spin_lock(&drvdata->spinlock); >>> -    drvdata->dsb->patt_ts = !!val; >>> +    if (tpdm_has_dsb_dataset(drvdata)) >>> +        drvdata->dsb->patt_ts = !!val; >>> + >>> +    if (tpdm_has_cmb_dataset(drvdata)) >>> +        drvdata->cmb->patt_ts = !!val; >>>       spin_unlock(&drvdata->spinlock); >>> + >>>       return size; >>>   } >>>   static DEVICE_ATTR_RW(enable_ts);

Do not overload the same for both DSB and CMB. Create one for each in DSB and CMB ? They could share the same show/store routines, but could be done with additional variable to indicate which attribute they are controlling. Like the other attributes, using dev_ext_attribute or such.

Suzuki

On 12/01/2024 02:42, Tao Zhang wrote:

On 1/8/2024 6:42 PM, Suzuki K Poulose wrote:

...

On 05/01/2024 07:49, Tao Zhang wrote:

...

On 12/30/2023 5:39 PM, Suzuki K Poulose wrote:

...

On 25/12/2023 01:55, Tao Zhang wrote:

...

On 12/20/2023 7:07 PM, Suzuki K Poulose wrote:

...

On 20/12/2023 09:51, Tao Zhang wrote: > > On 12/19/2023 9:51 PM, Suzuki K Poulose wrote: >> On 19/12/2023 02:43, Tao Zhang wrote: >>> >>> On 12/18/2023 6:46 PM, Suzuki K Poulose wrote: >>>> On 21/11/2023 02:24, Tao Zhang wrote:

...

...

...

...

...

...

>>>>>                     char *buf) >>>>>   { >>>>>       struct tpdm_drvdata *drvdata = >>>>> dev_get_drvdata(dev->parent); >>>>> +    ssize_t size = 0; >>>>>   -    return sysfs_emit(buf, "%u\n", >>>>> -             (unsigned int)drvdata->dsb->patt_ts); >>>>> +    if (tpdm_has_dsb_dataset(drvdata)) >>>>> +        size = sysfs_emit(buf, "%u\n", >>>>> +                 (unsigned int)drvdata->dsb->patt_ts); >>>>> + >>>>> +    if (tpdm_has_cmb_dataset(drvdata)) >>>>> +        size = sysfs_emit(buf, "%u\n", >>>>> +                 (unsigned int)drvdata->cmb->patt_ts); >>>> >>>> Why does this need to show two values ? This must only show >>>> ONE value. >>>> How you deduce that might be based on the availability of the >>>> feature >>>> set. Or store the TS value in the drvdata and use that instead >>>> for >>>> controlling CMB/DSB. >>> >>> Since both of CMB/DSB need to have "enable_ts" SysFs file, can >>> I separate them >> >> The question really is, do we need fine grained control. i.e., >> >> enable TS for DSB but not for CMB or vice versa. >> >> I am not an expert on the usage scenario of the same. So, if >> you/Qcomm >> thinks the users need separate, fine grained control for timestamp >> for the DSB and CMB, then yes, follow your recommendation below. >> i.e., tpdm.../dsb_patt/enable_ts >> >>> as "enable_dsb_ts" and "enable_cmb_ts"? The path will be like >>> below. >>> >>> tpdm0/dsb_patt/enable_dsb_ts >> >> You don't need enable_dsb_ts. It could be "enable_ts" >> >>> >>> tpdm1/cmb_patt/enable_cmb_ts >>> >>> Is this design appropriate? >> >> >> Otherwise, stick to single enable_ts : which enables the ts for >> both >> CMB/DSB. And it only ever show one value : 0 (TS is disabled for >> both >> CMB/DSB) 1 : TS enabled for both. > > We have a very special case, such as the TPDM supporting both CMB > and > > DSB datasets. Although this case is very rare, it still exists. > > Can I use the data bit to instruct whether timestamp is enabled > for CMB/DSB or not? For example, > > size = sysfs_emit(buf, "%u\n", >                  (unsigned int)(drvdata->dsb->patt_ts << 1 | > drvdata->cmb->patt_ts)); > > Thus, this value can instruct the following situations. > > 0 - TS is disabled for both CMB/DSB > > 1 - TS is enabled for CMB > > 2 - TS is enabled for DSB > > 3 - TS is enabled for both > > Is this approach acceptable? >

No, please stick to separate controls for TS. Do not complicate the user interface.

i.e., tpdm0/dsb_patt/enable_ts tpdm0/cmb_patt/enable_ts

We need to be able to control/show dsb and cmb timestamp enablement independently.

Can we achieve this requirement if we use a sysfs file with the same name?

They are independent and in their respective directory (group) for CMB and DSB. What am I missing ? e.g., if you want to enable TS for DSB, you do :

$ echo 1 > dsb_patt/enable_ts

And that only works for DSB not for CMB.

We have a special case that the TPDM supports both DSB and CMB dataset. In this special case, when we

issue this command to enable timestamp, it will call enable_ts_store API, right?

if (tpdm_has_dsb_dataset(drvdata))          drvdata->dsb->patt_ts = !!val;

if (tpdm_has_cmb_dataset(drvdata))          drvdata->cmb->patt_ts = !!val;

I don't understand. If they both are under different subgroups, why should they be conflicting ? Are you not able to distinguish them, when  you creat those attributes ? i.e., create two different "attributes" ?

Yes, although some TPDMs can support both CMB dataset and DSB dataset, we need to configure them separately

in some scenarios. Based on your suggestion, I want to use the following approach to implement it.

See below.

...

See below.

...

Since this special TPDM supports both DSB and CMB dataset, both DSB patt_ts and CMB patt_ts will be set

in this case even if I only configure the file in the DSB directory, right?

This is the problem we have now.

...

...

...

...

>>>> >>>> >>>>> + >>>>> +    return size; >>>>>   } >>>>>     /* >>>>> @@ -715,8 +755,13 @@ static ssize_t enable_ts_store(struct >>>>> device *dev, >>>>>           return -EINVAL; >>>>>         spin_lock(&drvdata->spinlock); >>>>> -    drvdata->dsb->patt_ts = !!val; >>>>> +    if (tpdm_has_dsb_dataset(drvdata)) >>>>> +        drvdata->dsb->patt_ts = !!val; >>>>> + >>>>> +    if (tpdm_has_cmb_dataset(drvdata)) >>>>> +        drvdata->cmb->patt_ts = !!val; >>>>>       spin_unlock(&drvdata->spinlock); >>>>> + >>>>>       return size; >>>>>   } >>>>>   static DEVICE_ATTR_RW(enable_ts);

Do not overload the same for both DSB and CMB. Create one for each in DSB and CMB ? They could share the same show/store routines, but could be done with additional variable to indicate which attribute they are controlling. Like the other attributes, using dev_ext_attribute or such.

New approach below, please help review to see if it is acceptable?

#define tpdm_patt_enable_ts_rw(name, mem)                \     (&((struct tpdm_dataset_attribute[]) {            \        {                                \         __ATTR(name, 0644, enable_ts_show,        \         enable_ts_store),        \         mem,                            \        }                                \     })[0].attr.attr)

#define DSB_PATT_ENABLE_TS                    \         tpdm_patt_enable_ts_rw(enable_ts,        \         DSB_PATT)

#define CMB_PATT_ENABLE_TS                    \         tpdm_patt_enable_ts_rw(enable_ts,        \         CMB_PATT)

static ssize_t enable_ts_show(struct device *dev,                   struct device_attribute *attr,                   char *buf) {     struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);     struct tpdm_dataset_attribute *tpdm_attr =         container_of(attr, struct tpdm_dataset_attribute, attr);     ssize_t size = 0;

if (tpdm_attr->mem == DSB_PATT) {         size = sysfs_emit(buf, "%u\n",                  (unsigned int)drvdata->dsb->patt_ts);     } else if (tpdm_attr->mem == CMB_PATT) {         size = sysfs_emit(buf, "%u\n",                 (unsigned int)drvdata->cmb->patt_ts);     } else         return -EINVAL;

return size; }

static ssize_t enable_ts_store(struct device *dev,                    struct device_attribute *attr,                    const char *buf,                    size_t size) {     struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);     struct tpdm_dataset_attribute *tpdm_attr =         container_of(attr, struct tpdm_dataset_attribute, attr);     unsigned long val;

if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))         return -EINVAL;

spin_lock(&drvdata->spinlock);     if (tpdm_attr->mem == DSB_PATT) {         drvdata->dsb->patt_ts = !!val;     } else if (tpdm_attr->mem == CMB_PATT) {         drvdata->cmb->patt_ts = !!val;     } else         return -EINVAL;     spin_unlock(&drvdata->spinlock);

return size; }

Yes, that is what I had in mind.

Thanks Suzuki

Best,

Tao

...

Suzuki

On 21/11/2023 02:24, Tao Zhang wrote:

Add the nodes for CMB subunit MSR(mux select register) support. CMB MSRs(mux select registers) is to separate mux,arbitration, ,interleaving,data packing control from stream filtering control.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

.../testing/sysfs-bus-coresight-devices-tpdm | 8 ++ drivers/hwtracing/coresight/coresight-tpdm.c | 86 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 16 +++- 3 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e0b77107be13..914f3fd81525 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -249,3 +249,11 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Disable the timestamp of all trace packets. 1 : Enable the timestamp of all trace packets.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] +Date: September 2023 +KernelVersion 6.7 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the MSR(mux select register) for the CMB subunit
  

• TPDM.
  

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f6cda5616e84..7e331ea436cc 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -86,6 +86,11 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev, return -EINVAL; return sysfs_emit(buf, "0x%x\n", drvdata->cmb->patt_mask[tpdm_attr->idx]);

• case CMB_MSR:

• if (tpdm_attr->idx >= drvdata->cmb_msr_num)
  

• 	return -EINVAL;
  

• return sysfs_emit(buf, "0x%x\n",
  

• 		drvdata->cmb->msr[tpdm_attr->idx]);
  

  } return -EINVAL; }

@@ -162,6 +167,12 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, else ret = -EINVAL; break;

• case CMB_MSR:

• if (tpdm_attr->idx < drvdata->cmb_msr_num)
  

• 	drvdata->cmb->msr[tpdm_attr->idx] = val;
  

• else
  

• 	ret = -EINVAL;
  

minor nit: Could we not break from here instead of adding return -EINVAL for each case ? (I understand it has been done for the existing cases. But I think we should clean up all of that, including the ones you added in Patch 5. Similarly for the dataset_show()

Suzuki

• break;
  

  default: ret = -EINVAL; }

@@ -220,6 +231,23 @@ static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj, return 0; } +static umode_t tpdm_cmb_msr_is_visible(struct kobject *kobj,

• 		       struct attribute *attr, int n)
  

+{

• struct device *dev = kobj_to_dev(kobj);
• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct device_attribute *dev_attr =

• container_of(attr, struct device_attribute, attr);
  

• struct tpdm_dataset_attribute *tpdm_attr =

• container_of(dev_attr, struct tpdm_dataset_attribute, attr);
  

• if (tpdm_attr->idx < drvdata->cmb_msr_num)

• return attr->mode;
  

• return 0;

+}

• static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) {

@@ -361,6 +389,15 @@ static void set_cmb_tier(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_CMB_TIER); } +static void set_cmb_msr(struct tpdm_drvdata *drvdata) +{

• int i;
• for (i = 0; i < drvdata->cmb_msr_num; i++)

• writel_relaxed(drvdata->cmb->msr[i],
  

• 	   drvdata->base + TPDM_CMB_MSR(i));
  

+}

• static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) { u32 val, i;

@@ -379,6 +416,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) set_cmb_tier(drvdata);

• set_cmb_msr(drvdata);
• val = readl_relaxed(drvdata->base + TPDM_CMB_CR); /*
  • Set to 0 for continuous CMB collection mode,

@@ -1084,6 +1123,42 @@ static struct attribute *tpdm_cmb_patt_attrs[] = { NULL, }; +static struct attribute *tpdm_cmb_msr_attrs[] = {

• CMB_MSR_ATTR(0),
• CMB_MSR_ATTR(1),
• CMB_MSR_ATTR(2),
• CMB_MSR_ATTR(3),
• CMB_MSR_ATTR(4),
• CMB_MSR_ATTR(5),
• CMB_MSR_ATTR(6),
• CMB_MSR_ATTR(7),
• CMB_MSR_ATTR(8),
• CMB_MSR_ATTR(9),
• CMB_MSR_ATTR(10),
• CMB_MSR_ATTR(11),
• CMB_MSR_ATTR(12),
• CMB_MSR_ATTR(13),
• CMB_MSR_ATTR(14),
• CMB_MSR_ATTR(15),
• CMB_MSR_ATTR(16),
• CMB_MSR_ATTR(17),
• CMB_MSR_ATTR(18),
• CMB_MSR_ATTR(19),
• CMB_MSR_ATTR(20),
• CMB_MSR_ATTR(21),
• CMB_MSR_ATTR(22),
• CMB_MSR_ATTR(23),
• CMB_MSR_ATTR(24),
• CMB_MSR_ATTR(25),
• CMB_MSR_ATTR(26),
• CMB_MSR_ATTR(27),
• CMB_MSR_ATTR(28),
• CMB_MSR_ATTR(29),
• CMB_MSR_ATTR(30),
• CMB_MSR_ATTR(31),
• NULL,

+};

• static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr,

@@ -1144,6 +1219,12 @@ static struct attribute_group tpdm_cmb_patt_grp = { .name = "cmb_patt", }; +static struct attribute_group tpdm_cmb_msr_grp = {

• .attrs = tpdm_cmb_msr_attrs,
• .is_visible = tpdm_cmb_msr_is_visible,
• .name = "cmb_msr",

+};

• static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attr_grp,

@@ -1154,6 +1235,7 @@ static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_cmb_attr_grp, &tpdm_cmb_trig_patt_grp, &tpdm_cmb_patt_grp,

• &tpdm_cmb_msr_grp, NULL, };

@@ -1192,6 +1274,10 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) of_property_read_u32(drvdata->dev->of_node, "qcom,dsb-msrs-num", &drvdata->dsb_msr_num);

• if (drvdata && tpdm_has_cmb_dataset(drvdata))

• of_property_read_u32(drvdata->dev->of_node,
  

• 	   "qcom,cmb-msrs-num", &drvdata->cmb_msr_num);
  

• /* Set up coresight component description */ desc.name = coresight_alloc_device_name(&tpdm_devs, dev); if (!desc.name)

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 65b7ca6c4077..255104d024ab 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -21,6 +21,8 @@ #define TPDM_CMB_XPR(n) (0xA18 + (n * 4)) /*CMB subunit trigger pattern mask registers*/ #define TPDM_CMB_XPMR(n) (0xA20 + (n * 4)) +/* CMB MSR register */ +#define TPDM_CMB_MSR(n) (0xA80 + (n * 4)) /* Enable bit for CMB subunit */ #define TPDM_CMB_CR_ENA BIT(0) @@ -36,6 +38,9 @@ /*Patten register number*/ #define TPDM_CMB_MAX_PATT 2 +/* MAX number of DSB MSR */ +#define TPDM_CMB_MAX_MSR 32

• /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784)

@@ -186,6 +191,10 @@ tpdm_simple_dataset_rw(tpmr##nr, \ CMB_PATT_MASK, nr) +#define CMB_MSR_ATTR(nr) \

• tpdm_simple_dataset_rw(msr##nr,			\
  

• CMB_MSR, nr)
  

• /**
  • struct dsb_dataset - specifics associated to dsb dataset
  • @mode: DSB programming mode

@@ -225,6 +234,7 @@ struct dsb_dataset {

• @patt_mask: Save value for pattern mask
• @trig_patt: Save value for trigger pattern
• @trig_patt_mask: Save value for trigger pattern mask

• • @msr Save value for MSR
  • @patt_ts: Indicates if pattern match for timestamp is enabled.
  • @trig_ts: Indicates if CTI trigger for timestamp is enabled.
  • @ts_all: Indicates if timestamp is enabled for all packets.

@@ -235,6 +245,7 @@ struct cmb_dataset { u32 patt_mask[TPDM_CMB_MAX_PATT]; u32 trig_patt[TPDM_CMB_MAX_PATT]; u32 trig_patt_mask[TPDM_CMB_MAX_PATT];

• u32 msr[TPDM_CMB_MAX_MSR]; bool patt_ts; bool trig_ts; bool ts_all;

@@ -251,6 +262,7 @@ struct cmb_dataset {

• @dsb Specifics associated to TPDM DSB.
• @cmb Specifics associated to TPDM CMB.
• @dsb_msr_num Number of MSR supported by DSB TPDM

• • @cmb_msr_num Number of MSR supported by CMB TPDM
  */

struct tpdm_drvdata { @@ -263,6 +275,7 @@ struct tpdm_drvdata { struct dsb_dataset *dsb; struct cmb_dataset *cmb; u32 dsb_msr_num;

• u32 cmb_msr_num; };

/* Enumerate members of various datasets */ @@ -277,7 +290,8 @@ enum dataset_mem { CMB_TRIG_PATT, CMB_TRIG_PATT_MASK, CMB_PATT,

• CMB_PATT_MASK

• CMB_PATT_MASK,
• CMB_MSR };

/**

On 19/12/2023 06:58, Tao Zhang wrote:

On 12/18/2023 7:02 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote:

...

Add the nodes for CMB subunit MSR(mux select register) support. CMB MSRs(mux select registers) is to separate mux,arbitration, ,interleaving,data packing control from stream filtering control.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

.../testing/sysfs-bus-coresight-devices-tpdm  |  8 ++   drivers/hwtracing/coresight/coresight-tpdm.c  | 86 +++++++++++++++++++   drivers/hwtracing/coresight/coresight-tpdm.h  | 16 +++-   3 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e0b77107be13..914f3fd81525 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -249,3 +249,11 @@ Description:           Accepts only one of the 2 values -  0 or 1.           0 : Disable the timestamp of all trace packets.           1 : Enable the timestamp of all trace packets.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the MSR(mux select register) for the CMB subunit +        TPDM. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f6cda5616e84..7e331ea436cc 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -86,6 +86,11 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev,               return -EINVAL;           return sysfs_emit(buf, "0x%x\n",               drvdata->cmb->patt_mask[tpdm_attr->idx]); +    case CMB_MSR: +        if (tpdm_attr->idx >= drvdata->cmb_msr_num) +            return -EINVAL; +        return sysfs_emit(buf, "0x%x\n", +                drvdata->cmb->msr[tpdm_attr->idx]);       }       return -EINVAL;   } @@ -162,6 +167,12 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev,           else               ret = -EINVAL;           break; +    case CMB_MSR: +        if (tpdm_attr->idx < drvdata->cmb_msr_num) +            drvdata->cmb->msr[tpdm_attr->idx] = val; +        else +            ret = -EINVAL;

minor nit: Could we not break from here instead of adding return -EINVAL for each case ? (I understand it has been done for the existing cases. But I think we should clean up all of that, including the ones you added in Patch 5. Similarly for the dataset_show()

Sure, do I also need to change the DSB corresponding code? If so, how about

if I add a new patch to the next patch series to change the previous existing cases?

You could fix the existing cases as a preparatory patch of the next version of this series. I can pick it up and push it to next as I see fit.

Suzuki

Best,

Tao

...

Suzuki

...

+        break;       default:           ret = -EINVAL;       } @@ -220,6 +231,23 @@ static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj,       return 0;   }   +static umode_t tpdm_cmb_msr_is_visible(struct kobject *kobj, +                       struct attribute *attr, int n) +{ +    struct device *dev = kobj_to_dev(kobj); +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    struct device_attribute *dev_attr = +        container_of(attr, struct device_attribute, attr); +    struct tpdm_dataset_attribute *tpdm_attr = +        container_of(dev_attr, struct tpdm_dataset_attribute, attr);

+    if (tpdm_attr->idx < drvdata->cmb_msr_num) +        return attr->mode;

+    return 0; +}

static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata)   {       if (tpdm_has_dsb_dataset(drvdata)) { @@ -361,6 +389,15 @@ static void set_cmb_tier(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_CMB_TIER);   }   +static void set_cmb_msr(struct tpdm_drvdata *drvdata) +{ +    int i;

+    for (i = 0; i < drvdata->cmb_msr_num; i++) +        writel_relaxed(drvdata->cmb->msr[i], +               drvdata->base + TPDM_CMB_MSR(i)); +}

static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)   {       u32 val, i; @@ -379,6 +416,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)         set_cmb_tier(drvdata);   +    set_cmb_msr(drvdata);

val = readl_relaxed(drvdata->base + TPDM_CMB_CR);       /*        * Set to 0 for continuous CMB collection mode, @@ -1084,6 +1123,42 @@ static struct attribute *tpdm_cmb_patt_attrs[] = {       NULL,   };   +static struct attribute *tpdm_cmb_msr_attrs[] = { +    CMB_MSR_ATTR(0), +    CMB_MSR_ATTR(1), +    CMB_MSR_ATTR(2), +    CMB_MSR_ATTR(3), +    CMB_MSR_ATTR(4), +    CMB_MSR_ATTR(5), +    CMB_MSR_ATTR(6), +    CMB_MSR_ATTR(7), +    CMB_MSR_ATTR(8), +    CMB_MSR_ATTR(9), +    CMB_MSR_ATTR(10), +    CMB_MSR_ATTR(11), +    CMB_MSR_ATTR(12), +    CMB_MSR_ATTR(13), +    CMB_MSR_ATTR(14), +    CMB_MSR_ATTR(15), +    CMB_MSR_ATTR(16), +    CMB_MSR_ATTR(17), +    CMB_MSR_ATTR(18), +    CMB_MSR_ATTR(19), +    CMB_MSR_ATTR(20), +    CMB_MSR_ATTR(21), +    CMB_MSR_ATTR(22), +    CMB_MSR_ATTR(23), +    CMB_MSR_ATTR(24), +    CMB_MSR_ATTR(25), +    CMB_MSR_ATTR(26), +    CMB_MSR_ATTR(27), +    CMB_MSR_ATTR(28), +    CMB_MSR_ATTR(29), +    CMB_MSR_ATTR(30), +    CMB_MSR_ATTR(31), +    NULL, +};

static struct attribute *tpdm_dsb_attrs[] = {       &dev_attr_dsb_mode.attr,       &dev_attr_dsb_trig_ts.attr, @@ -1144,6 +1219,12 @@ static struct attribute_group tpdm_cmb_patt_grp = {       .name = "cmb_patt",   };   +static struct attribute_group tpdm_cmb_msr_grp = { +    .attrs = tpdm_cmb_msr_attrs, +    .is_visible = tpdm_cmb_msr_is_visible, +    .name = "cmb_msr", +};

static const struct attribute_group *tpdm_attr_grps[] = {       &tpdm_attr_grp,       &tpdm_dsb_attr_grp, @@ -1154,6 +1235,7 @@ static const struct attribute_group *tpdm_attr_grps[] = {       &tpdm_cmb_attr_grp,       &tpdm_cmb_trig_patt_grp,       &tpdm_cmb_patt_grp, +    &tpdm_cmb_msr_grp,       NULL,   };   @@ -1192,6 +1274,10 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)           of_property_read_u32(drvdata->dev->of_node,                  "qcom,dsb-msrs-num", &drvdata->dsb_msr_num);   +    if (drvdata && tpdm_has_cmb_dataset(drvdata)) +        of_property_read_u32(drvdata->dev->of_node, +               "qcom,cmb-msrs-num", &drvdata->cmb_msr_num);

/* Set up coresight component description */       desc.name = coresight_alloc_device_name(&tpdm_devs, dev);       if (!desc.name) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 65b7ca6c4077..255104d024ab 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -21,6 +21,8 @@   #define TPDM_CMB_XPR(n)        (0xA18 + (n * 4))   /*CMB subunit trigger pattern mask registers*/   #define TPDM_CMB_XPMR(n)    (0xA20 + (n * 4)) +/* CMB MSR register */ +#define TPDM_CMB_MSR(n)        (0xA80 + (n * 4))     /* Enable bit for CMB subunit */   #define TPDM_CMB_CR_ENA        BIT(0) @@ -36,6 +38,9 @@   /*Patten register number*/   #define TPDM_CMB_MAX_PATT        2   +/* MAX number of DSB MSR */ +#define TPDM_CMB_MAX_MSR 32

/* DSB Subunit Registers */   #define TPDM_DSB_CR        (0x780)   #define TPDM_DSB_TIER        (0x784) @@ -186,6 +191,10 @@           tpdm_simple_dataset_rw(tpmr##nr,        \           CMB_PATT_MASK, nr)   +#define CMB_MSR_ATTR(nr)                    \ +        tpdm_simple_dataset_rw(msr##nr,            \ +        CMB_MSR, nr)

/**    * struct dsb_dataset - specifics associated to dsb dataset    * @mode:             DSB programming mode @@ -225,6 +234,7 @@ struct dsb_dataset {    * @patt_mask:        Save value for pattern mask    * @trig_patt:        Save value for trigger pattern    * @trig_patt_mask:   Save value for trigger pattern mask

• • @msr               Save value for MSR

* @patt_ts:          Indicates if pattern match for timestamp is enabled.    * @trig_ts:          Indicates if CTI trigger for timestamp is enabled.    * @ts_all:           Indicates if timestamp is enabled for all packets. @@ -235,6 +245,7 @@ struct cmb_dataset {       u32            patt_mask[TPDM_CMB_MAX_PATT];       u32            trig_patt[TPDM_CMB_MAX_PATT];       u32            trig_patt_mask[TPDM_CMB_MAX_PATT]; +    u32            msr[TPDM_CMB_MAX_MSR];       bool            patt_ts;       bool            trig_ts;       bool            ts_all; @@ -251,6 +262,7 @@ struct cmb_dataset {    * @dsb         Specifics associated to TPDM DSB.    * @cmb         Specifics associated to TPDM CMB.    * @dsb_msr_num Number of MSR supported by DSB TPDM

• • @cmb_msr_num Number of MSR supported by CMB TPDM

*/     struct tpdm_drvdata { @@ -263,6 +275,7 @@ struct tpdm_drvdata {       struct dsb_dataset    *dsb;       struct cmb_dataset    *cmb;       u32            dsb_msr_num; +    u32            cmb_msr_num;   };     /* Enumerate members of various datasets */ @@ -277,7 +290,8 @@ enum dataset_mem {       CMB_TRIG_PATT,       CMB_TRIG_PATT_MASK,       CMB_PATT, -    CMB_PATT_MASK +    CMB_PATT_MASK, +    CMB_MSR   };     /**

---

CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org

On 12/20/2023 5:06 PM, Tao Zhang wrote:

On 12/19/2023 10:09 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 06:58, Tao Zhang wrote:

...

On 12/18/2023 7:02 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote:

...

Add the nodes for CMB subunit MSR(mux select register) support. CMB MSRs(mux select registers) is to separate mux,arbitration, ,interleaving,data packing control from stream filtering control.

Reviewed-by: James Clark james.clark@arm.com Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com

---

.../testing/sysfs-bus-coresight-devices-tpdm  |  8 ++   drivers/hwtracing/coresight/coresight-tpdm.c  | 86 +++++++++++++++++++   drivers/hwtracing/coresight/coresight-tpdm.h  | 16 +++-   3 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e0b77107be13..914f3fd81525 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -249,3 +249,11 @@ Description:           Accepts only one of the 2 values -  0 or 1.           0 : Disable the timestamp of all trace packets.           1 : Enable the timestamp of all trace packets.

+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] +Date:        September 2023 +KernelVersion    6.7 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the MSR(mux select register) for the CMB subunit +        TPDM. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f6cda5616e84..7e331ea436cc 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -86,6 +86,11 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev,               return -EINVAL;           return sysfs_emit(buf, "0x%x\n", drvdata->cmb->patt_mask[tpdm_attr->idx]); +    case CMB_MSR: +        if (tpdm_attr->idx >= drvdata->cmb_msr_num) +            return -EINVAL; +        return sysfs_emit(buf, "0x%x\n",

• drvdata->cmb->msr[tpdm_attr->idx]);

}       return -EINVAL;   } @@ -162,6 +167,12 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev,           else               ret = -EINVAL;           break; +    case CMB_MSR: +        if (tpdm_attr->idx < drvdata->cmb_msr_num) +            drvdata->cmb->msr[tpdm_attr->idx] = val; +        else +            ret = -EINVAL;

minor nit: Could we not break from here instead of adding return -EINVAL for each case ? (I understand it has been done for the existing cases. But I think we should clean up all of that, including the ones you added in Patch 5. Similarly for the dataset_show()

Sure, do I also need to change the DSB corresponding code? If so, how about

if I add a new patch to the next patch series to change the previous existing cases?

You could fix the existing cases as a preparatory patch of the next version of this series. I can pick it up and push it to next as I see fit.

Got it. I will update this to the next patch series.

Hi Suzuki,

Since the dataset data is configured with spin lock protection, it needs to be unlock before return.

List my modification below. Would you mind help review to see if it is good for you.

static ssize_t tpdm_simple_dataset_store(struct device *dev,                      struct device_attribute *attr,                      const char *buf,                      size_t size) {     unsigned long val;

struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);     struct tpdm_dataset_attribute *tpdm_attr =         container_of(attr, struct tpdm_dataset_attribute, attr);

if (kstrtoul(buf, 0, &val))         return -EINVAL;

spin_lock(&drvdata->spinlock);     switch (tpdm_attr->mem) {     case DSB_TRIG_PATT:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->trig_patt[tpdm_attr->idx] = val;         else {             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_TRIG_PATT_MASK:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_PATT:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->patt_val[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_PATT_MASK:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->patt_mask[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_MSR:         if (tpdm_attr->idx < drvdata->dsb_msr_num)             drvdata->dsb->msr[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     default:         spin_unlock(&drvdata->spinlock);         return -EINVAL;     }     return size;

Best,

Tao

Best,

Tao

...

Suzuki

...

Best,

Tao

...

Suzuki

...

+        break;       default:           ret = -EINVAL;       } @@ -220,6 +231,23 @@ static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj,       return 0;   }   +static umode_t tpdm_cmb_msr_is_visible(struct kobject *kobj, +                       struct attribute *attr, int n) +{ +    struct device *dev = kobj_to_dev(kobj); +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    struct device_attribute *dev_attr = +        container_of(attr, struct device_attribute, attr); +    struct tpdm_dataset_attribute *tpdm_attr = +        container_of(dev_attr, struct tpdm_dataset_attribute, attr);

+    if (tpdm_attr->idx < drvdata->cmb_msr_num) +        return attr->mode;

+    return 0; +}

static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata)   {       if (tpdm_has_dsb_dataset(drvdata)) { @@ -361,6 +389,15 @@ static void set_cmb_tier(struct tpdm_drvdata *drvdata)       writel_relaxed(val, drvdata->base + TPDM_CMB_TIER);   }   +static void set_cmb_msr(struct tpdm_drvdata *drvdata) +{ +    int i;

+    for (i = 0; i < drvdata->cmb_msr_num; i++) +        writel_relaxed(drvdata->cmb->msr[i], +               drvdata->base + TPDM_CMB_MSR(i)); +}

static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)   {       u32 val, i; @@ -379,6 +416,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)         set_cmb_tier(drvdata);   +    set_cmb_msr(drvdata);

val = readl_relaxed(drvdata->base + TPDM_CMB_CR);       /*        * Set to 0 for continuous CMB collection mode, @@ -1084,6 +1123,42 @@ static struct attribute *tpdm_cmb_patt_attrs[] = {       NULL,   };   +static struct attribute *tpdm_cmb_msr_attrs[] = { +    CMB_MSR_ATTR(0), +    CMB_MSR_ATTR(1), +    CMB_MSR_ATTR(2), +    CMB_MSR_ATTR(3), +    CMB_MSR_ATTR(4), +    CMB_MSR_ATTR(5), +    CMB_MSR_ATTR(6), +    CMB_MSR_ATTR(7), +    CMB_MSR_ATTR(8), +    CMB_MSR_ATTR(9), +    CMB_MSR_ATTR(10), +    CMB_MSR_ATTR(11), +    CMB_MSR_ATTR(12), +    CMB_MSR_ATTR(13), +    CMB_MSR_ATTR(14), +    CMB_MSR_ATTR(15), +    CMB_MSR_ATTR(16), +    CMB_MSR_ATTR(17), +    CMB_MSR_ATTR(18), +    CMB_MSR_ATTR(19), +    CMB_MSR_ATTR(20), +    CMB_MSR_ATTR(21), +    CMB_MSR_ATTR(22), +    CMB_MSR_ATTR(23), +    CMB_MSR_ATTR(24), +    CMB_MSR_ATTR(25), +    CMB_MSR_ATTR(26), +    CMB_MSR_ATTR(27), +    CMB_MSR_ATTR(28), +    CMB_MSR_ATTR(29), +    CMB_MSR_ATTR(30), +    CMB_MSR_ATTR(31), +    NULL, +};

static struct attribute *tpdm_dsb_attrs[] = {       &dev_attr_dsb_mode.attr,       &dev_attr_dsb_trig_ts.attr, @@ -1144,6 +1219,12 @@ static struct attribute_group tpdm_cmb_patt_grp = {       .name = "cmb_patt",   };   +static struct attribute_group tpdm_cmb_msr_grp = { +    .attrs = tpdm_cmb_msr_attrs, +    .is_visible = tpdm_cmb_msr_is_visible, +    .name = "cmb_msr", +};

static const struct attribute_group *tpdm_attr_grps[] = {       &tpdm_attr_grp,       &tpdm_dsb_attr_grp, @@ -1154,6 +1235,7 @@ static const struct attribute_group *tpdm_attr_grps[] = {       &tpdm_cmb_attr_grp,       &tpdm_cmb_trig_patt_grp,       &tpdm_cmb_patt_grp, +    &tpdm_cmb_msr_grp,       NULL,   };   @@ -1192,6 +1274,10 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) of_property_read_u32(drvdata->dev->of_node,                  "qcom,dsb-msrs-num", &drvdata->dsb_msr_num);   +    if (drvdata && tpdm_has_cmb_dataset(drvdata)) +        of_property_read_u32(drvdata->dev->of_node, +               "qcom,cmb-msrs-num", &drvdata->cmb_msr_num);

/* Set up coresight component description */       desc.name = coresight_alloc_device_name(&tpdm_devs, dev);       if (!desc.name) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 65b7ca6c4077..255104d024ab 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -21,6 +21,8 @@   #define TPDM_CMB_XPR(n)        (0xA18 + (n * 4))   /*CMB subunit trigger pattern mask registers*/   #define TPDM_CMB_XPMR(n)    (0xA20 + (n * 4)) +/* CMB MSR register */ +#define TPDM_CMB_MSR(n)        (0xA80 + (n * 4))     /* Enable bit for CMB subunit */   #define TPDM_CMB_CR_ENA        BIT(0) @@ -36,6 +38,9 @@   /*Patten register number*/   #define TPDM_CMB_MAX_PATT        2   +/* MAX number of DSB MSR */ +#define TPDM_CMB_MAX_MSR 32

/* DSB Subunit Registers */   #define TPDM_DSB_CR        (0x780)   #define TPDM_DSB_TIER        (0x784) @@ -186,6 +191,10 @@           tpdm_simple_dataset_rw(tpmr##nr,        \           CMB_PATT_MASK, nr)   +#define CMB_MSR_ATTR(nr)                    \ +        tpdm_simple_dataset_rw(msr##nr,            \ +        CMB_MSR, nr)

/**    * struct dsb_dataset - specifics associated to dsb dataset    * @mode:             DSB programming mode @@ -225,6 +234,7 @@ struct dsb_dataset {    * @patt_mask:        Save value for pattern mask    * @trig_patt:        Save value for trigger pattern    * @trig_patt_mask:   Save value for trigger pattern mask

• • @msr               Save value for MSR

* @patt_ts:          Indicates if pattern match for timestamp is enabled.    * @trig_ts:          Indicates if CTI trigger for timestamp is enabled.    * @ts_all:           Indicates if timestamp is enabled for all packets. @@ -235,6 +245,7 @@ struct cmb_dataset {       u32            patt_mask[TPDM_CMB_MAX_PATT];       u32            trig_patt[TPDM_CMB_MAX_PATT];       u32            trig_patt_mask[TPDM_CMB_MAX_PATT]; +    u32            msr[TPDM_CMB_MAX_MSR];       bool            patt_ts;       bool            trig_ts;       bool            ts_all; @@ -251,6 +262,7 @@ struct cmb_dataset {    * @dsb         Specifics associated to TPDM DSB.    * @cmb         Specifics associated to TPDM CMB.    * @dsb_msr_num Number of MSR supported by DSB TPDM

• • @cmb_msr_num Number of MSR supported by CMB TPDM

*/     struct tpdm_drvdata { @@ -263,6 +275,7 @@ struct tpdm_drvdata {       struct dsb_dataset    *dsb;       struct cmb_dataset    *cmb;       u32            dsb_msr_num; +    u32            cmb_msr_num;   };     /* Enumerate members of various datasets */ @@ -277,7 +290,8 @@ enum dataset_mem {       CMB_TRIG_PATT,       CMB_TRIG_PATT_MASK,       CMB_PATT, -    CMB_PATT_MASK +    CMB_PATT_MASK, +    CMB_MSR   };     /**

---

CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org

---

CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org

On 1/12/2024 5:43 PM, Suzuki K Poulose wrote:

On 12/01/2024 09:12, Tao Zhang wrote:

...

On 12/20/2023 5:06 PM, Tao Zhang wrote:

...

On 12/19/2023 10:09 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 06:58, Tao Zhang wrote:

...

On 12/18/2023 7:02 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote: > Add the nodes for CMB subunit MSR(mux select register) support. > CMB MSRs(mux select registers) is to separate mux,arbitration, > ,interleaving,data packing control from stream filtering control. > > Reviewed-by: James Clark james.clark@arm.com > Signed-off-by: Tao Zhang quic_taozha@quicinc.com > Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com > --- >   .../testing/sysfs-bus-coresight-devices-tpdm  |  8 ++ >   drivers/hwtracing/coresight/coresight-tpdm.c  | 86 > +++++++++++++++++++ >   drivers/hwtracing/coresight/coresight-tpdm.h  | 16 +++- >   3 files changed, 109 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index e0b77107be13..914f3fd81525 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -249,3 +249,11 @@ Description: >           Accepts only one of the 2 values -  0 or 1. >           0 : Disable the timestamp of all trace packets. >           1 : Enable the timestamp of all trace packets. > + > +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] > +Date:        September 2023 > +KernelVersion    6.7 > +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao > Zhang (QUIC) quic_taozha@quicinc.com > +Description: > +        (RW) Set/Get the MSR(mux select register) for the CMB > subunit > +        TPDM. > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c > b/drivers/hwtracing/coresight/coresight-tpdm.c > index f6cda5616e84..7e331ea436cc 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -86,6 +86,11 @@ static ssize_t > tpdm_simple_dataset_show(struct device *dev, >               return -EINVAL; >           return sysfs_emit(buf, "0x%x\n", > drvdata->cmb->patt_mask[tpdm_attr->idx]); > +    case CMB_MSR: > +        if (tpdm_attr->idx >= drvdata->cmb_msr_num) > +            return -EINVAL; > +        return sysfs_emit(buf, "0x%x\n", > + drvdata->cmb->msr[tpdm_attr->idx]); >       } >       return -EINVAL; >   } > @@ -162,6 +167,12 @@ static ssize_t > tpdm_simple_dataset_store(struct device *dev, >           else >               ret = -EINVAL; >           break; > +    case CMB_MSR: > +        if (tpdm_attr->idx < drvdata->cmb_msr_num) > + drvdata->cmb->msr[tpdm_attr->idx] = val; > +        else > +            ret = -EINVAL;

minor nit: Could we not break from here instead of adding return -EINVAL for each case ? (I understand it has been done for the existing cases. But I think we should clean up all of that, including the ones you added in Patch 5. Similarly for the dataset_show()

Sure, do I also need to change the DSB corresponding code? If so, how about

if I add a new patch to the next patch series to change the previous existing cases?

You could fix the existing cases as a preparatory patch of the next version of this series. I can pick it up and push it to next as I see fit.

Got it. I will update this to the next patch series.

Hi Suzuki,

Since the dataset data is configured with spin lock protection, it needs to be unlock before return.

List my modification below. Would you mind help review to see if it is good for you.

static ssize_t tpdm_simple_dataset_store(struct device *dev,                       struct device_attribute *attr,                       const char *buf,                       size_t size) {      unsigned long val;

struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);      struct tpdm_dataset_attribute *tpdm_attr =          container_of(attr, struct tpdm_dataset_attribute, attr);

if (kstrtoul(buf, 0, &val))          return -EINVAL;

spin_lock(&drvdata->spinlock);

Use guard() to avoid explicit unlock on return and then you don't need the spin_unlock() everywhere. It would be done on return from the function implicitly.

...

switch (tpdm_attr->mem) {      case DSB_TRIG_PATT:

With guard() in place:

ret = -EINVAL;

switch () {     case XXX:

if (tpdm_attr->idx < TPDM_XXXX_IDX) {            drvdata->dsb->trig_patt[tpdm_attr->idx] = val;            ret = size;        }        break;     case ...         ...     }

return ret;

Thanks for your suggestion. I will update the code like below.

I will update it in the next version of the patch series if it meets your expectation.

static ssize_t tpdm_simple_dataset_store(struct device *dev,                      struct device_attribute *attr,                      const char *buf,                      size_t size) {     unsigned long val;     ssize_t ret = -EINVAL;

struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);     struct tpdm_dataset_attribute *tpdm_attr =         container_of(attr, struct tpdm_dataset_attribute, attr);

if (kstrtoul(buf, 0, &val))         return ret;

guard(spinlock)(&drvdata->spinlock);     switch (tpdm_attr->mem) {     case DSB_TRIG_PATT:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT) {             drvdata->dsb->trig_patt[tpdm_attr->idx] = val;             ret =size;         }         break;     case ...

...     }     return ret; }

Best,

Tao

Suzuki

On 1/15/2024 5:20 PM, Suzuki K Poulose wrote:

On 15/01/2024 06:20, Tao Zhang wrote:

...

On 1/12/2024 5:43 PM, Suzuki K Poulose wrote:

...

On 12/01/2024 09:12, Tao Zhang wrote:

...

On 12/20/2023 5:06 PM, Tao Zhang wrote:

...

On 12/19/2023 10:09 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 06:58, Tao Zhang wrote: > > On 12/18/2023 7:02 PM, Suzuki K Poulose wrote: >> On 21/11/2023 02:24, Tao Zhang wrote: >>> Add the nodes for CMB subunit MSR(mux select register) support. >>> CMB MSRs(mux select registers) is to separate mux,arbitration, >>> ,interleaving,data packing control from stream filtering control. >>> >>> Reviewed-by: James Clark james.clark@arm.com >>> Signed-off-by: Tao Zhang quic_taozha@quicinc.com >>> Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com >>> --- >>>   .../testing/sysfs-bus-coresight-devices-tpdm  | 8 ++ >>>   drivers/hwtracing/coresight/coresight-tpdm.c  | 86 >>> +++++++++++++++++++ >>>   drivers/hwtracing/coresight/coresight-tpdm.h  | 16 +++- >>>   3 files changed, 109 insertions(+), 1 deletion(-) >>> >>> diff --git >>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> index e0b77107be13..914f3fd81525 100644 >>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>> @@ -249,3 +249,11 @@ Description: >>>           Accepts only one of the 2 values -  0 or 1. >>>           0 : Disable the timestamp of all trace packets. >>>           1 : Enable the timestamp of all trace packets. >>> + >>> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] >>> +Date:        September 2023 >>> +KernelVersion    6.7 >>> +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, >>> Tao Zhang (QUIC) quic_taozha@quicinc.com >>> +Description: >>> +        (RW) Set/Get the MSR(mux select register) for the CMB >>> subunit >>> +        TPDM. >>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c >>> b/drivers/hwtracing/coresight/coresight-tpdm.c >>> index f6cda5616e84..7e331ea436cc 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >>> @@ -86,6 +86,11 @@ static ssize_t >>> tpdm_simple_dataset_show(struct device *dev, >>>               return -EINVAL; >>>           return sysfs_emit(buf, "0x%x\n", >>> drvdata->cmb->patt_mask[tpdm_attr->idx]); >>> +    case CMB_MSR: >>> +        if (tpdm_attr->idx >= drvdata->cmb_msr_num) >>> +            return -EINVAL; >>> +        return sysfs_emit(buf, "0x%x\n", >>> + drvdata->cmb->msr[tpdm_attr->idx]); >>>       } >>>       return -EINVAL; >>>   } >>> @@ -162,6 +167,12 @@ static ssize_t >>> tpdm_simple_dataset_store(struct device *dev, >>>           else >>>               ret = -EINVAL; >>>           break; >>> +    case CMB_MSR: >>> +        if (tpdm_attr->idx < drvdata->cmb_msr_num) >>> + drvdata->cmb->msr[tpdm_attr->idx] = val; >>> +        else >>> +            ret = -EINVAL; >> >> >> minor nit: Could we not break from here instead of adding >> return -EINVAL >> for each case ? (I understand it has been done for the existing >> cases. >> But I think we should clean up all of that, including the ones >> you added >> in Patch 5. Similarly for the dataset_show() > > Sure, do I also need to change the DSB corresponding code? If > so, how about > > if I add a new patch to the next patch series to change the > previous existing cases?

You could fix the existing cases as a preparatory patch of the next version of this series. I can pick it up and push it to next as I see fit.

Got it. I will update this to the next patch series.

Hi Suzuki,

Since the dataset data is configured with spin lock protection, it needs to be unlock before return.

List my modification below. Would you mind help review to see if it is good for you.

static ssize_t tpdm_simple_dataset_store(struct device *dev,                       struct device_attribute *attr,                       const char *buf,                       size_t size) {      unsigned long val;

struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);      struct tpdm_dataset_attribute *tpdm_attr =          container_of(attr, struct tpdm_dataset_attribute, attr);

if (kstrtoul(buf, 0, &val))          return -EINVAL;

spin_lock(&drvdata->spinlock);

Use guard() to avoid explicit unlock on return and then you don't need the spin_unlock() everywhere. It would be done on return from the function implicitly.

...

switch (tpdm_attr->mem) {      case DSB_TRIG_PATT:

With guard() in place:

ret = -EINVAL;

switch () {     case XXX:

if (tpdm_attr->idx < TPDM_XXXX_IDX) {            drvdata->dsb->trig_patt[tpdm_attr->idx] = val;            ret = size;        }        break;     case ...         ...     }

return ret;

Thanks for your suggestion. I will update the code like below.

I will update it in the next version of the patch series if it meets your expectation.

static ssize_t tpdm_simple_dataset_store(struct device *dev,                       struct device_attribute *attr,                       const char *buf,                       size_t size) {      unsigned long val;      ssize_t ret = -EINVAL;

struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);      struct tpdm_dataset_attribute *tpdm_attr =          container_of(attr, struct tpdm_dataset_attribute, attr);

if (kstrtoul(buf, 0, &val))          return ret;

guard(spinlock)(&drvdata->spinlock);      switch (tpdm_attr->mem) {      case DSB_TRIG_PATT:          if (tpdm_attr->idx < TPDM_DSB_MAX_PATT) {              drvdata->dsb->trig_patt[tpdm_attr->idx] = val;              ret =size;          }          break;      case ...

...      }      return ret; }

Yes that looks good to me. Please rebase this on to for-next/queue branch on the coresight repository.

Got it. Thanks for your mention.

Best,

Tao

Suzuki

On 15/01/2024 09:55, James Clark wrote:

On 12/01/2024 09:12, Tao Zhang wrote:

...

On 12/20/2023 5:06 PM, Tao Zhang wrote:

...

On 12/19/2023 10:09 PM, Suzuki K Poulose wrote:

...

On 19/12/2023 06:58, Tao Zhang wrote:

...

On 12/18/2023 7:02 PM, Suzuki K Poulose wrote:

...

On 21/11/2023 02:24, Tao Zhang wrote: > Add the nodes for CMB subunit MSR(mux select register) support. > CMB MSRs(mux select registers) is to separate mux,arbitration, > ,interleaving,data packing control from stream filtering control. > > Reviewed-by: James Clark james.clark@arm.com > Signed-off-by: Tao Zhang quic_taozha@quicinc.com > Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com > --- >   .../testing/sysfs-bus-coresight-devices-tpdm  |  8 ++ >   drivers/hwtracing/coresight/coresight-tpdm.c  | 86 > +++++++++++++++++++ >   drivers/hwtracing/coresight/coresight-tpdm.h  | 16 +++- >   3 files changed, 109 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index e0b77107be13..914f3fd81525 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -249,3 +249,11 @@ Description: >           Accepts only one of the 2 values -  0 or 1. >           0 : Disable the timestamp of all trace packets. >           1 : Enable the timestamp of all trace packets. > + > +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] > +Date:        September 2023 > +KernelVersion    6.7 > +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao > Zhang (QUIC) quic_taozha@quicinc.com > +Description: > +        (RW) Set/Get the MSR(mux select register) for the CMB > subunit > +        TPDM. > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c > b/drivers/hwtracing/coresight/coresight-tpdm.c > index f6cda5616e84..7e331ea436cc 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -86,6 +86,11 @@ static ssize_t tpdm_simple_dataset_show(struct > device *dev, >               return -EINVAL; >           return sysfs_emit(buf, "0x%x\n", > drvdata->cmb->patt_mask[tpdm_attr->idx]); > +    case CMB_MSR: > +        if (tpdm_attr->idx >= drvdata->cmb_msr_num) > +            return -EINVAL; > +        return sysfs_emit(buf, "0x%x\n", > + drvdata->cmb->msr[tpdm_attr->idx]); >       } >       return -EINVAL; >   } > @@ -162,6 +167,12 @@ static ssize_t > tpdm_simple_dataset_store(struct device *dev, >           else >               ret = -EINVAL; >           break; > +    case CMB_MSR: > +        if (tpdm_attr->idx < drvdata->cmb_msr_num) > +            drvdata->cmb->msr[tpdm_attr->idx] = val; > +        else > +            ret = -EINVAL;

minor nit: Could we not break from here instead of adding return -EINVAL for each case ? (I understand it has been done for the existing cases. But I think we should clean up all of that, including the ones you added in Patch 5. Similarly for the dataset_show()

Sure, do I also need to change the DSB corresponding code? If so, how about

if I add a new patch to the next patch series to change the previous existing cases?

You could fix the existing cases as a preparatory patch of the next version of this series. I can pick it up and push it to next as I see fit.

Got it. I will update this to the next patch series.

Hi Suzuki,

Since the dataset data is configured with spin lock protection, it needs to be unlock before return.

List my modification below. Would you mind help review to see if it is good for you.

static ssize_t tpdm_simple_dataset_store(struct device *dev,                      struct device_attribute *attr,                      const char *buf,                      size_t size) {     unsigned long val;

struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);     struct tpdm_dataset_attribute *tpdm_attr =         container_of(attr, struct tpdm_dataset_attribute, attr);

if (kstrtoul(buf, 0, &val))         return -EINVAL;

spin_lock(&drvdata->spinlock);     switch (tpdm_attr->mem) {     case DSB_TRIG_PATT:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->trig_patt[tpdm_attr->idx] = val;         else {             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_TRIG_PATT_MASK:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_PATT:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->patt_val[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_PATT_MASK:         if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)             drvdata->dsb->patt_mask[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     case DSB_MSR:         if (tpdm_attr->idx < drvdata->dsb_msr_num)             drvdata->dsb->msr[tpdm_attr->idx] = val;         else{             spin_unlock(&drvdata->spinlock);             return -EINVAL;         }     default:         spin_unlock(&drvdata->spinlock);         return -EINVAL;     }     return size;

Best,

Tao

This looks like a good fit for the new guard(spinlock)(&drvdata->spinlock) thing. Then there is no need to do all the manual unlocking.

Oh I see Suzuki already suggested it, nevermind.