The latest ARM CoreSight specification updates the component identification requirements for all components attached to an AMBA bus. (ARM IHI 0029E)
This specification defines bits 15:12 in the ComponentID (CID) value as the device class. Identification requirements now depend on this class. Class 0xF: Traditional components identified by Peripheral ID (PID) only. Class 0x9: CoreSight components may be identified by a Universal Component Identifier (UCI) consisting of the PID plus CoreSight DevType and DevArch values.
Current and future ARM CoreSight IP will now use the same PID for components on the same function - e.g. the ETM, CTI, PMU and Debug elements associated with a core. The first core to use this UCI method is the A35, which currently has binding entries in the ETMv4 driver.
This patchset prepares for the addition of the upcoming CTI driver, which will need to correctly bind with A35 and future hardware, while overcoming the limitation of binding by PID alone, which cannot now work.
The patchset updates the current AMBA Identification mechanism, which was already differentiating between 0xF and 0x9 CIDs, to add additional UCI compliant tests for the for the 0x9 device class.
Additional UCI structures are provided and added to the ETMv4 driver as appropriate.
Russell: Do you want me to add these 2 patches to your patch tracking system? Thanks Mike
Changes since v2: Simplification of amba_cs_uci_id_match(). Fix CID class bitfield comments. Dropped RFC tag on patchset.
Mike Leach (2): drivers: amba: Updates to component identification for driver matching. coresight: etmv4: Update ID register table to add UCI support
drivers/amba/bus.c | 45 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++- include/linux/amba/bus.h | 32 +++++++++++++ 3 files changed, 86 insertions(+), 9 deletions(-)
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 15:12 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org --- drivers/amba/bus.c | 45 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..524296a0eba0 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,36 @@
#define to_amba_driver(d) container_of(d, struct amba_driver, drv)
-static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci; + + uci = table->data;
+ /* no table data - return match on periphid */ + if (!uci) + return 1; + + /* test against read devtype and masked devarch value */ + ret = (dev->uci.devtype == uci->devtype) && + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + return ret; +} + +static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) { - ret = (dev->periphid & table->mask) == table->id; - if (ret) - break; + if (((dev->periphid & table->mask) == table->id) && + ((dev->cid != CORESIGHT_CID) || + (amba_cs_uci_id_match(table, dev)))) + return table; table++; } - - return ret ? table : NULL; + return NULL; }
static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +416,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
+ if (cid == CORESIGHT_CID) { + /* set the base to the start of the last 4k block */ + void __iomem *csbase = tmp + size - 4096; + + dev->uci.devarch = + readl(csbase + UCI_REG_DEVARCH_OFFSET); + dev->uci.devtype = + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; + } + amba_put_disable_pclk(dev);
- if (cid == AMBA_CID || cid == CORESIGHT_CID) + if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid; + dev->cid = cid; + }
if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..8c0f392e4da2 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d
+/* + * CoreSight Architecture specification updates the ID specification + * for components on the AMBA bus. (ARM IHI 0029E) + * + * Bits 15:12 of the CID are the device class. + * + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support + * at present. + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. + * + * Remaining CID bits stay as 0xb105-00d + */ + +/* + * Class 0x9 components use additional values to form a Unique Component + * Identifier (UCI), where peripheral ID values are identical for different + * components. Passed to the amba bus code from the component driver via + * the amba_id->data pointer. + */ +struct amba_cs_uci_id { + unsigned int devarch; + unsigned int devarch_mask; + unsigned int devtype; +}; + +#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC + struct clk;
struct amba_device { @@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid; + unsigned int cid; + struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; };
Hi Mike,
On 18/12/2018 21:59, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
Bits 15:12 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required.
The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching.
CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information.
Signed-off-by: Mike Leach mike.leach@linaro.org Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
Looks like you missed my Reviewed tags on the previous version. Anyways,
Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com
Hi Mike,
Thanks for the patch.
BTW somehow I can't find the latest series in my inbox, so commenting on this here.
Mathieu pointed me to this patch series.This solves CPU debug module sharing same PID as ETM on MSM8996. I will be posting patch for CPU debug UCI table soon.
But please find my one comment inline.
On 12/19/2018 3:29 AM, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
[..]
+static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) {
ret = (dev->periphid & table->mask) == table->id;if (ret)break;
if (((dev->periphid & table->mask) == table->id) &&((dev->cid != CORESIGHT_CID) ||(amba_cs_uci_id_match(table, dev))))
Shouldn't the check be (dev->cid == CORESIGHT_CID) ? Without this STM fails to probe on both SDM845 and MSM8996.
With this,
Tested-by: Sai Prakash Ranjan saiprakash.ranjan@codeaurora.org
Thanks, Sai
Hello Sai On Fri, 25 Jan 2019 at 07:20, Sai Prakash Ranjan saiprakash.ranjan@codeaurora.org wrote:
Hi Mike,
Thanks for the patch.
BTW somehow I can't find the latest series in my inbox, so commenting on this here.
Mathieu pointed me to this patch series.This solves CPU debug module sharing same PID as ETM on MSM8996. I will be posting patch for CPU debug UCI table soon.
But please find my one comment inline.
On 12/19/2018 3:29 AM, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
[..]
+static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) {
ret = (dev->periphid & table->mask) == table->id;if (ret)break;
if (((dev->periphid & table->mask) == table->id) &&((dev->cid != CORESIGHT_CID) ||(amba_cs_uci_id_match(table, dev))))Shouldn't the check be (dev->cid == CORESIGHT_CID) ? Without this STM fails to probe on both SDM845 and MSM8996.
I believe the test is correct
To expand the logic here:
if (dev->periphid & table->mask) == table->id) { //** match on peripheral ID at this point if (CID != CORESIGHT_ID) return table; //** not coresight - match on peripheral ID only //** or if (amba_cs_uci_id_match() ) return table; //** is coresight - match on UCI if available - otherwise peripheral ID only;
However - looking at the coresight STM driver - this is using the private .data field in the amba_id for a name - which I had not spotted before. I will have to revisit this patchset to fix either the amba id struct or the method for getting the uci data into the amba_id.data which allows for multiple uses.
Regards
Mike
With this,
Tested-by: Sai Prakash Ranjan saiprakash.ranjan@codeaurora.org
Thanks, Sai
-- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Mike,
On 25/01/2019 10:37, Mike Leach wrote:
Hello Sai On Fri, 25 Jan 2019 at 07:20, Sai Prakash Ranjan saiprakash.ranjan@codeaurora.org wrote:
Hi Mike,
Thanks for the patch.
BTW somehow I can't find the latest series in my inbox, so commenting on this here.
Mathieu pointed me to this patch series.This solves CPU debug module sharing same PID as ETM on MSM8996. I will be posting patch for CPU debug UCI table soon.
But please find my one comment inline.
On 12/19/2018 3:29 AM, Mike Leach wrote:
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID.
[..]
+static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) {
ret = (dev->periphid & table->mask) == table->id;if (ret)break;
if (((dev->periphid & table->mask) == table->id) &&((dev->cid != CORESIGHT_CID) ||(amba_cs_uci_id_match(table, dev))))Shouldn't the check be (dev->cid == CORESIGHT_CID) ? Without this STM fails to probe on both SDM845 and MSM8996.
I believe the test is correct
To expand the logic here:
if (dev->periphid & table->mask) == table->id) { //** match on peripheral ID at this point if (CID != CORESIGHT_ID) return table; //** not coresight - match on peripheral ID only //** or if (amba_cs_uci_id_match() ) return table; //** is coresight - match on UCI if available - otherwise peripheral ID only;
However - looking at the coresight STM driver - this is using the private .data field in the amba_id for a name - which I had not spotted before.
Good point. We also use this field for Coresight SOC-600 ETR for advertising the caps not detected from hardware.
I will have to revisit this patchset to fix either the amba id struct or the method for getting the uci data into the amba_id.data which allows for multiple uses.
Thanks Mike !
Cheers Suzuki
Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code.
Signed-off-by: Mike Leach mike.leach@linaro.org Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org --- drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..2fb8054e43ab 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1073,12 +1073,28 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) .mask = 0x000fffff, \ }
+static struct amba_cs_uci_id uci_id_etm4[] = { + { + /* ETMv4 UCI data */ + .devarch = 0x47704a13, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000013, + } +}; + +#define ETM4x_AMBA_UCI_ID(pid) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = uci_id_etm4, \ + } + static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ {}, };
On 18/12/2018 21:59, Mike Leach wrote:
Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code.
Signed-off-by: Mike Leach mike.leach@linaro.org Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..2fb8054e43ab 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1073,12 +1073,28 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) .mask = 0x000fffff, \ } +static struct amba_cs_uci_id uci_id_etm4[] = {
- {
/* ETMv4 UCI data */.devarch = 0x47704a13,.devarch_mask = 0xfff0ffff,.devtype = 0x00000013,- }
+};
+#define ETM4x_AMBA_UCI_ID(pid) \
- { \
.id = pid, \.mask = 0x000fffff, \.data = uci_id_etm4, \- }
- static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */
- ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */
- ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ {}, };
Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com
-
Mike Leach -
Sai Prakash Ranjan -
Suzuki K Poulose