On 25/10/2026 16:24, Leo Yan wrote:

This reverts commit 18049c8cff9cc89daadc4df6975f7d9069638926.

The original commit claimed that contiguous AUX pages unnecessarily exacerbate fragmentation for SPE, TRBE and ETR. This is not generally valid: larger allocations can keep pages with the same lifetime together, while order-0 allocations can scatter them across large blocks and prevent free pages from coalescing [1]. The follow-up discussion [2] has not established how forcing order-0 allocations addresses the reported problem.

TRBE and SPE write to virtually addressed buffers. The TRBE L1 TLB has one entry on Neoverse V2 [3] and two on Neoverse V3 [4]. Small mappings increase translation pressure, and TTW stalls can contribute to FIFO overflow and trace loss on TRBE.

Larger allocations provide contiguous, aligned chunks for PMD or contiguous-PTE mappings with the proposed vmap() support [5]. With the proposed vmap() support already applied, the tests in [2] showed that preferring larger AUX allocations reduced L2 data TLB refills by 99.68% in the TRBE test and 34.74% in the SPE test.

Restore the previous policy of trying higher-order allocations first. The allocator already uses __GFP_NORETRY and falls back to smaller orders, including order 0, when larger allocations fail.

Remove PERF_PMU_CAP_AUX_PREFER_LARGE, since the restored default provides that preference. Intel PT retains its existing allocation behaviour, with no functional change.

[1] https://lore.kernel.org/all/aPjrRkjiIt6HmXmT@casper.infradead.org/ [2] https://lore.kernel.org/linux-arm-kernel/20260810-perf_aux_trace_large_granu... [3] https://documentation-service.arm.com/static/633fe1ec4c59b30b517730b8#page=5... [4] https://documentation-service.arm.com/static/67361bd2c7fc0d1f211da382#page=5... [5] https://lore.kernel.org/linux-mm/20260715120813.3609949-1-jiangwen6@xiaomi.c...

Signed-off-by: Leo Yan leo.yan@arm.com

arch/x86/events/intel/pt.c | 2 -- include/linux/perf_event.h | 5 ++--- kernel/events/ring_buffer.c | 29 +++++++++-------------------- 3 files changed, 11 insertions(+), 25 deletions(-)

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 49349afee6119fb6fad815c847cb3cd9daa97604..3782af40f0832a874a7f0b60961d6652513de241 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1896,8 +1896,6 @@ static __init int pt_init(void) if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;

• else

• pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_PREFER_LARGE;
  

pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE | diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index eb3f7bab498ca9bee9ce7193744943b24ab2e0c5..b8d8b005f5c8a7c1def7cad02230bf9ffb876bd6 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -304,9 +304,8 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 #define PERF_PMU_CAP_AUX_PAUSE 0x0200 -#define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 -#define PERF_PMU_CAP_MEDIATED_VPMU 0x0800 -#define PERF_PMU_CAP_SIMD_REGS 0x1000 +#define PERF_PMU_CAP_MEDIATED_VPMU 0x0400 +#define PERF_PMU_CAP_SIMD_REGS 0x0800 /**

• pmu::scope

diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c index 64d4dbdc6c071b72b670dd044616f52981206ae8..95f4fbdfd2764de5b72d901d778c46302f525fad 100644 --- a/kernel/events/ring_buffer.c +++ b/kernel/events/ring_buffer.c @@ -684,15 +684,7 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, { bool overwrite = !(flags & RING_BUFFER_WRITABLE); int node = (event->cpu == -1) ? -1 : cpu_to_node(event->cpu);

• bool use_contiguous_pages = event->pmu->capabilities & (

• PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_PREFER_LARGE);
  

• /*

• * Initialize max_order to 0 for page allocation. This allocates single
  

• * pages to minimize memory fragmentation. This is overridden if the
  

• * PMU needs or prefers contiguous pages (use_contiguous_pages = true).
  

• */
  

• int max_order = 0;
• int ret = -ENOMEM;

• int ret = -ENOMEM, max_order;

if (!has_aux(event)) return -EOPNOTSUPP; @@ -702,8 +694,8 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, if (!overwrite) { /*

•  * Watermark defaults to half the buffer, to aid PMU drivers
  

•  * in double buffering.
  

•  * Watermark defaults to half the buffer, and so does the
  

•  * max_order, to aid PMU drivers in double buffering.
  

  */ if (!watermark) watermark = min_t(unsigned long,

@@ -711,19 +703,16 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, (unsigned long)nr_pages << (PAGE_SHIFT - 1)); /*

•  * If using contiguous pages, use aux_watermark as the basis
  

•  * for chunking to help PMU drivers honor the watermark.
  

•  * Use aux_watermark as the basis for chunking to
  

•  * help PMU drivers honor the watermark.
  

  */

• if (use_contiguous_pages)
  

• 	max_order = get_order(watermark);
  

• max_order = get_order(watermark);
  

  } else { /*

•  * If using contiguous pages, we need to start with the
  

•  * max_order that fits in nr_pages, not the other way around,
  

•  * hence ilog2() and not get_order.
  

•  * We need to start with the max_order that fits in nr_pages,
  

•  * not the other way around, hence ilog2() and not get_order.
  

  */

• if (use_contiguous_pages)
  

• 	max_order = ilog2(nr_pages);
  

• max_order = ilog2(nr_pages);
  

  watermark = 0; }

---

base-commit: 21a7f44fd0765fcc5194130b28767786eba1d1e7 change-id: 20261025-perf_revert_prefer_large_alloc-a0177d6379f6

Best regards,

Reviewed-by: James Clark james.clark@linaro.org