On Mon, Oct 12, 2026 at 02:35:37PM +0200, Michal Simek wrote:

On 10/2/26 17:07, Leo Yan wrote:

...

Static replicators have no programmable registers and need no APB programming clock.

The Zynq clock controller registers dbg_trc and dbg_apb and calls clk_prepare_enable() for each gate the bootloader left on.

That's one bootloader behavior. If there is another bootloader that clocks can be simply disabled. I don't think there is any reason to depends on bootloader behavior. If there are clocks which has to be ON I can't see any reason not to drive them.

My reference to zynq_clk_setup() was to explain that this patch leaves the existing management of dbg_trc and dbg_apb unchanged.

The CoreSight drivers do not request clocks named "dbg_trc" or "dbg_apb". And removing those unused clock properties introduces no additional dependence on the bootloader. Could you clarify how retaining these entries addresses the bootloader concern?

TRM page 741

Trace Port Clock The trace port clock is used to clock the TPIU and trace buffer when the MIO interface is chosen and must be twice the frequency of the desired TPIU clock. The TPIU clock frequency must be chosen to be fast enough to allow the trace port to keep up with the amount of data being traced, but slow enough to meet the dynamic characteristics of the data output buffers of the TPIU.

The quoted paragraph establishes a trace-clock requirement for the TPIU and trace buffer, how does it identify the clock inputs of the funnel and replicator?

Thanks, Leo