On 08/09/2025 03:01, Jie Gan wrote:

Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt.

Acked-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Signed-off-by: Jie Gan jie.gan@oss.qualcomm.com

---

.../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb

• interrupts:
• items:

•  - description: Byte cntr interrupt for etr0
  

•  - description: Byte cntr interrupt for etr1
  

• interrupt-names:
• items:

•  - const: etr0
  

•  - const: etr1
  

Why are they named "etr0" "etr1" ? That would be confusing, isn't it, especially with the Linux driver naming things randomly for the TMC-ETRs.

What we want is the "port" number corresponding to the "TMC-ETR" being monitored ?

Have you explored other options, "port-0", "port-1" ?

Suzuki

• in-ports: $ref: /schemas/graph.yaml#/properties/ports

@@ -56,6 +66,8 @@ additionalProperties: false examples: - |

• #include <dt-bindings/interrupt-controller/arm-gic.h>

• ctcu@1001000 {
      compatible = "qcom,sa8775p-ctcu";
      reg = <0x1001000 0x1000>;
  

@@ -63,6 +75,11 @@ examples: clocks = <&aoss_qmp>; clock-names = "apb";

•    interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
  

•                 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
  

•    interrupt-names = "etr0",
  

•                      "etr1";
  

•     in-ports {
          #address-cells = <1>;
          #size-cells = <0>;