On 05/01/2024 05:58, Linu Cherian wrote:

Add support to use reserved memory for coresight ETR trace buffer.

Introduce a new ETR buffer mode called ETR_MODE_RESRV, which becomes available when ETR device tree node is supplied with a valid reserved memory region.

ETR_MODE_RESRV can be selected only by explicit user request.

$ echo resrv >/sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred

Signed-off-by: Anil Kumar Reddy areddy3@marvell.com Signed-off-by: Linu Cherian lcherian@marvell.com

---

Changelog from v5:

• No changes

  .../hwtracing/coresight/coresight-tmc-core.c | 51 +++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 87 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 27 ++++++ 3 files changed, 164 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 7ec5365e2b64..224b969d7d90 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -22,6 +22,7 @@ #include <linux/spinlock.h> #include <linux/pm_runtime.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/coresight.h> #include <linux/amba/bus.h> @@ -370,6 +371,54 @@ static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata) return (auth & TMC_AUTH_NSID_MASK) == 0x3; } +static struct device_node *tmc_get_region_byname(struct device_node *node,

• 				 char *name)
  

+{

• int index;
• index = of_property_match_string(node, "memory-region-names", name);
• if (index < 0)

• return ERR_PTR(-ENODEV);
  

• return of_parse_phandle(node, "memory-region", index);

+}

+static void tmc_get_reserved_region(struct device *parent) +{

• struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
• struct device_node *node;
• struct resource res;
• int rc;
• node = tmc_get_region_byname(parent->of_node, "tracedata");
• if (IS_ERR_OR_NULL(node)) {

• dev_dbg(parent, "No reserved trace buffer specified\n");
  

• goto out;
  

Given we don't return anything , the goto is pointless, you could return from here.

• }
• rc = of_address_to_resource(node, 0, &res);
• of_node_put(node);
• if (rc || res.start == 0 || resource_size(&res) == 0) {

• dev_err(parent, "Reserved trace buffer memory is invalid\n");
  

• goto out;
  

Same here.

• }
• drvdata->crash_tbuf.vaddr = memremap(res.start,

• 				resource_size(&res),
  

• 				MEMREMAP_WC);
  

• if (IS_ERR_OR_NULL(drvdata->crash_tbuf.vaddr)) {

• dev_err(parent, "Reserved trace buffer mapping failed\n");
  

• rc = PTR_ERR(drvdata->crash_tbuf.vaddr);
  

This is pointless, as we never use this.

• goto out;
  

return

• }
• drvdata->crash_tbuf.paddr = res.start;
• drvdata->crash_tbuf.size = resource_size(&res);

+out:

• return;

+}

• /* Detect and initialise the capabilities of a TMC ETR */ static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps) {

@@ -482,6 +531,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; }

• tmc_get_reserved_region(dev);
• desc.dev = dev;

switch (drvdata->config_type) { diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index af02ba5d5f15..7fd8c4afef74 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -30,6 +30,7 @@ struct etr_buf_hw { bool has_iommu; bool has_etr_sg; bool has_catu;

• bool has_resrv; };

/* @@ -694,6 +695,74 @@ static const struct etr_buf_operations etr_flat_buf_ops = { .get_data = tmc_etr_get_data_flat_buf, }; +/*

• • tmc_etr_alloc_resrv_buf: Allocate a contiguous DMA buffer from reserved region.
• */

+static int tmc_etr_alloc_resrv_buf(struct tmc_drvdata *drvdata,

• 		  struct etr_buf *etr_buf, int node,
  

• 		  void **pages)
  

+{

• struct etr_flat_buf *resrv_buf;
• struct device *real_dev = drvdata->csdev->dev.parent;
• /* We cannot reuse existing pages for resrv buf */
• if (pages)

• return -EINVAL;
  

• resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_KERNEL);
• if (!resrv_buf)

• return -ENOMEM;
  

Shouldn't we also ensure the etr_buf->size < crash_tbuf.size ? Or we could simply allocate the full reserve buf, as we can't use it for anything else. In any case, the buffer should be bounded by the reserved space.

• resrv_buf->daddr = dma_map_resource(real_dev, drvdata->crash_tbuf.paddr,

• 			   etr_buf->size, DMA_FROM_DEVICE, 0);
  

• if (dma_mapping_error(real_dev, resrv_buf->daddr)) {

• dev_err(real_dev, "failed to map source buffer address\n");
  

• kfree(resrv_buf);
  

• return -ENOMEM;
  

• }
• resrv_buf->vaddr = drvdata->crash_tbuf.vaddr;
• resrv_buf->size = etr_buf->size;
• resrv_buf->dev = &drvdata->csdev->dev;
• etr_buf->hwaddr = resrv_buf->daddr;
• etr_buf->mode = ETR_MODE_RESRV;
• etr_buf->private = resrv_buf;
• return 0;

+}

+static void tmc_etr_free_resrv_buf(struct etr_buf *etr_buf) +{

• struct etr_flat_buf *resrv_buf = etr_buf->private;
• if (resrv_buf && resrv_buf->daddr) {

• struct device *real_dev = resrv_buf->dev->parent;
  

• dma_unmap_resource(real_dev, resrv_buf->daddr,
  

• 		resrv_buf->size, DMA_FROM_DEVICE, 0);
  

• }
• kfree(resrv_buf);

+}

+static void tmc_etr_sync_resrv_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp) +{

• /*

• * Adjust the buffer to point to the beginning of the trace data
  

• * and update the available trace data.
  

• */
  

• etr_buf->offset = rrp - etr_buf->hwaddr;
• if (etr_buf->full)

• etr_buf->len = etr_buf->size;
  

• else

• etr_buf->len = rwp - rrp;
  

Don't we need to sync the buffer for CPU via dma_sync_single_for_cpu() ? Otherwise, we could be reading stale data ?

+}

+static const struct etr_buf_operations etr_resrv_buf_ops = {

• .alloc = tmc_etr_alloc_resrv_buf,
• .free = tmc_etr_free_resrv_buf,
• .sync = tmc_etr_sync_resrv_buf,
• .get_data = tmc_etr_get_data_flat_buf,

+};

• /*
  • tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters
  • appropriately.

@@ -800,6 +869,7 @@ static const struct etr_buf_operations *etr_buf_ops[] = { [ETR_MODE_FLAT] = &etr_flat_buf_ops, [ETR_MODE_ETR_SG] = &etr_sg_buf_ops, [ETR_MODE_CATU] = NULL,

• [ETR_MODE_RESRV] = &etr_resrv_buf_ops };

void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu) @@ -825,6 +895,7 @@ static inline int tmc_etr_mode_alloc_buf(int mode, case ETR_MODE_FLAT: case ETR_MODE_ETR_SG: case ETR_MODE_CATU:

• case ETR_MODE_RESRV: if (etr_buf_ops[mode] && etr_buf_ops[mode]->alloc) rc = etr_buf_ops[mode]->alloc(drvdata, etr_buf, node, pages);

@@ -843,6 +914,7 @@ static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw) buf_hw->has_iommu = iommu_get_domain_for_dev(dev->parent); buf_hw->has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG); buf_hw->has_catu = !!tmc_etr_get_catu_device(drvdata);

• buf_hw->has_resrv = is_tmc_reserved_region_valid(dev->parent); }

static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_buf_size) @@ -874,13 +946,19 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, if (!etr_buf) return ERR_PTR(-ENOMEM);

• etr_buf->size = size;

• /* Overiride the buffer size here for reserved mode */

minor nit: "Override"

• etr_buf->size = (drvdata->etr_mode == ETR_MODE_RESRV) ?

• drvdata->crash_tbuf.size : size;
  

Isn't it better to do this from the actual code where we are successful in allocating the buffer ? That way, it works for the AUTO mode too ?

/* If there is user directive for buffer mode, try that first */ if (drvdata->etr_mode != ETR_MODE_AUTO) rc = tmc_etr_mode_alloc_buf(drvdata->etr_mode, drvdata, etr_buf, node, pages);

• /* Fallback mechanism is not valid for reserved mode */
• if (rc && (drvdata->etr_mode == ETR_MODE_RESRV))

• goto done;
  

• /*
  • If we have to use an existing list of pages, we cannot reliably
  • use a contiguous DMA memory (even if we have an IOMMU). Otherwise,

@@ -902,6 +980,7 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, if (rc && buf_hw.has_catu) rc = tmc_etr_mode_alloc_buf(ETR_MODE_CATU, drvdata, etr_buf, node, pages); +done: if (rc) { kfree(etr_buf); return ERR_PTR(rc); @@ -1829,6 +1908,7 @@ static const char *const buf_modes_str[] = { [ETR_MODE_FLAT] = "flat", [ETR_MODE_ETR_SG] = "tmc-sg", [ETR_MODE_CATU] = "catu",

• [ETR_MODE_RESRV] = "resrv", [ETR_MODE_AUTO] = "auto", };

@@ -1847,6 +1927,9 @@ static ssize_t buf_modes_available_show(struct device *dev, if (buf_hw.has_catu) size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]);

• if (buf_hw.has_resrv)

• size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_RESRV]);
  

• size += sysfs_emit_at(buf, size, "\n"); return size; }

@@ -1874,6 +1957,8 @@ static ssize_t buf_mode_preferred_store(struct device *dev, drvdata->etr_mode = ETR_MODE_ETR_SG; else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) && buf_hw.has_catu) drvdata->etr_mode = ETR_MODE_CATU;

• else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_RESRV]) && buf_hw.has_resrv)

• drvdata->etr_mode = ETR_MODE_RESRV;
  

  else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO])) drvdata->etr_mode = ETR_MODE_AUTO; else

diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 8dcb426ac3e7..10dba9f7d76a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -135,6 +135,7 @@ enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ ETR_MODE_CATU, /* Use SG mechanism in CATU */

• ETR_MODE_RESRV, /* Use reserved region contiguous buffer */ ETR_MODE_AUTO, /* Use the default mechanism */ };

@@ -164,6 +165,17 @@ struct etr_buf { void *private; }; +/**

• • @paddr : Start address of reserved memory region.
• • @vaddr : Corresponding CPU virtual address.
• • @size : Size of reserved memory region.
• */

+struct tmc_resrv_buf {

• phys_addr_t paddr;
• void *vaddr;
• size_t size;

+};

• /**
  • struct tmc_drvdata - specifics associated to an TMC component
  • @base: memory mapped base address for this component.

@@ -188,6 +200,10 @@ struct etr_buf {

• @idr_mutex: Access serialisation for idr.
• @sysfs_buf: SYSFS buffer for ETR.
• @perf_buf: PERF buffer for ETR.

• • @crash_tbuf: Used by ETR as hardware trace buffer and for trace data

• • retention (after crash) only when ETR_MODE_RESRV buffer
    

• • mode is enabled. Used by ETF for trace data retention
    

• • (after crash) by default.
    

minor nit: Please align the comment like the other fields.

Suzuki

*/ struct tmc_drvdata { void __iomem *base; @@ -213,6 +229,7 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf;

• struct tmc_resrv_buf crash_tbuf; };

struct etr_buf_operations { @@ -330,6 +347,16 @@ tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT; } +static inline bool is_tmc_reserved_region_valid(struct device *dev) +{

• struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
• if (drvdata->crash_tbuf.paddr &&

• drvdata->crash_tbuf.size)
  

• return true;
  

• return false;

+}

• struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);

void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);

Hi Suzuki,

-----Original Message----- From: Suzuki K Poulose suzuki.poulose@arm.com Sent: Tuesday, January 9, 2024 4:22 PM To: Linu Cherian lcherian@marvell.com; mike.leach@linaro.org; james.clark@arm.com; leo.yan@linaro.org Cc: linux-arm-kernel@lists.infradead.org; coresight@lists.linaro.org; linux- kernel@vger.kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; devicetree@vger.kernel.org; Sunil Kovvuri Goutham sgoutham@marvell.com; George Cherian gcherian@marvell.com; Anil Kumar Reddy H areddy3@marvell.com; Tanmay Jagdale tanmay@marvell.com Subject: [EXT] Re: [PATCH v6 5/7] coresight: tmc: Add support for reading tracedata from previous boot

External Email

---

Hi

On 05/01/2024 05:58, Linu Cherian wrote:

...

• Introduce a new mode CS_MODE_READ_PREVBOOT for reading

tracedata

...

captured in previous boot.

• Add special handlers for preparing ETR/ETF for this special mode

• User can read the trace data as below

  For example, for reading trace data from tmc_etf sink

  1. cd /sys/bus/coresight/devices/tmc_etfXX/

  2. Change mode to READ_PREVBOOT

     #echo 1 > read_prevboot

I do not like this "new mode" just for reading the crash trace. We are in the crash kernel when we have trace metadata available. Could we not simply expose this via /dev/tmc_xxx. We can certainly figure this out if we are in a crashkernel or not and the trace metadata is valid. Also, we should wipe out the trace data/metadata on a normal boot or after the crashkernel captures the data.

Somehow couldn’t get the intention behind wiping the tracedata/metadata after retrieval OR its just enough to add a provision to the user for wiping it. Can you please clarify.

We don't expect the user to do tracing in

the crashkernel, even if the user does it, it is upto the user to overwrite the trace. We could even expose a different file for the crash trace/metadata (say /dev/tmc_xxx_crash).

But please do not bloat the existing sysfs interface.

Since we intend to support the watchdog case as well, we cannot restrict reading the tracedata only from the crashdump kernel. In that regard, using a separate file /dev/tmc_xxx_crash looks better and cleaner option to me.

Suzuki

...

3. Dump trace buffer data to a file,

   #dd if=/dev/tmc_etfXX of=~/cstrace.bin

4. Reset back to normal mode

   #echo 0 > read_prevboot

Signed-off-by: Anil Kumar Reddy areddy3@marvell.com Signed-off-by: Tanmay Jagdale tanmay@marvell.com Signed-off-by: Linu Cherian lcherian@marvell.com

---

Changelog from v5:

• Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP in

tmc_etr_setup_prevboot_buf

...

and tmc_etb_setup_prevboot_buf

• Kmalloc invoked with spinlock taken is now done with GFP_ATOMIC
• Removed the requirement for memremap with spinlock taken. This is by making a assumption that the trace buffer address used for capturing trace data during kernel crash/hang would be same as that used for trace data retrieval in the subsequent boot. Added additional verification to ensure this.

• Fixed a memory leak in tmc_read_unprepare_etr in READ_PREVBOOT

mode

...

.../coresight/coresight-etm4x-core.c | 1 + .../hwtracing/coresight/coresight-tmc-core.c | 96 ++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 73 +++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 154 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 6 + include/linux/coresight.h | 13 ++ 6 files changed, 341 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 34aee59dd147..c26b5f72a494 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1010,6 +1010,7 @@ static void etm4_disable(struct coresight_device *csdev,

switch (mode) { case CS_MODE_DISABLED:

• case CS_MODE_READ_PREVBOOT: break; case CS_MODE_SYSFS: etm4_disable_sysfs(csdev);

diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 4d7530d6ac91..e6525c3dcf66 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -103,6 +103,60 @@ u32 tmc_get_memwidth_mask(struct

tmc_drvdata *drvdata)

...

return mask; }

+int tmc_read_prepare_prevboot(struct tmc_drvdata *drvdata) {

• int ret = 0;
• struct tmc_crash_metadata *mdata;
• struct coresight_device *csdev = drvdata->csdev;
• if (!drvdata->crash_mdata.vaddr) {

• ret = -ENOMEM;
  

• goto out;
  

• }
• mdata = drvdata->crash_mdata.vaddr;
• /* Check data integrity of metadata */
• if (mdata->crc32_mdata != find_crash_metadata_crc(mdata)) {

• dev_dbg(&drvdata->csdev->dev,
  

• 	"CRC mismatch in tmc crash metadata\n");
  

• ret = -EINVAL;
  

• goto out;
  

• }
• /* Check data integrity of tracedata */
• if (mdata->crc32_tdata != find_crash_tracedata_crc(drvdata, mdata))

{

...

• dev_dbg(&drvdata->csdev->dev,
  

• 	"CRC mismatch in tmc crash tracedata\n");
  

• ret = -EINVAL;
  

• goto out;
  

• }
• /* Check for valid metadata */
• if (!mdata->valid) {

• dev_dbg(&drvdata->csdev->dev,
  

• 	"Data invalid in tmc crash metadata\n");
  

• ret = -EINVAL;
  

• goto out;
  

• }
• /* Sink specific prevboot mode preparation */
• ret = prevboot_ops(csdev)->prepare(csdev);
• if (ret)

• goto out;
  

• if (mdata->sts & 0x1)

• coresight_insert_barrier_packet(drvdata->buf);
  

+out:

• return ret;

+}

+int tmc_read_unprepare_prevboot(struct tmc_drvdata *drvdata) {

• struct coresight_device *csdev = drvdata->csdev;
• /* Sink specific prevboot mode preparation */
• return prevboot_ops(csdev)->unprepare(csdev);

+}

• static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret = 0;

@@ -153,6 +207,10 @@ static int tmc_open(struct inode *inode, struct file

*file)

...

struct tmc_drvdata *drvdata = container_of(file->private_data, struct tmc_drvdata,

miscdev);

...

• /* Advertise if we are opening with a special mode */
• if (drvdata->mode == CS_MODE_READ_PREVBOOT)

• dev_dbg(&drvdata->csdev->dev, "TMC read mode for
  

previous boot\n");

...

• ret = tmc_read_prepare(drvdata); if (ret) return ret;

@@ -331,9 +389,44 @@ static ssize_t buffer_size_store(struct device *dev,

static DEVICE_ATTR_RW(buffer_size);

+static ssize_t read_prevboot_show(struct device *dev,

• 		struct device_attribute *attr, char *buf) {
  

• struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sprintf(buf, "%#x\n", (drvdata->mode ==

+CS_MODE_READ_PREVBOOT)); }

+static ssize_t read_prevboot_store(struct device *dev,

• 		 struct device_attribute *attr,
  

• 		 const char *buf, size_t size)
  

+{

• int ret;
• unsigned long val, flags;
• struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ret = kstrtoul(buf, 0, &val);
• if (ret)

• return ret;
  

• spin_lock_irqsave(&drvdata->spinlock, flags);
• if (val && (drvdata->mode == CS_MODE_DISABLED))

• drvdata->mode = CS_MODE_READ_PREVBOOT;
  

• else if (!val && (drvdata->mode == CS_MODE_READ_PREVBOOT))

• drvdata->mode = CS_MODE_DISABLED;
  

• spin_unlock_irqrestore(&drvdata->spinlock, flags);
• return size;

+}

+static DEVICE_ATTR_RW(read_prevboot);

• static struct attribute *coresight_tmc_attrs[] = { &dev_attr_trigger_cntr.attr, &dev_attr_buffer_size.attr,
• &dev_attr_read_prevboot.attr, NULL, };

@@ -635,7 +728,8 @@ static void tmc_shutdown(struct amba_device

*adev)

...

spin_lock_irqsave(&drvdata->spinlock, flags);

• if (drvdata->mode == CS_MODE_DISABLED)

• if (drvdata->mode == CS_MODE_DISABLED ||

•    drvdata->mode == CS_MODE_READ_PREVBOOT)
  

  goto out;

  if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) diff --git

a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index b53cef7628ff..72c2315f4e23 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -648,6 +648,56 @@ static int tmc_panic_sync_etf(struct

coresight_device *csdev)

...

return 0; }

+static int tmc_etb_setup_prevboot_buf(struct tmc_drvdata *drvdata) {

• unsigned long size;
• struct tmc_crash_metadata *mdata;
• struct device *dev = &drvdata->csdev->dev;
• mdata = drvdata->crash_mdata.vaddr;
• size = mdata->size << 2;
• /*

• * Buffer address given by metadata for retrieval of trace data
  

• * from previous boot is expected to be same as the reserved
  

• * trace buffer memory region provided through DTS
  

• */
  

• if (is_tmc_reserved_region_valid(dev->parent)

•    && (drvdata->crash_tbuf.paddr == mdata->trc_paddr))
  

• drvdata->buf = drvdata->crash_tbuf.vaddr;
  

• else {

• dev_dbg(dev, "Trace buffer address of previous boot
  

invalid\n");

...

• return -EINVAL;
  

• }
• drvdata->len = size;
• return 0;

+}

+static void tmc_etb_free_prevboot_buf(struct tmc_drvdata *drvdata) {

• void *buf = drvdata->buf;
• if (!buf)

• return;
  

• drvdata->buf = NULL;

+}

+static int tmc_etb_prepare_prevboot(struct coresight_device *csdev) {

• struct tmc_drvdata *drvdata = dev_get_drvdata(csdev-

dev.parent);

• return tmc_etb_setup_prevboot_buf(drvdata);

+}

+static int tmc_etb_unprepare_prevboot(struct coresight_device *csdev) +{

• struct tmc_drvdata *drvdata = dev_get_drvdata(csdev-

dev.parent);

• tmc_etb_free_prevboot_buf(drvdata);
• return 0;

+}

• static const struct coresight_ops_sink tmc_etf_sink_ops = { .enable = tmc_enable_etf_sink, .disable = tmc_disable_etf_sink,

@@ -665,6 +715,11 @@ static const struct coresight_ops_panic

tmc_etf_sync_ops = {

...

.sync = tmc_panic_sync_etf, };

+static const struct coresight_ops_prevboot tmc_etf_prevboot_ops = {

• .prepare = tmc_etb_prepare_prevboot,
• .unprepare = tmc_etb_unprepare_prevboot,

+};

• const struct coresight_ops tmc_etb_cs_ops = { .sink_ops = &tmc_etf_sink_ops, };

@@ -673,6 +728,7 @@ const struct coresight_ops tmc_etf_cs_ops = { .sink_ops = &tmc_etf_sink_ops, .link_ops = &tmc_etf_link_ops, .panic_ops = &tmc_etf_sync_ops,

• .prevboot_ops = &tmc_etf_prevboot_ops, };

  int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) @@ -693,6

+749,14 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) goto out; }

• if (drvdata->mode == CS_MODE_READ_PREVBOOT) {

• ret = tmc_read_prepare_prevboot(drvdata);
  

• if (ret)
  

• 	goto out;
  

• else
  

• 	goto mode_valid;
  

• }
• /* Don't interfere if operated from Perf */ if (drvdata->mode == CS_MODE_PERF) { ret = -EINVAL;

@@ -716,6 +780,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata

*drvdata)

...

__tmc_etb_disable_hw(drvdata);

}

+mode_valid: drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -735,8 +800,16 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) drvdata->config_type != TMC_CONFIG_TYPE_ETF)) return -EINVAL;

• spin_lock_irqsave(&drvdata->spinlock, flags);

• if (drvdata->mode == CS_MODE_READ_PREVBOOT) {

• tmc_read_unprepare_prevboot(drvdata);
  

• drvdata->reading = false;
  

• spin_unlock_irqrestore(&drvdata->spinlock, flags);
  

• return 0;
  

• }

• /* Re-enable the TMC if need be */ if (drvdata->mode == CS_MODE_SYSFS) { /* There is no point in reading a TMC in HW FIFO mode */ diff

--git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 23eb35f50571..ab7521bbb2f5 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1166,7 +1166,12 @@ ssize_t tmc_etr_get_sysfs_trace(struct

tmc_drvdata *drvdata,

...

{ s64 offset; ssize_t actual = len;

• struct etr_buf *etr_buf = drvdata->sysfs_buf;

• struct etr_buf *etr_buf;

• if (drvdata->mode == CS_MODE_READ_PREVBOOT)

• etr_buf = drvdata->prevboot_buf;
  

• else

• etr_buf = drvdata->sysfs_buf;
  
  

  if (pos + actual > etr_buf->len) actual = etr_buf->len - pos;

@@ -1873,6 +1878,130 @@ static int tmc_panic_sync_etr(struct

coresight_device *csdev)

...

return 0; }

+static int tmc_etr_setup_prevboot_buf(struct tmc_drvdata *drvdata) {

• int rc = 0;
• u64 trace_addr;
• struct etr_buf *etr_buf;
• struct etr_flat_buf *resrv_buf;
• struct tmc_crash_metadata *mdata;
• struct device *dev = &drvdata->csdev->dev;
• mdata = drvdata->crash_mdata.vaddr;
• etr_buf = kzalloc(sizeof(*etr_buf), GFP_ATOMIC);
• if (!etr_buf) {

• rc = -ENOMEM;
  

• goto out;
  

• }
• etr_buf->size = drvdata->crash_tbuf.size;
• resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_ATOMIC);
• if (!resrv_buf) {

• rc = -ENOMEM;
  

• goto rmem_err;
  

• }
• /*

• * Buffer address given by metadata for retrieval of trace data
  

• * from previous boot is expected to be same as the reserved
  

• * trace buffer memory region provided through DTS
  

• */
  

• if (is_tmc_reserved_region_valid(dev->parent)

•    && (drvdata->crash_tbuf.paddr == mdata->trc_paddr))
  

• resrv_buf->vaddr = drvdata->crash_tbuf.vaddr;
  

• else {

• dev_dbg(dev, "Trace buffer address of previous boot
  

invalid\n");

...

• rc = -EINVAL;
  

• goto map_err;
  

• }
• resrv_buf->size = etr_buf->size;
• resrv_buf->dev = &drvdata->csdev->dev;
• etr_buf->hwaddr = trace_addr;
• etr_buf->mode = ETR_MODE_RESRV;
• etr_buf->private = resrv_buf;
• etr_buf->ops = etr_buf_ops[ETR_MODE_RESRV];
• drvdata->prevboot_buf = etr_buf;
• return 0;

+map_err:

• kfree(resrv_buf);

+rmem_err:

• kfree(etr_buf);

+out:

• return rc;

+}

+static int tmc_etr_sync_prevboot_buf(struct tmc_drvdata *drvdata) {

• u32 status;
• u64 rrp, rwp, dba;
• struct tmc_crash_metadata *mdata;
• struct etr_buf *etr_buf = drvdata->prevboot_buf;
• mdata = drvdata->crash_mdata.vaddr;
• rrp = mdata->rrp;
• rwp = mdata->rwp;
• dba = mdata->dba;
• status = mdata->sts;
• etr_buf->full = !!(status & TMC_STS_FULL);
• /* Sync the buffer pointers */
• etr_buf->offset = rrp - dba;
• if (etr_buf->full)

• etr_buf->len = etr_buf->size;
  

• else

• etr_buf->len = rwp - rrp;
  

• /* Additional sanity checks for validating metadata */
• if ((etr_buf->offset > etr_buf->size) ||

•    (etr_buf->len > etr_buf->size)) {
  

• dev_dbg(&drvdata->csdev->dev,
  

• 	"Offset and length invalid in tmc crash metadata\n");
  

• return -EINVAL;
  

• }
• return 0;

+}

+static void tmc_etr_free_prevboot_buf(struct tmc_drvdata *drvdata) {

• struct etr_buf *etr_buf = drvdata->prevboot_buf;
• if (!etr_buf)

• return;
  

• drvdata->prevboot_buf = NULL;

+}

+static int tmc_etr_prepare_prevboot(struct coresight_device *csdev) {

• int ret = 0;
• struct tmc_drvdata *drvdata = dev_get_drvdata(csdev-

dev.parent);

• ret = tmc_etr_setup_prevboot_buf(drvdata);
• if (ret)

• goto out;
  

• ret = tmc_etr_sync_prevboot_buf(drvdata);

+out:

• return ret;

+}

+static int tmc_etr_unprepare_prevboot(struct coresight_device *csdev) +{

• struct tmc_drvdata *drvdata = dev_get_drvdata(csdev-

dev.parent);

• tmc_etr_free_prevboot_buf(drvdata);
• return 0;

+}

• static const struct coresight_ops_sink tmc_etr_sink_ops = { .enable = tmc_enable_etr_sink, .disable = tmc_disable_etr_sink,

@@ -1885,9 +2014,15 @@ static const struct coresight_ops_panic

tmc_etr_sync_ops = {

...

.sync = tmc_panic_sync_etr, };

+static const struct coresight_ops_prevboot tmc_etr_prevboot_ops = {

• .prepare = tmc_etr_prepare_prevboot,
• .unprepare = tmc_etr_unprepare_prevboot,

+};

• const struct coresight_ops tmc_etr_cs_ops = { .sink_ops = &tmc_etr_sink_ops, .panic_ops = &tmc_etr_sync_ops,

• .prevboot_ops = &tmc_etr_prevboot_ops, };

  int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) @@ -1899,12

+2034,21 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) if (WARN_ON_ONCE(drvdata->config_type !=

TMC_CONFIG_TYPE_ETR))

...

return -EINVAL;

• spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { ret = -EBUSY; goto out; }

• if (drvdata->mode == CS_MODE_READ_PREVBOOT) {

• ret = tmc_read_prepare_prevboot(drvdata);
  

• if (ret)
  

• 	goto out;
  

• else
  

• 	goto mode_valid;
  

• }

• /*

  • We can safely allow reads even if the ETR is operating in PERF

mode,

...

* since the sysfs session is captured in mode specific data.

@@ -1919,6 +2063,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata

*drvdata)

...

if (drvdata->mode == CS_MODE_SYSFS) __tmc_etr_disable_hw(drvdata);

+mode_valid: drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1937,6 +2082,12 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)

spin_lock_irqsave(&drvdata->spinlock, flags);

• if (drvdata->mode == CS_MODE_READ_PREVBOOT) {

• sysfs_buf = drvdata->prevboot_buf;
  

• tmc_read_unprepare_prevboot(drvdata);
  

• goto out;
  

• }
• /* RE-enable the TMC if need be */ if (drvdata->mode == CS_MODE_SYSFS) { /*

@@ -1954,6 +2105,7 @@ int tmc_read_unprepare_etr(struct tmc_drvdata

*drvdata)

...

drvdata->sysfs_buf = NULL;

}

+out: drvdata->reading = false; spin_unlock_irqrestore(&drvdata->spinlock, flags);

diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 6f13caae6495..6e1e910d5ea4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -216,6 +216,9 @@ struct tmc_resrv_buf {

• @idr_mutex: Access serialisation for idr.
• @sysfs_buf: SYSFS buffer for ETR.
• @perf_buf: PERF buffer for ETR.

• • @prevboot_buf: Previous boot buffer for ETR. This is a special purpose

• • buffer that is used only for mapping the trace buffer from
    

• • previous boot and not for capturing trace.
    

  • @crash_tbuf: Used by ETR as hardware trace buffer and for trace data

  • retention (after crash) only when ETR_MODE_RESRV buffer
    

  • mode is enabled. Used by ETF for trace data retention
    

@@ -247,6 +250,7 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf;

• struct etr_buf *prevboot_buf; struct tmc_resrv_buf crash_tbuf; struct tmc_resrv_buf crash_mdata; };

@@ -298,6 +302,8 @@ void tmc_flush_and_stop(struct tmc_drvdata

*drvdata);

...

void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); +int tmc_read_prepare_prevboot(struct tmc_drvdata *drvdata); int +tmc_read_unprepare_prevboot(struct tmc_drvdata *drvdata);

/* ETB/ETF functions */ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 4fd518738958..9f84decf1d7a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -294,6 +294,7 @@ enum cs_mode { CS_MODE_DISABLED, CS_MODE_SYSFS, CS_MODE_PERF,

• CS_MODE_READ_PREVBOOT, /* Trace data from previous boot */ };

  #define source_ops(csdev) csdev->ops->source_ops

@@ -302,6 +303,7 @@ enum cs_mode { #define helper_ops(csdev) csdev->ops->helper_ops #define ect_ops(csdev) csdev->ops->ect_ops #define panic_ops(csdev) csdev->ops->panic_ops +#define prevboot_ops(csdev) csdev->ops->prevboot_ops

/**

• struct coresight_ops_sink - basic operations for a sink @@

-381,12 +383,23 @@ struct coresight_ops_panic { int (*sync)(struct coresight_device *csdev); };

+/**

• • struct coresight_ops_prevboot - Generic device ops for prevboot

+mode

• • @prepare : Preparation for prevboot mode
• */

+struct coresight_ops_prevboot {

• int (*prepare)(struct coresight_device *csdev);

• int (*unprepare)(struct coresight_device *csdev); };

• struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops; const struct coresight_ops_panic *panic_ops;

• const struct coresight_ops_prevboot *prevboot_ops; };

  #if IS_ENABLED(CONFIG_CORESIGHT)

Hi,

On Fri, 5 Jan 2024 at 05:59, Linu Cherian lcherian@marvell.com wrote:

Configure TMC ETR and ETF to flush and stop trace capture on FlIn event. As a side effect, do manual flush only if auto flush fails.

Signed-off-by: Linu Cherian lcherian@marvell.com

Changelog from v5:

• No changes

drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 3 +++ 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 72c2315f4e23..57a9a9300d36 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -34,7 +34,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |

•                  TMC_FFCR_TRIGON_TRIGIN,
  

•                  TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
                   drvdata->base + TMC_FFCR);
  
  

This is a problem. Setting TMC_FFCR_STOP_ON_FLUSH changes the fundamentals of trigger event handling. Without this bit ETM can generate multiple event + triggers which are then embedded into the formatted trace stream for later search. With this new bit the capture will stop on the first event. Setting this bit should be dependent on the mode being set to ETR_MODE_RESRV

    writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);

@@ -615,7 +615,13 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev) if (val != TMC_MODE_CIRCULAR_BUFFER) goto out;

•   tmc_flush_and_stop(drvdata);
  

•   val = readl(drvdata->base + TMC_FFSR);
  

•   /* Do manual flush and stop only if its not auto-stopped */
  

•   if (!(val & TMC_FFSR_FT_STOPPED)) {
  

•           dev_info(&csdev->dev,
  

•                    "%s: Triggering manual flush\n", __func__);
  

•           tmc_flush_and_stop(drvdata);
  

•   }
  
  

Is there some reason to believe that the stop on flush will not work?

Using this conditional skips the tmc_wait_for_tmcready() called by tmc_flush_and_stop() if the formatter is stopped - which is a different condition test on a different register.

Why is this block of code not in the patch that introduces the tmc_panic_sync_etf()

    /* Sync registers from hardware to metadata region */
    mdata->sts = csdev_access_relaxed_read32(csa, TMC_STS);

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index ab7521bbb2f5..4b3c7ec7f62b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1113,7 +1113,7 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)

    writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
                   TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |

•                  TMC_FFCR_TRIGON_TRIGIN,
  

•                  TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
                   drvdata->base + TMC_FFCR);
    writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
    tmc_enable_hw(drvdata);
  

@@ -1846,7 +1846,13 @@ static int tmc_panic_sync_etr(struct coresight_device *csdev) if (!(val & TMC_CTL_CAPT_EN)) goto out;

•   tmc_flush_and_stop(drvdata);
  

•   val = readl(drvdata->base + TMC_FFSR);
  

•   /* Do manual flush and stop only if its not auto-stopped */
  

•   if (!(val & TMC_FFSR_FT_STOPPED)) {
  

•           dev_info(&csdev->dev,
  

•                    "%s: Triggering manual flush\n", __func__);
  

•           tmc_flush_and_stop(drvdata);
  

•   }
  
  

Above comments for etf apply equally to etr.

Regards

Mike

    /* Sync registers from hardware to metadata region */
    mdata->size = csdev_access_relaxed_read32(csa, TMC_RSZ);

diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 6e1e910d5ea4..cf9313b302c7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -77,6 +77,9 @@ #define TMC_AXICTL_AXCACHE_OS (0xf << 2) #define TMC_AXICTL_ARCACHE_OS (0xf << 16)

+/* TMC_FFSR - 0x300 */ +#define TMC_FFSR_FT_STOPPED BIT(1)

/* TMC_FFCR - 0x304 */ #define TMC_FFCR_FLUSHMAN_BIT 6

#define TMC_FFCR_EN_FMT BIT(0)

2.34.1

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

Hi Mike,

-----Original Message----- From: Mike Leach mike.leach@linaro.org Sent: Friday, January 5, 2024 9:41 PM To: Linu Cherian lcherian@marvell.com Cc: suzuki.poulose@arm.com; james.clark@arm.com; leo.yan@linaro.org; linux-arm-kernel@lists.infradead.org; coresight@lists.linaro.org; linux- kernel@vger.kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; devicetree@vger.kernel.org; Sunil Kovvuri Goutham sgoutham@marvell.com; George Cherian gcherian@marvell.com Subject: [EXT] Re: [PATCH v6 6/7] coresight: tmc: Stop trace capture on FlIn

External Email

---

Hi,

On Fri, 5 Jan 2024 at 05:59, Linu Cherian lcherian@marvell.com wrote:

...

Configure TMC ETR and ETF to flush and stop trace capture on FlIn event. As a side effect, do manual flush only if auto flush fails.

Signed-off-by: Linu Cherian lcherian@marvell.com

Changelog from v5:

• No changes

drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 3 +++ 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 72c2315f4e23..57a9a9300d36 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -34,7 +34,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata

*drvdata)

...

    writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base +

TMC_MODE);

...

    writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
                   TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |

•                  TMC_FFCR_TRIGON_TRIGIN,
  

•                  TMC_FFCR_TRIGON_TRIGIN |
  

• TMC_FFCR_STOP_ON_FLUSH, drvdata->base + TMC_FFCR);

This is a problem. Setting TMC_FFCR_STOP_ON_FLUSH changes the fundamentals of trigger event handling. Without this bit ETM can generate multiple event + triggers which are then embedded into the formatted trace stream for later search. With this new bit the capture will stop on the first event. Setting this bit should be dependent on the mode being set to ETR_MODE_RESRV

Okay, will add a configuration dependency here.

...

    writel_relaxed(drvdata->trigger_cntr, drvdata->base +

TMC_TRG); @@ -615,7 +615,13 @@ static int tmc_panic_sync_etf(struct

coresight_device *csdev)

...

    if (val != TMC_MODE_CIRCULAR_BUFFER)
            goto out;

•   tmc_flush_and_stop(drvdata);
  

•   val = readl(drvdata->base + TMC_FFSR);
  

•   /* Do manual flush and stop only if its not auto-stopped */
  

•   if (!(val & TMC_FFSR_FT_STOPPED)) {
  

•           dev_info(&csdev->dev,
  

•                    "%s: Triggering manual flush\n", __func__);
  

•           tmc_flush_and_stop(drvdata);
  

•   }
  
  

Is there some reason to believe that the stop on flush will not work?

CTI misconfiguration or even skipping the CTI configuration could be the reasons.

Using this conditional skips the tmc_wait_for_tmcready() called by tmc_flush_and_stop() if the formatter is stopped - which is a different condition test on a different register.

Okay got it. While add a tmc_wait_for_tmcready() for the event based flush as well.

Why is this block of code not in the patch that introduces the tmc_panic_sync_etf()

Ack. Will merge the above block of code alone to the patch that introduces tmc_panic_sync_xxx

...

    /* Sync registers from hardware to metadata region */
    mdata->sts = csdev_access_relaxed_read32(csa, TMC_STS); diff

--git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index ab7521bbb2f5..4b3c7ec7f62b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1113,7 +1113,7 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)

    writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
                   TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |

•                  TMC_FFCR_TRIGON_TRIGIN,
  

•                  TMC_FFCR_TRIGON_TRIGIN |
  

• TMC_FFCR_STOP_ON_FLUSH, drvdata->base + TMC_FFCR); writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata);

@@ -1846,7 +1846,13 @@ static int tmc_panic_sync_etr(struct

coresight_device *csdev)

...

    if (!(val & TMC_CTL_CAPT_EN))
            goto out;

•   tmc_flush_and_stop(drvdata);
  

•   val = readl(drvdata->base + TMC_FFSR);
  

•   /* Do manual flush and stop only if its not auto-stopped */
  

•   if (!(val & TMC_FFSR_FT_STOPPED)) {
  

•           dev_info(&csdev->dev,
  

•                    "%s: Triggering manual flush\n", __func__);
  

•           tmc_flush_and_stop(drvdata);
  

•   }
  
  

Above comments for etf apply equally to etr.

Ack.

Linu Cherian

On 05/01/2024 05:58, Linu Cherian wrote:

Add a preloaded configuration for generating external trigger on address match. This can be used by CTI and ETR blocks to stop trace capture on kernel panic.

Kernel address for panic function to be programmed as below.

$cd /config/cs-syscfg/features/gen_etrig/params $echo <panic_address> > address/value

Signed-off-by: Linu Cherian lcherian@marvell.com

Changelog from v5:

• No changes

  drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++++++++++++++++ 4 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c

diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 995d3b2c76df..68b15c8d9462 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \

• coresight-cfg-preload.o coresight-cfg-afdo.o \
  

• coresight-cfg-preload.o coresight-cfg-afdo.o coresight-cfg-pstop.o \
  

  coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \

diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.c b/drivers/hwtracing/coresight/coresight-cfg-preload.c index e237a4edfa09..4980e68483c5 100644 --- a/drivers/hwtracing/coresight/coresight-cfg-preload.c +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.c @@ -13,6 +13,7 @@ static struct cscfg_feature_desc *preload_feats[] = { #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) &strobe_etm4x,

• &gen_etrig_etm4x, #endif NULL };

@@ -20,6 +21,7 @@ static struct cscfg_feature_desc *preload_feats[] = { static struct cscfg_config_desc *preload_cfgs[] = { #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) &afdo_etm4x,

• &pstop_etm4x, #endif NULL };

diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.h b/drivers/hwtracing/coresight/coresight-cfg-preload.h index 21299e175477..291ba530a6a5 100644 --- a/drivers/hwtracing/coresight/coresight-cfg-preload.h +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.h @@ -10,4 +10,6 @@ #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) extern struct cscfg_feature_desc strobe_etm4x; extern struct cscfg_config_desc afdo_etm4x; +extern struct cscfg_feature_desc gen_etrig_etm4x; +extern struct cscfg_config_desc pstop_etm4x; #endif diff --git a/drivers/hwtracing/coresight/coresight-cfg-pstop.c b/drivers/hwtracing/coresight/coresight-cfg-pstop.c new file mode 100644 index 000000000000..037d6773fab8 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cfg-pstop.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright(C) 2023 Marvell.
• • Based on coresight-cfg-afdo.c
• */

+#include "coresight-config.h"

+/* ETMv4 includes and features */ +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) +#include "coresight-etm4x-cfg.h"

+/* preload configurations and features */

+/* preload in features for ETMv4 */

+/* panic_stop feature */ +static struct cscfg_parameter_desc gen_etrig_params[] = {

• {

• .name = "address",
  

• .value = 0x0,
  

• },

+};

+static struct cscfg_regval_desc gen_etrig_regs[] = {

• /* resource selector */
• {

• .type = CS_CFG_REG_TYPE_RESOURCE,
  

• .offset = TRCRSCTLRn(2),
  

• .hw_info = ETM4_CFG_RES_SEL,
  

• .val32 = 0x40001,
  

• },
• /* single address comparator */
• {

• .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_64BIT |
  

• 	CS_CFG_REG_TYPE_VAL_PARAM,
  

• .offset =  TRCACVRn(0),
  

• .val32 = 0x0,
  

• },
• {

• .type = CS_CFG_REG_TYPE_RESOURCE,
  

• .offset = TRCACATRn(0),
  

• .val64 = 0xf00,
  

• },
• /* Driver external output[0] with comparator out */
• {

• .type = CS_CFG_REG_TYPE_RESOURCE,
  

• .offset = TRCEVENTCTL0R,
  

• .val32 = 0x2,
  

• },
• /* end of regs */

+};

+struct cscfg_feature_desc gen_etrig_etm4x = {

• .name = "gen_etrig",
• .description = "Generate external trigger on address match\n"

•        "parameter \'address\': address of kernel address\n",
  

• .match_flags = CS_CFG_MATCH_CLASS_SRC_ETM4,
• .nr_params = ARRAY_SIZE(gen_etrig_params),
• .params_desc = gen_etrig_params,
• .nr_regs = ARRAY_SIZE(gen_etrig_regs),
• .regs_desc = gen_etrig_regs,

+};

+/* create a panic stop configuration */

+/* the total number of parameters in used features */ +#define PSTOP_NR_PARAMS ARRAY_SIZE(gen_etrig_params)

+static const char *pstop_ref_names[] = {

• "gen_etrig",

+};

+struct cscfg_config_desc pstop_etm4x = {

• .name = "panicstop",
• .description = "Stop ETM on kernel panic\n",

Since this is actually generic, i.e., Stop trace on a Kernel address, we could rename this ? Or why don't we pre-populate the address of "panic" at load time. That way the user doesn't have to figure out the kernel address (e.g., if KASLR is enabled)

Suzuki

• .nr_feat_refs = ARRAY_SIZE(pstop_ref_names),
• .feat_ref_names = pstop_ref_names,
• .nr_total_params = PSTOP_NR_PARAMS,

+};

+/* end of ETM4x configurations */ +#endif /* IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) */