New subject: 答复: 答复: 答复: 答复: [PATCH] sctrl: coresight test: opening the sctrl atb clock gating

17 Mar 2017

Hello,
On 17 March 2017 at 03:19, lipengcheng (C) lipengcheng8@huawei.com wrote:
...
Hi Leo and Mathieu.
Please help to verify the accuracy of the data,thank you very much
By accuracy you mean decode the data snapshot you included below?
Unfortunately that is not possible without using the openCSD library,
something that is currently working with the coresight/perf integration.
If you give me a base tree where the dts patch applies, I will be happy to
test the solution.
Thanks,
Mathieu
...
For the detail, you can follow the next test step
1、  Merge coresight dts patch.
2、enable etr or etf。
echo '1'>/sys/bus/coresight/devices/f6404000.etr/enable_sink
or
echo '1'>/sys/bus/coresight/devices/f6402000.etf/enable_sink
3、  enable cpu etm：
example cpu0 etm4x: echo '1'>/sys/bus/coresight/
devices/f659c000.etm/enable_source
4、cd dev
dd if=./f6402000.etf of=/tmp/etf
or
dd if=./f6404000.etr of=/tmp/etr
...
5、etf or etr data：
[image: cid:image001.png@01D29F40.B5B27320]
李鹏程
华为技术有限公司 Huawei Technologies Co., Ltd.
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*发件人:* lipengcheng (C)
*发送时间:* 2017年3月17日 12:13
*收件人:* 'Guodong Xu' guodong.xu@linaro.org; Leo Yan leo.yan@linaro.org
*抄送:* Suzhuangluan suzhuangluan@hisilicon.com
*主题:* 答复: 答复: 答复: [PATCH] sctrl: coresight test: opening the sctrl atb
clock gating
Hi Guodong，
[image: cid:image003.png@01D29F40.B5B27320]
我这边测试单独enable etm 是报building pach 异常，感觉是通路不通。。还是要先将软件流程调通。

  clk240mhz: clk240mhz {



                              #clock-cells = <0>;



                              compatible = "fixed-clock";



                              clock-frequency = <200000000>;



  };








时钟应用上面的：

  etr@0,f6404000 {



           compatible = "arm,coresight-tmc", "arm,primecell";



           reg = <0 0xf6404000 0 0x1000>;




           coresight-default-sink;



           clocks = <&clk240mhz>;



           clock-names = "apb_pclk";



           port {



                     etr_in_port: endpoint@0 {



                              slave-mode;



                              remote-endpoint =



<&replicator_out_port0>;

                     };



           };




  };








李鹏程
华为技术有限公司 Huawei Technologies Co., Ltd.
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*发件人:* Guodong Xu [mailto:guodong.xu@linaro.org guodong.xu@linaro.org]
*发送时间:* 2017年3月17日 11:36
*收件人:* Leo Yan leo.yan@linaro.org
*抄送:* lipengcheng (C) lipengcheng8@huawei.com; Suzhuangluan <
suzhuangluan@hisilicon.com>
*主题:* Re: 答复: 答复: [PATCH] sctrl: coresight test: opening the sctrl atb
clock gating
李鹏程,
赞同Leo建议的方式. 你这边应该有hikey吧? 直接把主线代码抓下来编译调试. 这也是Mathieu的环境, 遇到问题大家基准相同好交流.
-国栋
2017-03-16 21:48 GMT+08:00 Leo Yan leo.yan@linaro.org:
我和Mathieu讨论过一些，他认为ETB/ETF这一块应该是没有问题的，但是怀疑是ETM这一块没有数据出来。我对coresight
不是特别了解，前面在两个板子上做了些实验，DB410c和Hikey。DB410c上比较快就能够enable起来，所以我这边后来就没有花太多的时间在
Hikey上。这是当前的状态。
主要的问题是我们主要在主线kernel上开发，而主线版本上看起来可能时钟还是有些问题。我和Mathieu都
认为比较有效率的方式是，海思同事是否能够直接在HIkey上验证内核主线版本，我的理解是最简便的方式是可以在主线内核启动之后，
依赖于内核的里面驱动去使能时钟，然后使用调试器（trace32）抓取ETB里面的内容，如果解析里面的跳转指令，
就代表硬件的逻辑是可以正常工作的，否则硬件逻辑没有工作。
比较复杂的调试方法就是使用Perf+OpenCSD进行调试，这个会增加调试难度的地方就是还需要了解perf+OpenCSD里面的机制。
On 16 March 2017 at 20:39, lipengcheng (C) lipengcheng8@huawei.com
wrote:
合入后，是那部分有问题，现在coresight 代码变化比较大。
我这里要看话，会花费很多时间，能不能看看是啥问题？我负责支持解决问题，是否ok？
李鹏程
华为技术有限公司 Huawei Technologies Co., Ltd.
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is intended only for the person or entity whose address is listed above.
Any use of the
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*发件人**:* Guodong Xu [mailto:guodong.xu@linaro.org]
*发送时间**:* 2017年3月16日 17:16
*收件人**:* lipengcheng (C) lipengcheng8@huawei.com
*抄送**:* Leo Yan leo.yan@linaro.org; Suzhuangluan <
suzhuangluan@hisilicon.com>
*主题**:* Re: 答复: [PATCH] sctrl: coresight test: opening the sctrl atb
clock gating
On 16 March 2017 at 17:06, lipengcheng (C) lipengcheng8@huawei.com
wrote:
Hi guodong and leo，
最新调试是否还有问题？
之前mathieu反馈时钟有问题，合入这个patch 时钟是否解决了？
合入后, 仍没有解决.
-国栋
李鹏程
华为技术有限公司 Huawei Technologies Co., Ltd.
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*发件人**:* lipengcheng (C)
*发送时间**:* 2017年3月14日 20:11
*收件人**:* 'Leo Yan' leo.yan@linaro.org
*抄送**:* Suzhuangluan suzhuangluan@hisilicon.com
*主题**:* 答复: [PATCH] sctrl: coresight test: opening the sctrl atb clock
gating
meot@linaro-developer:~# ./perf record -e cs_etm/@f6404000.etr/
--per-thread una
failed to mmap with 12 (Cannot allocate memory)
这个是没有申请到memory ，不是之前时钟不可用的问题。单独测试etm4x，是否有问题。
李鹏程
华为技术有限公司 Huawei Technologies Co., Ltd.
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 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
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*发件人**:* Leo Yan [mailto:leo.yan@linaro.org leo.yan@linaro.org]
*发送时间**:* 2017年3月7日 16:18
*收件人**:* lipengcheng (C) lipengcheng8@huawei.com
*抄送**:* Guodong Xu guodong.xu@linaro.org; Mathieu Poirier <
mathieu.poirier@linaro.org>; Liuyongfu liuyongfu@hisilicon.com; Dan
zhao dan.zhao@hisilicon.com; Suzhuangluan suzhuangluan@hisilicon.com
*主题**:* Re: [PATCH] sctrl: coresight test: opening the sctrl atb clock
gating
Hi Pengcheng,
I tried your patch with perf command, I still can see the failure:
[    1.424133] hi6220_sysconf:before sctrl ACPU_SC_CLK_STAT is 17fd
[    1.424138] hi6220_sysconf:after sctrl ACPU_SC_CLK_STAT is 1ffd
meot@linaro-developer:~# ./perf record -e cs_etm/@f6404000.etr/
--per-thread una
failed to mmap with 12 (Cannot allocate memory)
On 6 March 2017 at 17:20, Li Pengcheng lipengcheng8@huawei.com wrote:
opening the sctrl ACPU_SC_CLKEN register 11 bit atb clock gating.
Signed-off-by: Li Pengcheng lipengcheng8@huawei.com
drivers/misc/Makefile           |  1 +
 drivers/misc/hi6220-sysconfig.c | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 drivers/misc/hi6220-sysconfig.c

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3198336..8bf83fe 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_ECHO)            += echo/
 obj-$(CONFIG_VEXPRESS_SYSCFG)  += vexpress-syscfg.o
 obj-$(CONFIG_CXL_BASE)         += cxl/
 obj-$(CONFIG_PANEL)             += panel.o
+obj-y                          += hi6220-sysconfig.o
lkdtm-$(CONFIG_LKDTM)          += lkdtm_core.o
 lkdtm-$(CONFIG_LKDTM)          += lkdtm_bugs.o
diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-
sysconfig.c
new file mode 100644
index 0000000..c61bfbb
--- /dev/null
+++ b/drivers/misc/hi6220-sysconfig.c
@@ -0,0 +1,29 @@
+#include <linux/io.h>



+#define SOC_HI6220_ACPU_SCTRL_BASE_ADDR 0xF6504000
+#define ACPU_SC_CLKEN 0x00C
+#define ACPU_SC_CLK_STAT 0x014



+static int __init hi6220_sysconf(void)
+{

   static void __iomem *base = NULL;



  base = ioremap(SOC_HI6220_ACPU_SCTRL_BASE_ADDR, SZ_4K);


  if (base == NULL) {


          pr_err("hi6220: asctl reg iomap failed!\n");


          return -ENOMEM;


  }


  /* enable coresight */


  pr_err("%s:before sctrl ACPU_SC_CLK_STAT is %x\n",


           __func__,


           readl(base + ACPU_SC_CLK_STAT));


  writel(BIT(11), base + ACPU_SC_CLKEN);


  pr_err("%s:after sctrl ACPU_SC_CLK_STAT is %x\n",


          __func__,


          readl(base + ACPU_SC_CLK_STAT));



  iounmap(base);



   return 0;


}
postcore_initcall(hi6220_sysconf);

--
2.1.0

    

Re: 答复: 答复: 答复: [PATCH] sctrl: coresight test: opening the sctrl atb clock gating

李鹏程

李鹏程

李鹏程

李鹏程

李鹏程

Signed-off-by: Li Pengcheng lipengcheng8@huawei.com