Linaro-mm-sig September 2026

linaro-mm-sig@lists.linaro.org

21 participants
56 discussions

[PATCH 0/2] Document the DMA-buf mapping lifetime negotiation

by Leon Romanovsky

DMA-buf lets an exporter pin, move or revoke the backing storage under an importer, and which of the three applies is decided by the optional callbacks each side implements and by whether dma_buf_pin() succeeds. Nothing in Documentation/ describes that, and the single reference to the mechanism still names move_notify(), removed in v7.1. Thanks Signed-off-by: Leon Romanovsky <leonro(a)nvidia.com> --- Leon Romanovsky (2): PCI/P2PDMA: Update DMABUF lifecycle docs after move_notify() rename dma-buf: Document how exporters and importers agree on mapping lifetime Documentation/driver-api/dma-buf.rst | 6 +++ Documentation/driver-api/pci/p2pdma.rst | 6 ++- drivers/dma-buf/dma-buf.c | 85 ++++++++++++++++++++++++++++++++- 3 files changed, 94 insertions(+), 3 deletions(-) --- base-commit: 8049741ac93acd3a590dac070e12571fddf0e294 change-id: 20260820-document-dma-buf-3f8b41e32f57 Best regards, -- Leon Romanovsky <leonro(a)nvidia.com>

3 weeks, 3 days

Re: [PATCH] Documentation/gpu: Fix brackets

by Randy Dunlap

Hi, On 9/3/26 9:10 AM, Manuel Ebner wrote: > Remove needless '(' and add missing ')'. > > Signed-off-by: Manuel Ebner <manuelebnerli(a)mailbox.org> > --- > Documentation/gpu/drm-vm-bind-locking.rst | 2 +- > Documentation/gpu/nova/core/todo.rst | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) This patch probably should be 2 patches since these files have different maintainers. > diff --git a/Documentation/gpu/drm-vm-bind-locking.rst b/Documentation/gpu/drm-vm-bind-locking.rst > index a345aa513..df6cf0132 100644 > --- a/Documentation/gpu/drm-vm-bind-locking.rst > +++ b/Documentation/gpu/drm-vm-bind-locking.rst > @@ -170,7 +170,7 @@ submission is therefore preceded with a re-validation section: > validate_gem_bo(&gpu_vm_bo->gem_bo); > > // The following list iteration needs the Gem object's > - // dma_resv to be held (it protects the gpu_vm_bo's list of > + // dma_resv to be held. It protects the gpu_vm_bo's list of > // gpu_vmas, but since local gem objects share the gpu_vm's > // dma_resv, it is already held at this point. I think that I must like parenthetical phrases more than you do. ;) Acked-by: Randy Dunlap <rdunlap(a)infradead.org> Thanks. > for_each_gpu_vma_of_gpu_vm_bo(&gpu_vm_bo, &gpu_vma) > diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/core/todo.rst > index d5130b2b0..a01c362b1 100644 > --- a/Documentation/gpu/nova/core/todo.rst > +++ b/Documentation/gpu/nova/core/todo.rst > @@ -33,7 +33,7 @@ A good example from nova-core would be the ``Chipset`` enum type, which defines > the value ``AD102``. When probing the GPU the value ``0x192`` can be read from a > certain register indication the chipset AD102. Hence, the enum value ``AD102`` > should be derived from the number ``0x192``. Currently, nova-core uses a custom > -implementation (``Chipset::from_u32`` for this. > +implementation (``Chipset::from_u32``) for this. > > Instead, it would be desirable to have something like the ``FromPrimitive`` > trait [1] from the num crate. -- ~Randy

3 weeks, 4 days

Re: [PATCH v8 2/2] dma-buf: Split sgl by largest page-aligned chunk

by Jason Gunthorpe

On Wed, Sep 02, 2026 at 07:07:50PM -0400, David Hu wrote: > On Wed, Sep 2, 2026 at 8:08 AM Jason Gunthorpe <jgg(a)ziepe.ca> wrote: > > > > On Tue, Sep 01, 2026 at 05:08:49PM +0000, David Hu wrote: > > > From: David Hu <xuehaohu(a)google.com> > > > > > > Currently, `fill_sg_entry()` splits the scatterlist using `UINT_MAX`. > > > This creates a non-page-aligned DMA length (`0xFFFFFFFF`) for the > > > first entry, resulting in non-page-aligned DMA addresses for all > > > subsequent entries. > > > > This patch is fine, but pedenatically a scatterlist's entry limit > > should be bounded to dma_get_max_seg_size(), though I don't think it > > helps this. Operating scatterlists at the size limits has proven > > problematic in a number of places already... > > > > > In addition, a non-page-aligned sgl length will trigger an edge case > > > in `ib_umem_find_best_pgsz()`. In case of a discontinuity in later > > > buffers, we will have a `va` with lowest bit set to 1. That will lead > > > to `ib_umem_find_best_pgsz()` always return 0, and break the promise > > > to find best page size for the mapping on the NIC side. > > > > That's an IB side bug, the newer logic that joins adjacent SGLs should > > have avoided it? > > Hi Jason, > > Thank you for the review. I think you are right on both counts. > Regarding the IB side, the new SGL joining logic in > `ib_umem_find_best_pgsz()` indeed avoids the issue. `mask |= va` is > skipped for artifically split, contiguous SGLs. Since Christian has > already pulled v8 into drm-misc-next, I won't spin a v9 to avoid > creating unnecessary noise on the list. If you prefer a followup, > please let me know. Nope, I'm fine, it just explains why it wasn't seen in other tested. You were backporting and mix&matched things. It confirms the upstream kernel was fine from the start. There are other importers besides RDMA, so I still think that this is a good change regardless. Having each segment remain page aligned, and staying away from ULONG_MAX that might trigger overflows is a friendly and robust thing to do for less sophisticated importers. Jason

3 weeks, 4 days

Re: [PATCH v8 0/2] dma-buf: Fix silent overflow and alignment

by Christian König

On 9/1/26 19:08, David Hu wrote: > From: David Hu <xuehaohu(a)google.com> > > This series address two related issues in scatter-gather mapping, > specifically for the MMIO based dma-buf mapping. The fixes ensure > sgt mapping is correct, and proper for large MMIO regions. > > Patch 1 fixes a silent integer overflow for mapping length exceeding 4G > (Previously submitted as [PATCH v7] dma-buf: Fix silent overflow for > phys vec to sgt) > https://lore.kernel.org/all/20260609164047.486227-1-xuehaohu@google.com/ > > Patch 2 Splits sgl by largest page aligned chunk > (Previously submitted as [PATCH v3] dma-buf: Split sgl by largest page-aligned chunk) > https://lore.kernel.org/all/20260722233806.3922093-1-dhu@x6u.co/ *sigh* such issues are exactly the reason why I didn't wanted the dma-mapping stuff inside DMA-buf. That clearly doesn't belong here. I'm going to push those fixes to drm-misc-next now, but when there are more issues like that will mark the code as abandoned and not maintained. Regards, Christian. > > Changes in v8: > - Combined the two patches into one unified series to avoid merge > conflicts. > - Collected Reviewed-by tag from Leon Romanovsky for Patch 2. > > David Hu (2): > dma-buf: Fix silent overflow for phys vec to sgt > dma-buf: Split sgl by largest page-aligned chunk > > drivers/dma-buf/dma-buf-mapping.c | 31 +++++++++++++++++++++---------- > 1 file changed, 21 insertions(+), 10 deletions(-) > > -- > 2.55.0.897.gb25b4bd76c-goog >

3 weeks, 5 days

Re: [PATCH v5 4/5] accel/amdxdna: refuse to flush an imported BO

by Lizhi Hou

Applied this to drm-misc-fixes. On 8/19/26 15:44, Taimuraz Kaitmazov wrote: > SYNC_BO clflushes an imported BO's scatterlist. An importer may not do > that: the memory belongs to the exporter, and dma-buf gives the importer > no interface to ask for maintenance on it. Refuse the request instead. > > is_import_bo() is (obj)->attach, which covers more than foreign buffers. > A userptr BO arrives through a ubuf, and on a carveout device every share > BO and the device heap arrive through a cbuf, so SYNC_BO answers > -EOPNOTSUPP for those too, including the AMDXDNA_BO_DEV path that flushes > through its heap. > > Only the ubuf case gives up maintenance it was getting: on a 64 MiB > userptr BO a 4 KiB sync and a full sync both cost 659 us, this arm having > ignored the range. amdxdna_cbuf_map() fills in only the DMA address and > length, so drm_clflush_sg() already walks zero pages on carveout memory. > Userspace maintains these through the mapping it already holds, as XRT's > buffer::sync() does unless it is told to sync through the driver. > > Suggested-by: Lizhi Hou <lizhi.hou(a)amd.com> > Signed-off-by: Taimuraz Kaitmazov <taimuraz(a)kaitmazov.com> > Reviewed-by: Lizhi Hou <lizhi.hou(a)amd.com> > --- > drivers/accel/amdxdna/amdxdna_gem.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c > index 0e0f844526ca..4be5298d1062 100644 > --- a/drivers/accel/amdxdna/amdxdna_gem.c > +++ b/drivers/accel/amdxdna/amdxdna_gem.c > @@ -1224,6 +1224,9 @@ static int amdxdna_flush_bo(struct amdxdna_gem_obj *abo, u64 offset, u64 size) > { > u64 end; > > + if (is_import_bo(abo)) > + return -EOPNOTSUPP; > + > if (offset >= abo->mem.size) > return -EINVAL; > > @@ -1234,9 +1237,7 @@ static int amdxdna_flush_bo(struct amdxdna_gem_obj *abo, u64 offset, u64 size) > if (!size) > return 0; > > - if (is_import_bo(abo)) > - drm_clflush_sg(abo->base.sgt); > - else if (amdxdna_gem_vmap(abo)) > + if (amdxdna_gem_vmap(abo)) > drm_clflush_virt_range(amdxdna_gem_vmap(abo) + offset, size); > else if (abo->base.pages) > drm_clflush_pages(abo->base.pages, abo->mem.size >> PAGE_SHIFT);

3 weeks, 5 days

Re: [PATCH v8 2/2] dma-buf: Split sgl by largest page-aligned chunk

by Jason Gunthorpe

On Tue, Sep 01, 2026 at 05:08:49PM +0000, David Hu wrote: > From: David Hu <xuehaohu(a)google.com> > > Currently, `fill_sg_entry()` splits the scatterlist using `UINT_MAX`. > This creates a non-page-aligned DMA length (`0xFFFFFFFF`) for the > first entry, resulting in non-page-aligned DMA addresses for all > subsequent entries. This patch is fine, but pedenatically a scatterlist's entry limit should be bounded to dma_get_max_seg_size(), though I don't think it helps this. Operating scatterlists at the size limits has proven problematic in a number of places already... > In addition, a non-page-aligned sgl length will trigger an edge case > in `ib_umem_find_best_pgsz()`. In case of a discontinuity in later > buffers, we will have a `va` with lowest bit set to 1. That will lead > to `ib_umem_find_best_pgsz()` always return 0, and break the promise > to find best page size for the mapping on the NIC side. That's an IB side bug, the newer logic that joins adjacent SGLs should have avoided it? Jason

3 weeks, 5 days

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Linaro-mm-sig September 2026