On Thu, Jun 18, 2026 at 05:02:58PM +0100, Matt Evans wrote:
My understanding is that the sequences above wake a device that happens to have previously been put into D3, and AFAICT it could only have got there because of a previous vfio_pci_set_power_state(). Seems its only caller is from the emulation of PCI_PM_CTRL using vfio_lock_and_set_power_state(), and this zaps/revokes BAR access before a transition to D3. Similarly, an attempt to access a BAR via an ioctl/through vfio_pci_core_do_io_rw() fails the D3 check in __vfio_pci_memory_enabled(), and besides will try to take the memory_lock.
I thought the general design was the bars were made inaccessible before going to a low power state, and remain inaccessible while it is in low power?
So the order of D0 doesn't matter. If it is not in D0 then there is no mappings and zap/revoke is a NOP.
If is it in D0 then it doesn't matter because D0 is a nop.
Jason