On 09/10/2024 13:15, Shu-hsiang Yang wrote:

1. Add camera isp7x module device document
2. Add camera interface device document

Signed-off-by: Shu-hsiang Yang Shu-hsiang.Yang@mediatek.com

.../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++ .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++ .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++ .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++ .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++ 5 files changed, 582 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml

diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml new file mode 100644 index 000000000000..c709e4bf0a18 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024 MediaTek Inc.

Drop blank line

+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: The cam-raw unit of MediaTek ISP system

+maintainers:

• • Shu-hsiang Yang shu-hsiang.yang@mediatek.com
• • Shun-yi Wang shun-yi.wang@mediatek.com
• • Teddy Chen teddy.chen@mediatek.com

+description:

• MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.

+properties:

• compatible:
• const: mediatek,cam-raw

SoC specific compatible instead. I see Rob gave you review, so few more points. ...

• assigned-clocks:
• maxItems: 1
• assigned-clock-parents:
• maxItems: 1

Drop assigned-clock*

• iommus:
• description:

•  Points to the respective IOMMU block with master port as argument, see
  

•  Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
  

•  Ports are according to the HW.
  

• minItems: 1
• maxItems: 32

+required:

• • compatible
• • reg
• • reg-names
• • interrupts
• • power-domains
• • clocks
• • clock-names
• • iommus

+additionalProperties: false

+examples:

• • |
• #include <dt-bindings/interrupt-controller/arm-gic.h>
• #include <dt-bindings/interrupt-controller/irq.h>
• #include <dt-bindings/power/mediatek,mt8188-power.h>
• #include <dt-bindings/clock/mediatek,mt8188-clk.h>
• #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
• soc {

•  #address-cells = <2>;
  

•  #size-cells = <2>;
  

•  cam_raw_a@16030000 {
  

Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetre...

e.g. isp

Also, underscores are not allowed in node names. Please do not send to us your downstream code. Read DTS coding style and write code maching upstream style.

•    compatible = "mediatek,cam-raw";
  

•    reg = <0 0x16030000 0 0x8000>,
  

•          <0 0x16038000 0 0x8000>;
  

•    reg-names = "base", "inner_base";
  

•    mediatek,cam-id = <0>;
  

•    mediatek,larbs = <&larb16a>;
  

•    interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
  

•    #address-cells = <2>;
  

•    #size-cells = <2>;
  

•    dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
  

•    power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
  

•    clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
  

•        <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
  

•        <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
  

•        <&camsys CLK_CAM_MAIN_CAM>,
  

•        <&camsys CLK_CAM_MAIN_CAMTG>,
  

•        <&camsys_rawa CLK_CAM_RAWA_LARBX>,
  

•        <&camsys_rawa CLK_CAM_RAWA_CAM>,
  

•        <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
  

•        <&topckgen CLK_TOP_CAM>,
  

•        <&topckgen CLK_TOP_CAMTG>,
  

•        <&topckgen CLK_TOP_CAMTM>;
  

Messed alignment.

•    clock-names = "camsys_cam2mm0_cgpdn",
  

•        "camsys_cam2mm1_cgpdn",
  

•        "camsys_cam2sys_cgpdn",
  

•        "camsys_cam_cgpdn",
  

•        "camsys_camtg_cgpdn",
  

•        "camsys_rawa_larbx_cgpdn",
  

•        "camsys_rawa_cam_cgpdn",
  

•        "camsys_rawa_camtg_cgpdn",
  

•        "topckgen_top_cam",
  

•        "topckgen_top_camtg",
  

•        "topckgen_top_camtm";
  

Also misaligned.

•    assigned-clocks = <&topckgen CLK_TOP_CAM>;
  

•    assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
  

•    iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
  

•        <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
  

Also misaligned.

All comments apply to other files as well.

Best regards, Krzysztof