Hi!

I just want to clarify some buffer object operations and terminology that seems confusing to people and that are used by most modern GPU drivers. I think it's useful to be aware of this, going forward in the memory manager discussions.

Terminology:

Scanout buffer: Buffer that is used for continous access by a device. Needs to be permanently pinned. Pinned buffer: A pinned buffer may not move and may not change backing pages. Allows it to be mapped to a device. Synchronization object: An object that is either in a signaled or non-signaled state. Signaled means that the device is done with the buffer, and has flushed its caches. A synchronization object has a device-specific part that may, for example, contain flushing state.

Basic device use of a buffer:

Scanout buffers (and perhaps also capture buffers?) are typically pinned. Other buffers that are temporarily used by a GPU and, for example, a video decoding engine or image processor are typically *not* pinned. The usage pattern for submitting any commands that affect the buffer is as follows:

1) Take a mutex that stops the buffer from being moved. This mutex could be global (stops all buffers from being moved) or per-buffer. 2) Wait on any previous synchronization objects attached to the buffer, if those sync objects would not be implicitly signaled when the device executes its work. This is where it becomes bad to have a global mutex under 1). 3) Validate the buffer. This means setting up any missing (contigous) device mappings or move to VRAM, flush cpu caches if necessary. 4) Patch up the device commands to reflect any movement of the buffer in 3). New offsets, SG-lists etc. 5) Submit the device commands. 6) Create a new synchronization object and attach it to the buffer. 7) Release the mutex taken i 1).

The buffer will not be moved until the synchronization object has signaled, and mappings set up under 3) will not be torn down until the memory manager receives a request to free up mapping resources.

I'd call this "Generation 2" device buffer management. (Intel (uses busy lists, no sync objects), Radeon, Nouveau, vmwgfx, New VIA) "Generation 1" was using a global memory manager for pinned buffers (SiS, old VIA DRM drivers) Generation 3 would be page based device MMUs with programmable apertures to access VRAM.

What we were discussing today is basically creating a unified gen 1 manager, with a new user-space interface.

/Thomas