CoreSight June 2020

coresight@lists.linaro.org

19 participants
34 discussions

by subhasish Karmakar

Hi All, I am seeing this bug in STM decoder. Where STM decoder is going into an infinite loop and never comes out of it. I have pasted the debug patch and log excerpts for your reference. Read "*Bug Description*" from Step-1 to Step-6 for detailed explanation. Please help me with a fix. *Debug Patch:--------------------------------------*diff --git a/decoder/source/stm/trc_pkt_proc_stm.cpp b/decoder/source/stm/trc_pkt_proc_stm.cpp index b39a053..3bc754f 100644 --- a/decoder/source/stm/trc_pkt_proc_stm.cpp +++ b/decoder/source/stm/trc_pkt_proc_stm.cpp @@ -81,7 +81,10 @@ ocsd_datapath_resp_t TrcPktProcStm::processData( const ocsd_trc_index_t index, m_p_data_in = pDataBlock; m_data_in_size = dataBlockSize; m_data_in_used = 0; - + + printf("while-entry (m_data_in_used[%d] < m_data_in_size[%d]) || m_nibble_2nd_valid[%d] || (m_proc_state[%d] == SEND_PKT)\n", + m_data_in_used,m_data_in_size,m_nibble_2nd_valid,m_proc_state); + // while there is data and a continue response on the data path while( dataToProcess() && OCSD_DATA_RESP_IS_CONT(resp) ) { @@ -141,6 +144,8 @@ ocsd_datapath_resp_t TrcPktProcStm::processData( const ocsd_trc_index_t index, fatal.setMessage("Unknown System Error decoding trace."); LogError(fatal); } + *+ /*** Bug Description Step-4: m_data_in_used = 12 < m_data_in_size = 14, exit condition does not satisfy in processData(). + Control enters into waitForSync() again ***/*+ + printf("while-exit (m_data_in_used[%d] < m_data_in_size[%d]) || m_nibble_2nd_valid[%d] || (m_proc_state[%d] == SEND_PKT)\n", + m_data_in_used,m_data_in_size,m_nibble_2nd_valid,m_proc_state); } *numBytesProcessed = m_data_in_used; @@ -249,9 +254,12 @@ void TrcPktProcStm::waitForSync(const ocsd_trc_index_t blk_st_index) m_bWaitSyncSaveSuppressed = true; // no need to save bytes until we want to send data. *+ /*** Bug Description Step-1: m_data_in_used = 0 and m_data_in_size = 14 for first time entry. ***/+ /*** Bug Description Step-5: m_data_in_used = 12 and m_data_in_size = 14 for second time entry.+ But m_is_sync = TRUE, control does not enter into while loop . readNibble() is not called. ***/*+ + printf("(bGotData[%d] && !m_is_sync[%d])\n", bGotData, m_is_sync); while(bGotData && !m_is_sync) { bGotData = readNibble(); // read until we have a sync or run out of data + *+ /*** Bug Description Step-2: m_data_in_used = 12 and m_is_sync = TRUE, when we have found sync packet. ***/*+ + printf("m_data_in_used[%d], m_nibble_2nd_valid[%d], m_num_nibbles[%d], m_is_sync[%d]\n", + m_data_in_used, m_nibble_2nd_valid, m_num_nibbles, m_is_sync); } m_bWaitSyncSaveSuppressed = false; @@ -272,7 +280,7 @@ void TrcPktProcStm::waitForSync(const ocsd_trc_index_t blk_st_index) { // for a), b), c) send the none sync data then re-enter // if out of data, or sync with some previous data, this is sent as unsynced. - + *+ /*** Bug Description Step-3: m_data_in_used = 12 and m_data_in_size = 14 NOTSYNC packet sent ***/+ /*** Bug Description Step-6: step 3 to 6 creates an infinite loop. ***/*+ + printf("(!bGotData[%d] || m_num_nibbles[%d] > 22)\n", bGotData, m_num_nibbles); m_curr_packet.setPacketType(STM_PKT_NOTSYNC,false); if(mon_in_use.usingMonitor()) { *Log With Debug Patch:------------------------------------------*while-entry (m_data_in_used[0] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[0] == SEND_PKT) (bGotData[1] && !m_is_sync[0]) m_data_in_used[1], m_nibble_2nd_valid[1], m_num_nibbles[1], m_is_sync[0] m_data_in_used[1], m_nibble_2nd_valid[0], m_num_nibbles[2], m_is_sync[0] m_data_in_used[2], m_nibble_2nd_valid[1], m_num_nibbles[3], m_is_sync[0] m_data_in_used[2], m_nibble_2nd_valid[0], m_num_nibbles[4], m_is_sync[0] m_data_in_used[3], m_nibble_2nd_valid[1], m_num_nibbles[5], m_is_sync[0] m_data_in_used[3], m_nibble_2nd_valid[0], m_num_nibbles[6], m_is_sync[0] m_data_in_used[4], m_nibble_2nd_valid[1], m_num_nibbles[7], m_is_sync[0] m_data_in_used[4], m_nibble_2nd_valid[0], m_num_nibbles[8], m_is_sync[0] m_data_in_used[5], m_nibble_2nd_valid[1], m_num_nibbles[9], m_is_sync[0] m_data_in_used[5], m_nibble_2nd_valid[0], m_num_nibbles[10], m_is_sync[0] m_data_in_used[6], m_nibble_2nd_valid[1], m_num_nibbles[11], m_is_sync[0] m_data_in_used[6], m_nibble_2nd_valid[0], m_num_nibbles[12], m_is_sync[0] m_data_in_used[7], m_nibble_2nd_valid[1], m_num_nibbles[13], m_is_sync[0] m_data_in_used[7], m_nibble_2nd_valid[0], m_num_nibbles[14], m_is_sync[0] m_data_in_used[8], m_nibble_2nd_valid[1], m_num_nibbles[15], m_is_sync[0] m_data_in_used[8], m_nibble_2nd_valid[0], m_num_nibbles[16], m_is_sync[0] m_data_in_used[9], m_nibble_2nd_valid[1], m_num_nibbles[17], m_is_sync[0] m_data_in_used[9], m_nibble_2nd_valid[0], m_num_nibbles[18], m_is_sync[0] m_data_in_used[10], m_nibble_2nd_valid[1], m_num_nibbles[19], m_is_sync[0] m_data_in_used[10], m_nibble_2nd_valid[0], m_num_nibbles[20], m_is_sync[0] m_data_in_used[11], m_nibble_2nd_valid[1], m_num_nibbles[21], m_is_sync[0] m_data_in_used[11], m_nibble_2nd_valid[0], m_num_nibbles[22], m_is_sync[0] m_data_in_used[12], m_nibble_2nd_valid[1], m_num_nibbles[23], m_is_sync[0] m_data_in_used[12], m_nibble_2nd_valid[0], m_num_nibbles[24], m_is_sync[1] (!bGotData[1] || m_num_nibbles[24] > 22) while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[3] == SEND_PKT) Idx:0;[ 0xF1 ];NOTSYNC:STM not synchronised while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[0] == SEND_PKT) (bGotData[1] && !m_is_sync[1]) (!bGotData[1] || m_num_nibbles[23] > 22) while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[3] == SEND_PKT) Idx:12;[ 0x0F ];NOTSYNC:STM not synchronised while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[0] == SEND_PKT) (bGotData[1] && !m_is_sync[1]) (!bGotData[1] || m_num_nibbles[23] > 22) while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[3] == SEND_PKT) Idx:12;[ 0x0F ];NOTSYNC:STM not synchronised while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[0] == SEND_PKT) (bGotData[1] && !m_is_sync[1]) (!bGotData[1] || m_num_nibbles[23] > 22) while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[3] == SEND_PKT) Idx:12;[ 0x0F ];NOTSYNC:STM not synchronised while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[0] == SEND_PKT) (bGotData[1] && !m_is_sync[1]) (!bGotData[1] || m_num_nibbles[23] > 22) while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[3] == SEND_PKT) Idx:12;[ 0x0F ];NOTSYNC:STM not synchronised while-exit (m_data_in_used[12] < m_data_in_size[14]) || m_nibble_2nd_valid[0] || (m_proc_state[0] == SEND_PKT) (bGotData[1] && !m_is_sync[1]) (!bGotData[1] || m_num_nibbles[23] > 22) Thank alot for your support, Subhasish

4 years, 4 months

[RFC PATCH 0/3] CoreSight complex config support; ETM strobing.

by Mike Leach

This patchset introduces initial concepts in CoreSight complex configuration support - the device "feature", which is a method of programming the device to perform a specific function. A built-in feature is provided - the ETM strobing function, which programs the ETM to switch trace on and off in a specific mark / space ratio to effectively sample the program being traced. This feature is essential for the Auto-FDO flow using CoreSight trace. Features are declared as a data table, a set of register, resource and parameter requirements. A feature can then be loaded into a device, when the requirements are validated. Once loaded a feature can be enabled for a specific trace run. A feature appears in the sysfs file for the device, as a directory of form 'name.feat', with parameters 'enable', 'description' and any input parameters that may be used to control the operation. For example the ETM strobing feature provided has parameters of 'window' and 'period' to control the sampling mark / space ratio. The representation in sysfs for the ETMv4 is therefore:- etmX/strobing.feat/ /enable /window /period Future developments will introduce resource management, and allow for the runtime loading of additional features, and the setting of features across an entire CoreSight system. Mike Leach (3): coresight: etmv4: Fix resource selector constant. coresight: etmv4: Counter values not saved on disable. coresight: etmv4: Adds initial complex config with ETM4 strobe feature. drivers/hwtracing/coresight/Makefile | 7 +- .../hwtracing/coresight/coresight-config.c | 380 ++++++++++++++++++ .../hwtracing/coresight/coresight-config.h | 156 +++++++ .../hwtracing/coresight/coresight-etm4x-cfg.c | 325 +++++++++++++++ .../hwtracing/coresight/coresight-etm4x-cfg.h | 29 ++ .../coresight/coresight-etm4x-sysfs.c | 3 + drivers/hwtracing/coresight/coresight-etm4x.c | 24 +- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight.c | 1 + include/linux/coresight.h | 2 + 10 files changed, 925 insertions(+), 6 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config.c create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h -- 2.17.1

4 years, 4 months

[PATCH v4] perf test: Introduce script for Arm CoreSight testing

by Leo Yan

We need a simple method to test Perf with Arm CoreSight drivers, this could be used for smoke testing when new patch is coming for perf or CoreSight drivers, and we also can use the test to confirm if the CoreSight has been enabled successfully on new platforms. This patch introduces the shell script test_arm_coresight.sh which is under the 'pert test' framework. This script provides three testing scenarios: Test scenario 1: traverse all possible paths between source and sink For traversing possible paths, simply to say, the testing rationale is source oriented testing, it traverses every source (now only refers to ETM device) and test its all possible sinks. To search the complete paths from one specific source to its sinks, this patch relies on the sysfs '/sys/bus/coresight/devices/devX/out:Y' for depth-first search (DFS) for iteration connected device nodes, if the output device is detected as one of ETR, ETF, or ETB types then it will test trace data recording and decoding for this PMU device. The script runs three output testings for every trace data: - Test branch samples dumping with 'perf script' command; - Test branch samples reporting with 'perf report' command; - Use option '--itrace=i1000i' to insert synthesized instructions events and the script will check if perf can output the percentage value successfully based on the instruction samples. Test scenario 2: CPU wide mode test For CPU wide mode testing, it passes option '-a' to perf tool to enable tracing on all CPUs, so it's hard to say which program will be traced. But perf tool itself contributes much overload in this case, so it will parse trace data and check if process 'perf' can be detected or not. Test scenario 3: snapshot mode test. For snapshot mode testing, it uses 'dd' command to launch a long running program, so this can give chance to send signal -USR2; it will check the captured trace data contains 'dd' related thread info or not. If any test fails, it will report failure and directly exit with error. This test will be only applied on a platform with PMU event 'cs_etm//', otherwise will skip the testing. Below is detailed usage for it: # cd $linux/tools/perf -> This is important so can use shell script # perf test list [...] 65: probe libc's inet_pton & backtrace it with ping 66: Check Arm CoreSight trace data recording and branch samples 67: Check open filename arg using perf trace + vfs_getname 68: Zstd perf.data compression/decompression 69: Add vfs_getname probe to get syscall args filenames 70: Use vfs_getname probe to get syscall args filenames # perf test 66 66: Check Arm CoreSight trace data recording and branch samples: Ok Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/tests/shell/test_arm_coresight.sh | 172 +++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100755 tools/perf/tests/shell/test_arm_coresight.sh diff --git a/tools/perf/tests/shell/test_arm_coresight.sh b/tools/perf/tests/shell/test_arm_coresight.sh new file mode 100755 index 000000000000..73b973bada26 --- /dev/null +++ b/tools/perf/tests/shell/test_arm_coresight.sh @@ -0,0 +1,172 @@ +#!/bin/sh +# Check Arm CoreSight trace data recording and branch samples + +# Uses the 'perf record' to record trace data with Arm CoreSight sinks; +# then verify if there have any branch samples and instruction samples +# are generated by CoreSight with 'perf script' and 'perf report' +# commands. + +# SPDX-License-Identifier: GPL-2.0 +# Leo Yan <leo.yan(a)linaro.org>, 2020 + +perfdata=$(mktemp /tmp/__perf_test.perf.data.XXXXX) +file=$(mktemp /tmp/temporary_file.XXXXX) + +skip_if_no_cs_etm_event() { + perf list | grep -q 'cs_etm//' && return 0 + + # cs_etm event doesn't exist + return 2 +} + +skip_if_no_cs_etm_event || exit 2 + +record_touch_file() { + echo "Recording trace (only user mode) with path: CPU$2 => $1" + perf record -o ${perfdata} -e cs_etm/@$1/u --per-thread \ + -- taskset -c $2 touch $file +} + +perf_script_branch_samples() { + echo "Looking at perf.data file for dumping branch samples:" + + # Below is an example of the branch samples dumping: + # touch 6512 1 branches:u: ffffb220824c strcmp+0xc (/lib/aarch64-linux-gnu/ld-2.27.so) + # touch 6512 1 branches:u: ffffb22082e0 strcmp+0xa0 (/lib/aarch64-linux-gnu/ld-2.27.so) + # touch 6512 1 branches:u: ffffb2208320 strcmp+0xe0 (/lib/aarch64-linux-gnu/ld-2.27.so) + perf script -F,-time -i ${perfdata} | \ + egrep " +$1 +[0-9]+ .* +branches:([u|k]:)? +" +} + +perf_report_branch_samples() { + echo "Looking at perf.data file for reporting branch samples:" + + # Below is an example of the branch samples reporting: + # 73.04% 73.04% touch libc-2.27.so [.] _dl_addr + # 7.71% 7.71% touch libc-2.27.so [.] getenv + # 2.59% 2.59% touch ld-2.27.so [.] strcmp + perf report --stdio -i ${perfdata} | \ + egrep " +[0-9]+\.[0-9]+% +[0-9]+\.[0-9]+% +$1 " +} + +perf_report_instruction_samples() { + echo "Looking at perf.data file for instruction samples:" + + # Below is an example of the instruction samples reporting: + # 68.12% touch libc-2.27.so [.] _dl_addr + # 5.80% touch libc-2.27.so [.] getenv + # 4.35% touch ld-2.27.so [.] _dl_fixup + perf report --itrace=i1000i --stdio -i ${perfdata} | \ + egrep " +[0-9]+\.[0-9]+% +$1" +} + +arm_cs_iterate_devices() { + for dev in $1/connections/out\:*; do + + # Skip testing if it's not a directory + ! [ -d $dev ] && continue; + + # Read out its symbol link file name + path=`readlink -f $dev` + + # Extract device name from path, e.g. + # path = '/sys/devices/platform/20010000.etf/tmc_etf0' + # `> device_name = 'tmc_etf0' + device_name=`echo $path | awk -F/ '{print $(NF)}'` + + echo $device_name | egrep -q "etr|etb|etf" + + # Only test if the output device is ETR/ETB/ETF + if [ $? -eq 0 ]; then + + pmu_dev="/sys/bus/event_source/devices/cs_etm/sinks/$device_name" + + # Exit if PMU device node doesn't exist + if ! [ -f $pmu_dev ]; then + echo "PMU device $pmu_dev doesn't exist" + exit 1 + fi + + record_touch_file $device_name $2 && + perf_script_branch_samples touch && + perf_report_branch_samples touch && + perf_report_instruction_samples touch + + err=$? + + # Exit when find failure + [ $err != 0 ] && exit $err + + rm -f ${perfdata} + rm -f ${file} + fi + + arm_cs_iterate_devices $dev $2 + done +} + +arm_cs_etm_traverse_path_test() { + # Iterate for every ETM device + for dev in /sys/bus/coresight/devices/etm*; do + + # Find the ETM device belonging to which CPU + cpu=`cat $dev/cpu` + + echo $dev + echo $cpu + + # Use depth-first search (DFS) to iterate outputs + arm_cs_iterate_devices $dev $cpu + done +} + +arm_cs_etm_cpu_wide_test() { + echo "Recording trace with CPU wide mode" + perf record -o ${perfdata} -e cs_etm// -a -- ls + + perf_script_branch_samples perf && + perf_report_branch_samples perf && + perf_report_instruction_samples perf + + err=$? + + # Exit when find failure + [ $err != 0 ] && exit $err + + rm -f ${perfdata} + rm -f ${file} +} + +arm_cs_etm_snapshot_test() { + echo "Recording trace with snapshot mode" + perf record -o ${perfdata} -e cs_etm// -S --per-thread \ + -- dd if=/dev/zero of=/dev/null & + PERFPID=$! + + # Wait for perf program + sleep 1 + + # Send signal to snapshot trace data + kill -USR2 $PERFPID + + # Stop perf program + kill $PERFPID + wait $PERFPID + + perf_script_branch_samples dd && + perf_report_branch_samples dd && + perf_report_instruction_samples dd + + err=$? + + # Exit when find failure + [ $err != 0 ] && exit $err + + rm -f ${perfdata} + rm -f ${file} +} + +arm_cs_etm_traverse_path_test +arm_cs_etm_cpu_wide_test +arm_cs_etm_snapshot_test +exit 0 -- 2.17.1

4 years, 4 months

Issue with ETF sink under sysfs on Dragonboard DB410.

by Mike Leach

Hi, During some recent testing I happened to be using the ETF on the DB410 as a sink for a quick trace test. Running my usual script which does the following sequence via sysfs:- 1. enable sink. 2. enable source. 3. wait 4 .disable source 5. disable sink 6. read data from sink. At step 6, the board hung, threw an abort and rebooted:- root@linaro-developer:~# [ 128.556367] Internal error: synchronous external abort: 96000010 [#1] SMP Closer investigation shows this was occurring in tmc_etf_read_unprepare() in coresight-tmc-etf.c. A quick check though my archive of previous kernels, shows that a 5.6-rc3 build from 27/02/20 does not show the issue, a 5.6-rc6 build from 20/03/20 does show the problem. A look through the log for coresight-tmc-etf.c shows only one recent change to this file, a patch from Sai - commit 347adb0d6385, on 20/05/20 - to tmc_etf_read_prepare() - which is a couple of months after the issue first arises. Interestingly, if I replicate the change made in this commit, to tmc_etf_read_unprepare(), then the problem disappears. Obviously I can submit a patch to the 5.8-rc1 tree once that appears, assuming that this would not be simply masking a problem elsewhere. Thoughts? Anyone see similar issues? Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

4 years, 4 months

[PATCH 0/2] coresight: tmc: Add shutdown callback for TMC ETR/ETF

by Sai Prakash Ranjan

This series adds a shutdown callback to TMC ETR/ETF to ensure that it is properly shutdown in reboot/shutdown path. This is required for ETR/ETF which has SMMU address translation enabled like on SC7180 SoC and few others. If the hardware is still accessing memory after SMMU translation is disabled as part of SMMU shutdown callback in system reboot or shutdown path, then IOVAs(I/O virtual address) which it was using will go on the bus as the physical addresses which might result in unknown crashes (NoC/interconnect errors). So we make sure from this shutdown callback that the ETR/ETF is shutdown before SMMU translation is disabled and device_link in SMMU driver will take care of ordering of shutdown callbacks such that SMMU shutdown callback is not called before any of its consumer shutdown callbacks. Sai Prakash Ranjan (2): coresight: tmc: Add enable flag to indicate the status of ETR/ETF coresight: tmc: Add shutdown callback for TMC ETR/ETF .../hwtracing/coresight/coresight-tmc-etf.c | 4 +-- .../hwtracing/coresight/coresight-tmc-etr.c | 2 +- drivers/hwtracing/coresight/coresight-tmc.c | 31 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 5 +++ 4 files changed, 39 insertions(+), 3 deletions(-) base-commit: 059e38815950dbec65beafe03757bce9436e89a4 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

4 years, 4 months

[PATCH 0/2] arm64: dts: qcom: sc7180: Add support for ETMv4 PM and skipping power up.

by Sai Prakash Ranjan

Patch 1 is a resend of https://lore.kernel.org/patchwork/patch/1230367/ since that patch seems to have added the property to replicator node instead of etm7 node either when the patch was applied to the tree. Patch 2 adds support to skip powering up of ETM to workaround the hardware errata where CPU watchdog counter is stopped when power up bit is set. Depends on https://lore.kernel.org/patchwork/cover/1242100/ changes. Sai Prakash Ranjan (2): arm64: dts: qcom: sc7180: Support ETMv4 power management arm64: dts: qcom: sc7180: Add support to skip powering up of ETM arch/arm64/boot/dts/qcom/sc7180.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

4 years, 4 months

[PATCH v4 0/1] perf: cs_etm: Allow no sink on command line.

by Mike Leach

Currently starting CoreSight tracing using perf requires a sink selection on the command line:- sudo ./perf record -e cs_etm/@tmc_etr0/ --per-thread uname -a Not providing the @<sink> here results in an error and no trace produced. After this set (alongside the CoreSight change set [1]) the infrastructure will be able to select a default sink:- sudo ./perf record -e cs_etm// --per-thread uname -a This matches with the default operation provided with perf and intelpt. This patch removes the check that a sink value is provided on the command line with a NULL value passed to the CoreSight infrastructure if omitted. Note: If this set is applied to a system without [1], then the effect is benign as the existing CoreSight infrastructure will detect the error and refuse to trace. Applies to Linux coresight/next branch [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2020-May/734854.html Changes since v3: 1) Removed RFC designation and distributed to wider audience. 2) Split set into perf user runtime (this set), and CoreSight driver code. Mike Leach (1): perf: cs-etm: Allow no CoreSight sink to be specified on command line tools/perf/arch/arm/util/cs-etm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.17.1

4 years, 4 months

[PATCH v4 0/5] Update CoreSight infrastructure to select a default sink.

by Mike Leach

This patchset provides a proposed infrastructure to allow for the automatic selection of a sink during CoreSight tracing operations. Currently starting tracing using perf requires a sink selection on the command line:- sudo ./perf record -e cs_etm/@tmc_etr0/ --per-thread uname -a After this set (and the follow-up perf change set) the infrastructure will be able to select a default sink:- sudo ./perf record -e cs_etm// --per-thread uname -a This matches with the default operation provided with perf and intelpt. Where no sink is specified at the start of a trace session, the CoreSight system will walk the connection graph from the source ETM, to find a suitable sink using the first encountered highest priority device. The CoreSight infrastructure is updated to define sink sub_types to differentiate between sinks with built in buffers (ETB / ETF) - BUFFER type, and those that use system memory (ETR) - SYSMEM - types. SYSMEM types are considered higher priority. When two sinks are found of equal priority, then the closest sink to the source in terms of connection nodes is chosen. The automatic sink selection will also operate if an ETM is enabled using sysfs commands, and no sink is currently enabled. Applies to Linux coresight/next branch Changes since v3: 1) Removed RFC designation and distributed to wider audience. 2) Split set into CoreSight driver code (this set), and perf user runtime set. 3) Minor cosmetic changes. Mike Leach (5): coresight: Fix comment in main header file. coresight: Add default sink selection to CoreSight base coresight: tmc: Update sink types for default selection. coresight: etm: perf: Add default sink selection to etm perf coresight: sysfs: Allow select default sink on source enable. .../hwtracing/coresight/coresight-etm-perf.c | 17 +- drivers/hwtracing/coresight/coresight-priv.h | 2 + drivers/hwtracing/coresight/coresight-tmc.c | 3 +- drivers/hwtracing/coresight/coresight.c | 147 +++++++++++++++++- include/linux/coresight.h | 6 +- 5 files changed, 168 insertions(+), 7 deletions(-) -- 2.17.1

4 years, 4 months

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[PATCH] Fix corrupt data after perf inject from

by Al Grant

(Hi - posted for review. There was a recent ABI breaking change (see commit reference below), after which perf inject on ETM creates corrupt files. The simple fix ends up with it using the new ABI. I have an alternative patch set that emulates the old ABI - for the benefit of tools like autofdo that can't yet consume the new ABI - but it's much messier.) From: Al Grant <al.grant(a)arm.com> Commit 42bbabed09ce6208026648a71a45b4394c74585a ("perf tools: Add hw_idx in struct branch_stack") changed the format of branch stacks in perf samples. When samples use this new format, a flag must be set in the corresponding event. Synthesized branch stacks generated from CoreSight ETM trace were using the new format, but not setting the event attribute, leading to consumers seeing corrupt data. This patch fixes the issue by setting the event attribute to indicate use of the new format. Fixes: 42bbabed09ce ("perf tools: Add hw_idx in struct branch_stack") Signed-off-by: Al Grant <al.grant(a)arm.com> Acked-by: Andrea Brunato <andrea.brunato(a)arm.com> diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 62d2f9b9ce1b..71a056e29675 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1332,7 +1332,13 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, } if (etm->synth_opts.last_branch) + { attr.sample_type |= PERF_SAMPLE_BRANCH_STACK; + /* We don't use the hardware index, but the sample generation + code uses the new format branch_stack with this field, + so the event attributes must indicate that it's present. */ + attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX; + } if (etm->synth_opts.instructions) { attr.config = PERF_COUNT_HW_INSTRUCTIONS; IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 4 months

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CoreSight June 2020