CoreSight June 2022

coresight@lists.linaro.org

10 participants
21 discussions

Re: [PATCH] coresight: etm4x: add CPU hotplug support for probing

by Suzuki K Poulose

Hi Tamas Thanks for the patch. I have tested this on my Juno board and it works fine. I have some comments inline. On 16/06/2022 16:18, Tamas Zsoldos wrote: > etm4x devices cannot be successfully probed when their CPU is offline. > This adds a mechanism to delay the probing in this case and try again > once the CPU is brought online. It may be worth elaborating this a bit. e.g, "For e.g., if the system is booted with maxcpus=n, the ETM won't be probed on CPUs n+1, even when the CPUs are brought up online later" , > > Signed-off-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> > --- > .../coresight/coresight-etm4x-core.c | 195 ++++++++++++++---- > 1 file changed, 155 insertions(+), 40 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 7f416a12000e..f0bff08e9de9 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -70,6 +70,14 @@ struct etm4_init_arg { > struct csdev_access *csa; > }; > > +struct etm4_delayed_probe { > + u32 etm_pid; > + struct device *dev; > +}; > + > +static DEFINE_PER_CPU(struct etm4_delayed_probe *, delayed_probe); > +static enum cpuhp_state hp_probe; I am wondering if we can reuse the existing hotplug notifier ? See more on this below. > + > /* > * Check if TRCSSPCICRn(i) is implemented for a given instance. > * > @@ -1938,48 +1946,20 @@ static void etm4_pm_clear(void) > } > } > > -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > +static int etm4_add_coresight_dev(struct device *dev, > + struct csdev_access *access) Could this be : etm4_add_coresight_dev(struct etm4_init_arg *init_arg) That provides us with "access". Also if replace init_arg.drvdata field with init_arg.dev we can use that for etm4_init_arch_data() and etm4_add_coresight_dev. we can get to drvdata from the dev via, dev_get_drvdata(dev). > { > int ret; > struct coresight_platform_data *pdata = NULL; > - struct etmv4_drvdata *drvdata; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); > struct coresight_desc desc = { 0 }; > - struct etm4_init_arg init_arg = { 0 }; > u8 major, minor; > char *type_name; > > - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > - return -ENOMEM; > - > - dev_set_drvdata(dev, drvdata); > - > - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) > - pm_save_enable = coresight_loses_context_with_cpu(dev) ? > - PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; > - > - if (pm_save_enable != PARAM_PM_SAVE_NEVER) { > - drvdata->save_state = devm_kmalloc(dev, > - sizeof(struct etmv4_save_state), GFP_KERNEL); > - if (!drvdata->save_state) > - return -ENOMEM; > - } > - > - drvdata->base = base; > - > - spin_lock_init(&drvdata->spinlock); > - > - drvdata->cpu = coresight_get_cpu(dev); > - if (drvdata->cpu < 0) > - return drvdata->cpu; > - > - init_arg.drvdata = drvdata; > - init_arg.csa = &desc.access; > - init_arg.pid = etm_pid; > + return -EINVAL; > > - if (smp_call_function_single(drvdata->cpu, > - etm4_init_arch_data, &init_arg, 1)) > - dev_err(dev, "ETM arch init failed\n"); > + desc.access = *access; > > if (!drvdata->arch) > return -EINVAL; > @@ -2050,6 +2030,69 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > return 0; > } > > +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > +{ > + struct etmv4_drvdata *drvdata; > + struct csdev_access access = { 0 }; > + struct etm4_init_arg init_arg = { 0 }; > + struct etm4_delayed_probe *delayed; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + dev_set_drvdata(dev, drvdata); > + > + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) > + pm_save_enable = coresight_loses_context_with_cpu(dev) ? > + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; > + > + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { > + drvdata->save_state = devm_kmalloc(dev, > + sizeof(struct etmv4_save_state), GFP_KERNEL); > + if (!drvdata->save_state) > + return -ENOMEM; > + } > + > + drvdata->base = base; > + > + spin_lock_init(&drvdata->spinlock); > + > + drvdata->cpu = coresight_get_cpu(dev); > + if (drvdata->cpu < 0) > + return drvdata->cpu; > + > + init_arg.drvdata = drvdata; > + init_arg.csa = &access; > + init_arg.pid = etm_pid; > + > + /* > + * Serialize against CPUHP callbacks to avoid race condition > + * between the smp call and saving the delayed probe. > + */ > + cpus_read_lock(); > + if (smp_call_function_single(drvdata->cpu, > + etm4_init_arch_data, &init_arg, 1)) { > + /* The CPU was offline, try again once it comes online. */ > + delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); > + if (!delayed) { > + cpus_read_unlock(); > + return -ENOMEM; > + } > + > + delayed->etm_pid = etm_pid; > + delayed->dev = dev; > + > + per_cpu(delayed_probe, drvdata->cpu) = delayed; > + > + cpus_read_unlock(); > + return 0; > + } > + cpus_read_unlock(); > + > + return etm4_add_coresight_dev(dev, &access); > +} > + > static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) > { > void __iomem *base; > @@ -2088,6 +2131,64 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) > return ret; > } > > +static int etm4_probe_cpu(unsigned int cpu) > +{ > + int ret; > + struct etm4_delayed_probe di; > + struct csdev_access access = { 0 }; > + struct etm4_init_arg init_arg; > + struct etm4_delayed_probe *dp = *this_cpu_ptr(&delayed_probe); This could be called from the existing etm4_starting_cpu() ? static int etm4_starting_cpu(unsigned int cpu) { if (!etmdrvdata[cpu]) - return 0; + return etm4_probe_cpu(cpu); spin_lock(&etmdrvdata[cpu]->spinlock); if (!etmdrvdata[cpu]->os_unlock) etm4_os_unlock(etmdrvdata[cpu]); if (local_read(&etmdrvdata[cpu]->mode)) etm4_enable_hw(etmdrvdata[cpu]); spin_unlock(&etmdrvdata[cpu]->spinlock); } > + > + if (!dp) > + return 0; > + > + di = *dp; > + devm_kfree(di.dev, dp); > + *this_cpu_ptr(&delayed_probe) = NULL; > + > + ret = pm_runtime_resume_and_get(di.dev); > + if (ret < 0) { > + dev_err(di.dev, "Failed to get PM runtime!\n"); > + return 0; > + } > + > + init_arg.drvdata = dev_get_drvdata(di.dev); > + if (!init_arg.drvdata) > + return 0; > + > + init_arg.csa = &access; > + init_arg.pid = di.etm_pid; > + etm4_init_arch_data(&init_arg); > + > + etm4_add_coresight_dev(di.dev, &access); > + > + pm_runtime_put(di.dev); > + return 0; > +} > + > +static int etm4_setup_cpuhp_probe(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, > + "arm/coresight4:delayed_probe", > + etm4_probe_cpu, NULL); > + > + if (ret > 0) { > + hp_probe = ret; > + return 0; > + } > + return ret; > +} > + > +static void etm4_remove_cpuhp_probe(void) > +{ > + if (hp_probe) > + cpuhp_remove_state_nocalls(hp_probe); > + > + hp_probe = 0; > +} > + And we could get rid of the above ^^ > static struct amba_cs_uci_id uci_id_etm4[] = { > { > /* ETMv4 UCI data */ > @@ -2102,16 +2203,20 @@ static void clear_etmdrvdata(void *info) > int cpu = *(int *)info; > > etmdrvdata[cpu] = NULL; > + per_cpu(delayed_probe, cpu) = NULL; > } > > static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) > { > - etm_perf_symlink(drvdata->csdev, false); > + bool had_dev; > /* > * Taking hotplug lock here to avoid racing between etm4_remove_dev() > * and CPU hotplug call backs. > */ > cpus_read_lock(); > + > + had_dev = etmdrvdata[drvdata->cpu]; > + Is this ever false ? Why do we need this change ? How does this patch affect the tear down ? Suzuki

2 years, 3 months

[PATCH v11 0/9] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series "coresight: Add new API to allocate trace source ID values". https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220308205000.… Changes from V10: 1. Change dev_info to dev_dbg in TPDM/TPDA drivers. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 2. Merge sysfs API change of integration_test to integration_test driver change. -- -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Mao Jinlong (9): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add coresight components arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 111 +++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++ MAINTAINERS | 2 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 671 ++++++++++++++++++ drivers/hwtracing/coresight/Kconfig | 23 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 +- drivers/hwtracing/coresight/coresight-tpda.c | 206 ++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 + drivers/hwtracing/coresight/coresight-tpdm.c | 259 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 ++ include/linux/coresight.h | 1 + 13 files changed, 1508 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

2 years, 4 months

Re: [PATCH next] Documentation: coresight: escape coresight bindings file wildcard

by Mathieu Poirier

On Thu, Jun 30, 2022 at 05:13:17PM +0700, Bagas Sanjaya wrote: > Stephen Rothwell reported htmldocs warning: > > Documentation/trace/coresight/coresight.rst:133: WARNING: Inline emphasis start-string without end-string. > > The warning above is due to unescaped wildcard asterisk (*) on CoreSight > devicetree binding filename, which confuses Sphinx as emphasis instead. > > Escape the wildcard to fix the warning. > > Link: https://lore.kernel.org/linux-next/20220630173801.41bf22a2@canb.auug.org.au/ > Fixes: 3c15fddf312120 ("dt-bindings: arm: Convert CoreSight bindings to DT schema") > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Leo Yan <leo.yan(a)linaro.org> > Cc: Jonathan Corbet <corbet(a)lwn.net> > Cc: Rob Herring <robh(a)kernel.org> > Cc: coresight(a)lists.linaro.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-next(a)vger.kernel.org > Cc: linux-kernel(a)vger.kernel.org > Reported-by: Stephen Rothwell <sfr(a)canb.auug.org.au> > Signed-off-by: Bagas Sanjaya <bagasdotme(a)gmail.com> > --- > Documentation/trace/coresight/coresight.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Applied. Thanks, Mathieu > diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst > index 529b7c80e6f353..1644a0244ad10a 100644 > --- a/Documentation/trace/coresight/coresight.rst > +++ b/Documentation/trace/coresight/coresight.rst > @@ -130,7 +130,7 @@ Misc: > Device Tree Bindings > -------------------- > > -See Documentation/devicetree/bindings/arm/arm,coresight-*.yaml for details. > +See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details. > > As of this writing drivers for ITM, STMs and CTIs are not provided but are > expected to be added as the solution matures. > > base-commit: 6cc11d2a1759275b856e464265823d94aabd5eaf > -- > An old man doll... just what I always wanted! - Clara >

2 years, 4 months

[PATCH v5 0/2] Fix lockdep issues seen in CoreSight configfs interface

by Mike Leach

Issues with lockdep possible deadlock scenarios have been reported when using the coresight configfs interface handling complex configuration, when unloading modules. These are due to holding the main configuration mutex during configfs register, but taking it later when accessing configfs files. The patches improve the clean up of configurations and update load and unload of configurations and initialisation of configfs to fix the locking mechanisms. Applies to coresight/next (5.19-rc2) Tested on DB410c (with patch [0] also applied to fix separate console boot issue). Fixes: eb2ec49606c2 ("coresight: syscfg: Update load API for config loadable modules") Reported-by: Suzuki Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> [0] https://lkml.kernel.org/r/20220614124618.2830569-1-suzuki.poulose@arm.com Changes since v4: No functional change - fixed comment in patch header 1/2 and error string format to remove checkpatch warning as requested by Mathieu. Changes since v3: Addressed minor issues raised by Suzuki. Changes since v2: Added additional work to fix load and unload ops after issue recurred due to file access. Mike Leach (2): coresight: configfs: Fix unload of configurations on module exit coresight: syscfg: Update load and unload operations .../hwtracing/coresight/coresight-config.h | 2 + .../hwtracing/coresight/coresight-syscfg.c | 298 +++++++++++++++--- .../hwtracing/coresight/coresight-syscfg.h | 13 + 3 files changed, 261 insertions(+), 52 deletions(-) -- 2.17.1

2 years, 4 months

Problems with On-Device Trace Capturing

by finn.burmester＠student.uni-luebeck.de

Hi, sorry for bothering you but I hope this is the right place for my questions, as I am kind of stuck right now. I am an undergrad student and currently experimenting with on-device Coresight Tracing. As a board I use the STM32MP157A-DK1, which has some Coresight devices, especially ETM v3.5 for the two A7 cores (32 Bit) and an ETF as a sink. I’d like to use CSAL for trace capturing and OpenCSD for trace decoding, but I’m facing some issues that I don’t understand. For tracing I use the “tracedemo” application from CSAL. As I want to trace userspace-code, I removed the kernel dump part from cs_util_create_snapshot. Except from this, I left everything unchanged, although I have already played around with some configurations. To avoid problems that may be caused by cpuidle, I pass the kernel parameter nohlt on boot, as suggested here in another thread. I also disabled ASLR. For the board configuration I added this function ```c static int do_registration_stm32(struct cs_devices_t *devices) { enum { A7_0, A7_1 }; cs_device_t funnel, etf, cti, etm, timestamp_gen, tpiu, cscti; //register the rom tables cs_register_romtable(0x50080000); cs_register_romtable(0x50090000); //CPU affinities /* ETM */ cs_device_set_affinity(cs_device_register(0x500DC000), A7_0); cs_device_set_affinity(cs_device_register(0x500DD000), A7_1); /* CTIs */ cs_device_set_affinity(cs_device_register(0x500D8000), A7_0); cs_device_set_affinity(cs_device_register(0x500D9000), A7_1); //register other devices timestamp_gen = cs_device_register(0x50082000); // funnels funnel = cs_device_get(0x50091000); cs_atb_register(cs_cpu_get_device(A7_0, CS_DEVCLASS_SOURCE), 0, funnel, 0); cs_atb_register(cs_cpu_get_device(A7_1, CS_DEVCLASS_SOURCE), 0, funnel, 1); //get the TPIU tpiu = cs_device_get(0x50093000); //get the ETF devices->etb = cs_device_get(0x50092000); /* It's ETF, not ETB actually */ cs_atb_register(funnel, 0, devices->etb, 0); cs_atb_register(devices->etb, 0, tpiu, 0); cscti = cs_device_register(0x50094000); /* the linux board probe does not set up CPUIDs correctly for stm32 - hardcode here for both linux and BAREMETAL. */ devices->cpu_id[0] = 0xC07; devices->cpu_id[1] = 0xC07; return 0; } ``` My Test-target application is as simple as this: ```c int main() { int a[20]; for (int i=0; i<10;i++) { a[i] = 1+i; } for (int i=0; i<13;i++) { a[i] = i; } return 0; } ``` The objdump of my target program looks like this: ```c 000103a0 <main>: 103a0: b480 push {r7} 103a2: b097 sub sp, #92 ; 0x5c 103a4: af00 add r7, sp, #0 103a6: 2300 movs r3, #0 103a8: 657b str r3, [r7, #84] ; 0x54 103aa: e00b b.n 103c4 <main+0x24> 103ac: 6d7b ldr r3, [r7, #84] ; 0x54 103ae: 1c5a adds r2, r3, #1 103b0: 6d7b ldr r3, [r7, #84] ; 0x54 103b2: 009b lsls r3, r3, #2 103b4: f107 0158 add.w r1, r7, #88 ; 0x58 103b8: 440b add r3, r1 103ba: f843 2c58 str.w r2, [r3, #-88] 103be: 6d7b ldr r3, [r7, #84] ; 0x54 103c0: 3301 adds r3, #1 103c2: 657b str r3, [r7, #84] ; 0x54 103c4: 6d7b ldr r3, [r7, #84] ; 0x54 103c6: 2b09 cmp r3, #9 103c8: ddf0 ble.n 103ac <main+0xc> 103ca: 2300 movs r3, #0 103cc: 653b str r3, [r7, #80] ; 0x50 103ce: e00a b.n 103e6 <main+0x46> 103d0: 6d3b ldr r3, [r7, #80] ; 0x50 103d2: 009b lsls r3, r3, #2 103d4: f107 0258 add.w r2, r7, #88 ; 0x58 103d8: 4413 add r3, r2 103da: 6d3a ldr r2, [r7, #80] ; 0x50 103dc: f843 2c58 str.w r2, [r3, #-88] 103e0: 6d3b ldr r3, [r7, #80] ; 0x50 103e2: 3301 adds r3, #1 103e4: 653b str r3, [r7, #80] ; 0x50 103e6: 6d3b ldr r3, [r7, #80] ; 0x50 103e8: 2b0c cmp r3, #12 103ea: ddf1 ble.n 103d0 <main+0x30> 103ec: 2300 movs r3, #0 103ee: 4618 mov r0, r3 103f0: 375c adds r7, #92 ; 0x5c 103f2: 46bd mov sp, r7 103f4: f85d 7b04 ldr.w r7, [sp], #4 103f8: 4770 bx lr ``` I start the trace capture with the command ./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name STM32 so that I only trace my main function. Then I start my target program and after this I stop the tracing. I try to look at the raw trace with OpenCSD, but I only get the following output: ```c $ ~/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister: CS Decode library testing ----------------------------------------------- ** Library Version : 1.3.1 Test Command Line:- /home/finn/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 bc bc bc b8 bc bc b8 bc Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 16; ID_DATA[0x10]; bc d4 bc bc bc bc bc bc bc bc bc bc ec 94 Idx:16; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 32; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 48 bytes. ``` So the trace stream seems to be not synchronized, but I have no idea why. I played around with the sync frequency, and set it to something low like 8. ```c cs_device_write(dev, CS_ETMSYNCFR, 8); ``` Then I get some readable trace, but of course the overhead is absurd. Also the trace only starts from 0x000103a8, while I would expect the first packet to be an i-sync for 0x000103a0, as this is the first address of my filter condition. ```c Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 00 00 00 00 00 80 90 08 Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Idx:6; ID:10; A_SYNC : Alignment Synchronisation. Idx:12; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 16; ID_DATA[0x10]; 09 a9 03 01 00 00 00 00 00 00 80 88 08 09 c5 Idx:13; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103a8; NS; ISA=Thumb2; Idx:21; ID:10; A_SYNC : Alignment Synchronisation. Idx:27; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 32; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 ad 03 01 Idx:28; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:35; ID:10; A_SYNC : Alignment Synchronisation. Idx:41; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 48; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 b3 03 01 00 00 Idx:42; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:49; ID:10; A_SYNC : Alignment Synchronisation. Idx:55; ID:10; P_HDR : Atom P-header.; EEE Idx:56; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 64; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 bb 03 01 00 00 00 00 Idx:62; ID:10; A_SYNC : Alignment Synchronisation. Idx:69; ID:10; P_HDR : Atom P-header.; EEE Idx:70; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 80; ID_DATA[0x10]; 00 00 80 8c 08 09 c3 03 01 00 00 00 00 00 00 Idx:76; ID:10; A_SYNC : Alignment Synchronisation. Idx:83; ID:10; P_HDR : Atom P-header.; EEE Idx:84; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 96; ID_DATA[0x10]; 80 88 08 09 c7 03 01 00 00 00 00 00 00 80 88 Idx:90; ID:10; A_SYNC : Alignment Synchronisation. Idx:97; ID:10; P_HDR : Atom P-header.; EE Idx:98; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:104; ID:10; A_SYNC : Alignment Synchronisation. Idx:110; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 112; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:112; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:118; ID:10; A_SYNC : Alignment Synchronisation. Idx:124; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 128; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb Idx:125; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:132; ID:10; A_SYNC : Alignment Synchronisation. Idx:138; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 144; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 Idx:139; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:147; ID:10; A_SYNC : Alignment Synchronisation. Idx:153; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 160; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 Idx:154; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:161; ID:10; A_SYNC : Alignment Synchronisation. Idx:167; ID:10; P_HDR : Atom P-header.; EE Idx:168; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 176; ID_DATA[0x10]; 00 00 00 00 80 88 08 09 ad 03 01 00 00 00 00 Idx:174; ID:10; A_SYNC : Alignment Synchronisation. Idx:181; ID:10; P_HDR : Atom P-header.; EE Idx:182; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Frame Data; Index 192; ID_DATA[0x10]; 00 00 80 8c 08 09 b3 03 01 00 00 00 00 00 00 Idx:188; ID:10; A_SYNC : Alignment Synchronisation. Idx:195; ID:10; P_HDR : Atom P-header.; EEE Idx:196; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 208; ID_DATA[0x10]; 80 8c 08 09 bb 03 01 00 00 00 00 00 00 80 8c Idx:202; ID:10; A_SYNC : Alignment Synchronisation. Idx:209; ID:10; P_HDR : Atom P-header.; EEE Idx:210; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:216; ID:10; A_SYNC : Alignment Synchronisation. Idx:222; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 224; ID_DATA[0x10]; 08 09 c3 03 01 00 00 00 00 00 00 80 88 08 09 Idx:224; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:230; ID:10; A_SYNC : Alignment Synchronisation. Idx:236; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 240; ID_DATA[0x10]; c7 03 01 00 00 00 00 00 00 80 88 08 09 ad 03 Idx:237; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:244; ID:10; A_SYNC : Alignment Synchronisation. Idx:250; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 256; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 b3 03 01 Idx:251; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:258; ID:10; A_SYNC : Alignment Synchronisation. Idx:264; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 272; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 00 Idx:265; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:273; ID:10; A_SYNC : Alignment Synchronisation. Idx:279; ID:10; P_HDR : Atom P-header.; EEE Idx:280; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 288; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 00 Idx:286; ID:10; A_SYNC : Alignment Synchronisation. Idx:293; ID:10; P_HDR : Atom P-header.; EEE Idx:294; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 304; ID_DATA[0x10]; 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 00 Idx:300; ID:10; A_SYNC : Alignment Synchronisation. Idx:307; ID:10; P_HDR : Atom P-header.; EE Idx:308; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 320; ID_DATA[0x10]; 80 88 08 09 ad 03 01 00 00 00 00 00 00 80 8c Idx:314; ID:10; A_SYNC : Alignment Synchronisation. Idx:321; ID:10; P_HDR : Atom P-header.; EE Idx:322; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:328; ID:10; A_SYNC : Alignment Synchronisation. Idx:334; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 336; ID_DATA[0x10]; 08 09 b3 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:336; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:342; ID:10; A_SYNC : Alignment Synchronisation. Idx:348; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 352; ID_DATA[0x10]; bb 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 Idx:349; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:356; ID:10; A_SYNC : Alignment Synchronisation. Idx:362; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 368; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 Idx:363; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:370; ID:10; A_SYNC : Alignment Synchronisation. Idx:376; ID:10; P_HDR : Atom P-header.; EE Idx:377; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 384; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 b1 03 01 00 00 Idx:384; ID:10; A_SYNC : Alignment Synchronisation. Idx:390; ID:10; P_HDR : Atom P-header.; EEEE Idx:391; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 400; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 b9 03 01 00 00 00 00 Idx:397; ID:10; A_SYNC : Alignment Synchronisation. Idx:405; ID:10; P_HDR : Atom P-header.; EEE Idx:406; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 416; ID_DATA[0x10]; 00 00 80 88 08 09 bf 03 01 00 00 00 00 00 00 Idx:412; ID:10; A_SYNC : Alignment Synchronisation. Idx:419; ID:10; P_HDR : Atom P-header.; EE Idx:420; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Frame Data; Index 432; ID_DATA[0x10]; 80 8c 08 09 c5 03 01 00 00 00 00 00 00 80 8c Idx:426; ID:10; A_SYNC : Alignment Synchronisation. Idx:433; ID:10; P_HDR : Atom P-header.; EEE Idx:434; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:440; ID:10; A_SYNC : Alignment Synchronisation. Idx:446; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 448; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:448; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:454; ID:10; A_SYNC : Alignment Synchronisation. Idx:460; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 464; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb 03 Idx:461; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:468; ID:10; A_SYNC : Alignment Synchronisation. Idx:474; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 480; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 00 Idx:475; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:482; ID:10; A_SYNC : Alignment Synchronisation. Idx:488; ID:10; P_HDR : Atom P-header.; EEE Idx:489; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 496; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 00 Idx:496; ID:10; A_SYNC : Alignment Synchronisation. Idx:502; ID:10; P_HDR : Atom P-header.; EE Idx:503; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 512; ID_DATA[0x10]; 00 00 00 80 90 08 09 b1 03 01 00 00 00 00 Idx:509; ID:10; A_SYNC : Alignment Synchronisation. Idx:516; ID:10; P_HDR : Atom P-header.; EEEE Idx:517; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 528; ID_DATA[0x10]; 00 00 80 8c 08 09 b9 03 01 00 00 00 00 00 00 Idx:523; ID:10; A_SYNC : Alignment Synchronisation. Idx:531; ID:10; P_HDR : Atom P-header.; EEE Idx:532; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 544; ID_DATA[0x10]; 80 88 08 09 bf 03 01 00 00 00 00 00 00 80 8c Idx:538; ID:10; A_SYNC : Alignment Synchronisation. Idx:545; ID:10; P_HDR : Atom P-header.; EE Idx:546; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:552; ID:10; A_SYNC : Alignment Synchronisation. Idx:558; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 560; ID_DATA[0x10]; 08 09 c5 03 01 00 00 00 00 00 00 80 90 08 09 Idx:560; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:566; ID:10; A_SYNC : Alignment Synchronisation. Idx:572; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 576; ID_DATA[0x10]; af 03 01 00 00 00 00 00 00 80 88 08 09 b3 03 Idx:573; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ae; NS; ISA=Thumb2; Idx:580; ID:10; A_SYNC : Alignment Synchronisation. Idx:586; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 592; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 Idx:587; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:594; ID:10; A_SYNC : Alignment Synchronisation. Idx:600; ID:10; P_HDR : Atom P-header.; EEE Idx:601; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 608; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 Idx:608; ID:10; A_SYNC : Alignment Synchronisation. Idx:614; ID:10; P_HDR : Atom P-header.; EEE Idx:615; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 624; ID_DATA[0x10]; 00 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 Idx:621; ID:10; A_SYNC : Alignment Synchronisation. Idx:628; ID:10; P_HDR : Atom P-header.; EE Idx:629; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 640; ID_DATA[0x10]; 00 80 90 08 09 b1 03 01 00 00 00 00 00 00 Idx:635; ID:10; A_SYNC : Alignment Synchronisation. Idx:642; ID:10; P_HDR : Atom P-header.; EEEE Idx:643; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 656; ID_DATA[0x10]; 80 8c 08 09 b9 03 01 00 00 00 00 00 00 80 88 Idx:649; ID:10; A_SYNC : Alignment Synchronisation. Idx:657; ID:10; P_HDR : Atom P-header.; EEE Idx:658; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Idx:664; ID:10; A_SYNC : Alignment Synchronisation. Idx:670; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 672; ID_DATA[0x10]; 08 09 bf 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:672; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:678; ID:10; A_SYNC : Alignment Synchronisation. Idx:684; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 688; ID_DATA[0x10]; c5 03 01 00 c8 00 00 00 00 00 80 08 09 cb 03 Idx:685; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:692; ID:10; P_HDR : Atom P-header.; EEN Idx:693; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 704; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e7 03 01 00 Idx:699; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ca; NS; ISA=Thumb2; Idx:706; ID:10; A_SYNC : Alignment Synchronisation. Idx:712; ID:10; P_HDR : Atom P-header.; EEE Idx:713; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e6; NS; ISA=Thumb2; Frame Data; Index 720; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 d1 03 01 00 00 00 Idx:720; ID:10; A_SYNC : Alignment Synchronisation. Idx:726; ID:10; P_HDR : Atom P-header.; EEE Idx:727; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 736; ID_DATA[0x10]; 00 00 00 80 88 08 09 d5 03 01 00 00 00 00 00 Idx:733; ID:10; A_SYNC : Alignment Synchronisation. Idx:740; ID:10; P_HDR : Atom P-header.; EE Idx:741; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 752; ID_DATA[0x10]; 00 80 8c 08 09 dd 03 01 00 00 00 00 00 00 80 Idx:747; ID:10; A_SYNC : Alignment Synchronisation. Idx:754; ID:10; P_HDR : Atom P-header.; EEE Idx:755; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:761; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 768; ID_DATA[0x10]; 8c 08 09 e5 03 01 00 00 00 00 00 00 80 88 Idx:768; ID:10; P_HDR : Atom P-header.; EEE Idx:769; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:775; ID:10; A_SYNC : Alignment Synchronisation. Idx:781; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 784; ID_DATA[0x10]; 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:784; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:790; ID:10; A_SYNC : Alignment Synchronisation. Idx:796; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 800; ID_DATA[0x10]; d3 03 01 00 00 00 00 00 00 80 90 08 09 dd 03 Idx:797; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:804; ID:10; A_SYNC : Alignment Synchronisation. Idx:810; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 816; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 00 Idx:811; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:818; ID:10; A_SYNC : Alignment Synchronisation. Idx:824; ID:10; P_HDR : Atom P-header.; EEE Idx:825; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 832; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 00 Idx:832; ID:10; A_SYNC : Alignment Synchronisation. Idx:838; ID:10; P_HDR : Atom P-header.; EE Idx:839; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 848; ID_DATA[0x10]; 00 00 00 80 88 08 09 d1 03 01 00 00 00 00 00 Idx:845; ID:10; A_SYNC : Alignment Synchronisation. Idx:852; ID:10; P_HDR : Atom P-header.; EE Idx:853; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 864; ID_DATA[0x10]; 00 80 88 08 09 d5 03 01 00 00 00 00 00 00 80 Idx:859; ID:10; A_SYNC : Alignment Synchronisation. Idx:866; ID:10; P_HDR : Atom P-header.; EE Idx:867; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:873; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 880; ID_DATA[0x10]; 8c 08 09 dd 03 01 00 00 00 00 00 00 80 8c 08 Idx:880; ID:10; P_HDR : Atom P-header.; EEE Idx:881; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:887; ID:10; A_SYNC : Alignment Synchronisation. Idx:893; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 896; ID_DATA[0x10]; 09 e5 03 01 00 00 00 00 00 00 80 88 08 09 e9 Idx:894; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:901; ID:10; A_SYNC : Alignment Synchronisation. Idx:907; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 912; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 d1 03 Idx:908; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:915; ID:10; A_SYNC : Alignment Synchronisation. Idx:921; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 928; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 d5 03 01 00 Idx:922; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:930; ID:10; A_SYNC : Alignment Synchronisation. Idx:936; ID:10; P_HDR : Atom P-header.; EE Idx:937; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 944; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 dd 03 01 00 00 00 Idx:944; ID:10; A_SYNC : Alignment Synchronisation. Idx:950; ID:10; P_HDR : Atom P-header.; EEE Idx:951; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 960; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:957; ID:10; A_SYNC : Alignment Synchronisation. Idx:964; ID:10; P_HDR : Atom P-header.; EEE Idx:965; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 976; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:971; ID:10; A_SYNC : Alignment Synchronisation. Idx:978; ID:10; P_HDR : Atom P-header.; EE Idx:979; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:985; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 992; ID_DATA[0x10]; 8c 08 09 d3 03 01 00 00 00 00 00 00 80 90 08 Idx:992; ID:10; P_HDR : Atom P-header.; EEE Idx:993; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:999; ID:10; A_SYNC : Alignment Synchronisation. Idx:1005; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1008; ID_DATA[0x10]; 09 dd 03 01 00 00 00 00 00 00 80 8c 08 09 e5 Idx:1006; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1013; ID:10; A_SYNC : Alignment Synchronisation. Idx:1019; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1024; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 e9 03 01 Idx:1020; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1027; ID:10; A_SYNC : Alignment Synchronisation. Idx:1033; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1040; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 d3 03 01 00 Idx:1034; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1041; ID:10; A_SYNC : Alignment Synchronisation. Idx:1047; ID:10; P_HDR : Atom P-header.; EEE Idx:1048; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1056; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 dd 03 01 00 00 00 Idx:1056; ID:10; A_SYNC : Alignment Synchronisation. Idx:1062; ID:10; P_HDR : Atom P-header.; EEEE Idx:1063; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1072; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:1069; ID:10; A_SYNC : Alignment Synchronisation. Idx:1076; ID:10; P_HDR : Atom P-header.; EEE Idx:1077; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 1088; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:1083; ID:10; A_SYNC : Alignment Synchronisation. Idx:1090; ID:10; P_HDR : Atom P-header.; EE Idx:1091; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1097; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1104; ID_DATA[0x10]; 88 08 09 d1 03 01 00 00 00 00 00 00 80 88 08 Idx:1104; ID:10; P_HDR : Atom P-header.; EE Idx:1105; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:1111; ID:10; A_SYNC : Alignment Synchronisation. Idx:1117; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1120; ID_DATA[0x10]; 09 d5 03 01 00 00 00 00 00 00 80 8c 08 09 dd Idx:1118; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:1125; ID:10; A_SYNC : Alignment Synchronisation. Idx:1131; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1136; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1132; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1139; ID:10; A_SYNC : Alignment Synchronisation. Idx:1145; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1152; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1146; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1153; ID:10; A_SYNC : Alignment Synchronisation. Idx:1159; ID:10; P_HDR : Atom P-header.; EE Idx:1160; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1168; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 Idx:1166; ID:10; A_SYNC : Alignment Synchronisation. Idx:1173; ID:10; P_HDR : Atom P-header.; EEE Idx:1174; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1184; ID_DATA[0x10]; 00 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1180; ID:10; A_SYNC : Alignment Synchronisation. Idx:1188; ID:10; P_HDR : Atom P-header.; EEEE Idx:1189; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1200; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1195; ID:10; A_SYNC : Alignment Synchronisation. Idx:1202; ID:10; P_HDR : Atom P-header.; EEE Idx:1203; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1209; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1216; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1216; ID:10; P_HDR : Atom P-header.; EE Idx:1217; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1223; ID:10; A_SYNC : Alignment Synchronisation. Idx:1229; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1232; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1230; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1237; ID:10; A_SYNC : Alignment Synchronisation. Idx:1243; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1248; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1244; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1251; ID:10; A_SYNC : Alignment Synchronisation. Idx:1257; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1264; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1258; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1265; ID:10; A_SYNC : Alignment Synchronisation. Idx:1271; ID:10; P_HDR : Atom P-header.; EE Idx:1272; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1280; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1278; ID:10; A_SYNC : Alignment Synchronisation. Idx:1285; ID:10; P_HDR : Atom P-header.; EEE Idx:1286; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1296; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1292; ID:10; A_SYNC : Alignment Synchronisation. Idx:1299; ID:10; P_HDR : Atom P-header.; EEEE Idx:1300; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1312; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1306; ID:10; A_SYNC : Alignment Synchronisation. Idx:1314; ID:10; P_HDR : Atom P-header.; EEE Idx:1315; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1321; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1328; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1328; ID:10; P_HDR : Atom P-header.; EE Idx:1329; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1335; ID:10; A_SYNC : Alignment Synchronisation. Idx:1341; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1344; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1342; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1349; ID:10; A_SYNC : Alignment Synchronisation. Idx:1355; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1360; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1356; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1363; ID:10; A_SYNC : Alignment Synchronisation. Idx:1369; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1376; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1370; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1377; ID:10; A_SYNC : Alignment Synchronisation. Idx:1383; ID:10; P_HDR : Atom P-header.; EE Idx:1384; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1392; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1390; ID:10; A_SYNC : Alignment Synchronisation. Idx:1397; ID:10; P_HDR : Atom P-header.; EEE Idx:1398; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1408; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 00 Idx:1404; ID:10; A_SYNC : Alignment Synchronisation. Idx:1411; ID:10; P_HDR : Atom P-header.; EEEE Idx:1412; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1424; ID_DATA[0x10]; 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1418; ID:10; A_SYNC : Alignment Synchronisation. Idx:1425; ID:10; P_HDR : Atom P-header.; EEE Idx:1426; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1432; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1440; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1440; ID:10; P_HDR : Atom P-header.; EE Idx:1441; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1447; ID:10; A_SYNC : Alignment Synchronisation. Idx:1453; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1456; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1454; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1461; ID:10; A_SYNC : Alignment Synchronisation. Idx:1467; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1472; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1468; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1475; ID:10; A_SYNC : Alignment Synchronisation. Idx:1481; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1488; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 c4 Idx:1482; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1489; ID:10; A_SYNC : Alignment Synchronisation. Idx:1495; ID:10; P_HDR : Atom P-header.; EE Idx:1496; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1502; ID:10; P_HDR : Atom P-header.; EN Frame Data; Index 1504; ID_DATA[0x10]; 00 00 00 00 00 80 08 09 ed 03 01 00 00 00 00 Idx:1504; ID:10; A_SYNC : Alignment Synchronisation. Idx:1510; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ec; NS; ISA=Thumb2; Frame Data; Index 1520; ID_DATA[0x10]; 00 00 80 90 08 09 f5 03 01 00 84 Idx:1516; ID:10; A_SYNC : Alignment Synchronisation. Idx:1523; ID:10; P_HDR : Atom P-header.; EEEE Idx:1524; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103f4; NS; ISA=Thumb2; Idx:1530; ID:10; P_HDR : Atom P-header.; E Frame Data; Index 1530; ID_DATA[0x00]; 00 00 00 Frame Data; Index 1536; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 1552 bytes. ``` As far as I understand the ETM should emit an i-sync packet when the address-range-filter triggers, so the first packet I should see in the trace should be that i-sync packet with the first address of my function. And then I would expect some atoms or other trace. It should be possible to accurately trace also small portions of code (starting from the instruction that triggers the enabling of the ETM), right? I would be very happy if you could tell me if I have understood or done something wrong and would be glad about any hints for successfully obtaining and reading traces on my device. Best regards, Finn

2 years, 4 months

[PATCH v4 0/2] Fix lockdep issues seen in CoreSight configfs interface

by Mike Leach

Issues with lockdep possible deadlock scenarios have been reported when using the coresight configfs interface handling complex configuration, when unloading modules. These are due to holding the main configuration mutex during configfs register, but taking it later when accessing configfs files. The patches improve the clean up of configurations and update load and unload of configurations and initialisation of configfs to fix the locking mechanisms. Applies to coresight/next (5.19-rc2) Tested on DB410c (with patch [0] also applied to fix separate console boot issue). Fixes: eb2ec49606c2 ("coresight: syscfg: Update load API for config loadable modules") Reported-by: Suzuki Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> [0] https://lkml.kernel.org/r/20220614124618.2830569-1-suzuki.poulose@arm.com Changes since v3: Addressed minor issues raised by Suzuki. Changes since v2: Added additional work to fix load and unload ops after issue recurred due to file access. Mike Leach (2): coresight: configfs: Fix unload of configurations on module exit coresight: syscfg: Update load and unload operations .../hwtracing/coresight/coresight-config.h | 2 + .../hwtracing/coresight/coresight-syscfg.c | 299 +++++++++++++++--- .../hwtracing/coresight/coresight-syscfg.h | 13 + 3 files changed, 262 insertions(+), 52 deletions(-) -- 2.17.1

2 years, 4 months

Re: [PATCH v5] coresight: etm4x: avoid build failure with unrolled loops

by Suzuki K Poulose

Hi Nick, Thanks for the rework. On 23/06/2022 18:41, Nick Desaulniers wrote: > When the following configs are enabled: > * CORESIGHT > * CORESIGHT_SOURCE_ETM4X > * UBSAN > * UBSAN_TRAP > > Clang fails assemble the kernel with the error: > <instantiation>:1:7: error: expected constant expression in '.inst' directive > .inst (0xd5200000|((((2) << 19) | ((1) << 16) | (((((((((((0x160 + (i * 4))))) >> 2))) >> 7) & 0x7)) << 12) | ((((((((((0x160 + (i * 4))))) >> 2))) & 0xf)) << 8) | (((((((((((0x160 + (i * 4))))) >> 2))) >> 4) & 0x7)) << 5)))|(.L__reg_num_x8)) > ^ > drivers/hwtracing/coresight/coresight-etm4x-core.c:702:4: note: while in > macro instantiation > etm4x_relaxed_read32(csa, TRCCNTVRn(i)); > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:403:4: note: expanded from > macro 'etm4x_relaxed_read32' > read_etm4x_sysreg_offset((offset), false))) > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:383:12: note: expanded > from macro 'read_etm4x_sysreg_offset' > __val = read_etm4x_sysreg_const_offset((offset)); \ > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:149:2: note: expanded from > macro 'read_etm4x_sysreg_const_offset' > READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:144:2: note: expanded from > macro 'READ_ETM4x_REG' > read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) > ^ > arch/arm64/include/asm/sysreg.h:1108:15: note: expanded from macro > 'read_sysreg_s' > asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ > ^ > arch/arm64/include/asm/sysreg.h:1074:2: note: expanded from macro '__mrs_s' > " mrs_s " v ", " __stringify(r) "\n" \ > ^ > > Consider the definitions of TRCSSCSRn and TRCCNTVRn: > drivers/hwtracing/coresight/coresight-etm4x.h:56 > #define TRCCNTVRn(n) (0x160 + (n * 4)) > drivers/hwtracing/coresight/coresight-etm4x.h:81 > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > > Where the macro parameter is expanded to i; a loop induction variable > from etm4_disable_hw. > > When any compiler can determine that loops may be unrolled, then the > __builtin_constant_p check in read_etm4x_sysreg_offset() defined in > drivers/hwtracing/coresight/coresight-etm4x.h may evaluate to true. This > can lead to the expression `(0x160 + (i * 4))` being passed to > read_etm4x_sysreg_const_offset. Via the trace above, this is passed > through READ_ETM4x_REG, read_sysreg_s, and finally to __mrs_s where it > is string-ified and used directly in inline asm. > > Regardless of which compiler or compiler options determine whether a > loop can or can't be unrolled, which determines whether > __builtin_constant_p evaluates to true when passed an expression using a > loop induction variable, it is NEVER safe to allow the preprocessor to > construct inline asm like: > asm volatile (".inst (0x160 + (i * 4))" : "=r"(__val)); > ^ expected constant expression > > Replace unsafe uses of calls to etm4x_relaxed_read32 with > csdev_access_relaxed_read32 when the parameter is an expression that > would be invalid inline asm so that it does not depend on the ability of > the compiler to optimize __builtin_constant_p of the expression to true. > Only when the second parameter of etm4x_relaxed_read32 expands to an > expression dependent on a loop induction variable do we need to fix > this. > > For such cases where the induction variable is used in an expression, > perform the following function call replacements: > * etm4x_relaxed_write32 -> csdev_access_relaxed_write32 > * etm4x_relaxed_write64 -> csdev_access_relaxed_write64 > * etm4x_relaxed_read32 -> csdev_access_relaxed_read32 > * etm4x_read32 -> csdev_access_read32 > * etm4x_read64 -> csdev_access_read64 > > This is not a bug in clang; it's a potentially unsafe use of the macro > arguments in read_etm4x_sysreg_offset dependent on __builtin_constant_p. > > Link: https://github.com/ClangBuiltLinux/linux/issues/1310 > Reported-by: Arnd Bergmann <arnd(a)kernel.org> > Suggested-by: Arnd Bergmann <arnd(a)kernel.org> > Suggested-by: Tao Zhang <quic_taozha(a)quicinc.com> > Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Signed-off-by: Nick Desaulniers <ndesaulniers(a)google.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 years, 4 months

Re: [PATCH v4] coresight: etm4x: avoid build failure with unrolled loops

by Suzuki K Poulose

Hi Nick Thanks for resending the patch. Unfortunately, this one still doesn't address my comments in the v3 [0]. On 14/06/2022 23:02, Nick Desaulniers wrote: > When the following configs are enabled: > * CORESIGHT > * CORESIGHT_SOURCE_ETM4X > * UBSAN > * UBSAN_TRAP > > Clang fails assemble the kernel with the error: > <instantiation>:1:7: error: expected constant expression in '.inst' directive > .inst (0xd5200000|((((2) << 19) | ((1) << 16) | (((((((((((0x160 + (i * 4))))) >> 2))) >> 7) & 0x7)) << 12) | ((((((((((0x160 + (i * 4))))) >> 2))) & 0xf)) << 8) | (((((((((((0x160 + (i * 4))))) >> 2))) >> 4) & 0x7)) << 5)))|(.L__reg_num_x8)) > ^ > drivers/hwtracing/coresight/coresight-etm4x-core.c:702:4: note: while in macro instantiation > etm4x_relaxed_read32(csa, TRCCNTVRn(i)); > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:403:4: note: expanded from macro 'etm4x_relaxed_read32' > read_etm4x_sysreg_offset((offset), false))) > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:383:12: note: expanded from macro 'read_etm4x_sysreg_offset' > __val = read_etm4x_sysreg_const_offset((offset)); \ > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:149:2: note: expanded from macro 'read_etm4x_sysreg_const_offset' > READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) > ^ > drivers/hwtracing/coresight/coresight-etm4x.h:144:2: note: expanded from macro 'READ_ETM4x_REG' > read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) > ^ > arch/arm64/include/asm/sysreg.h:1108:15: note: expanded from macro 'read_sysreg_s' > asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ > ^ > arch/arm64/include/asm/sysreg.h:1074:2: note: expanded from macro '__mrs_s' > " mrs_s " v ", " __stringify(r) "\n" \ > ^ > > Consider the definitions of TRCSSCSRn and TRCCNTVRn: > drivers/hwtracing/coresight/coresight-etm4x.h:56 > #define TRCCNTVRn(n) (0x160 + (n * 4)) > drivers/hwtracing/coresight/coresight-etm4x.h:81 > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > > Where the macro parameter is expanded to i; a loop induction variable > from etm4_disable_hw. > > When any compiler can determine that loops may be unrolled, then the > __builtin_constant_p check in read_etm4x_sysreg_offset() defined in > drivers/hwtracing/coresight/coresight-etm4x.h may evaluate to true. This > can lead to the expression `(0x160 + (i * 4))` being passed to > read_etm4x_sysreg_const_offset. Via the trace above, this is passed > through READ_ETM4x_REG, read_sysreg_s, and finally to __mrs_s where it > is string-ified and used directly in inline asm. > > Regardless of compiler or compiler options determine whether a loop can > or can't be unrolled, which determines whether __builtin_constant_p > evaluates to true when passed an expression using a loop induction > variable, it is NEVER safe to allow the preprocessor to construction > inline asm like: > asm volatile (".inst (0x160 + (i * 4))" : "=r"(__val)); > ^ expected constant expression > > Replace unsafe uses of calls to etm4x_relaxed_read32 with > csdev_access_read32 when the parameter is an expression that would be > invalid inline asm so that it does not depend on the ability of the > compiler to optimize __builtin_constant_p of the expression to true. > Only when the second parameter of etm4x_relaxed_read32 expands to an > expression dependent on a loop induction variable do we need to fix > this. > > This is not a bug in clang; it's a potentially unsafe use of the macro > arguments in read_etm4x_sysreg_offset dependent on __builtin_constant_p. > > Link: https://github.com/ClangBuiltLinux/linux/issues/1310 > Suggested-by: Arnd Bergmann <arnd(a)kernel.org> > Suggested-by: Tao Zhang <quic_taozha(a)quicinc.com> > Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Signed-off-by: Nick Desaulniers <ndesaulniers(a)google.com> > --- > V1 (Arnd): > https://lore.kernel.org/lkml/20210225094324.3542511-1-arnd@kernel.org/ > > V2 (Arnd): > https://lore.kernel.org/lkml/20210429145752.3218324-1-arnd@kernel.org/ > > V3 (Tao): > https://lore.kernel.org/lkml/1632652550-26048-1-git-send-email-quic_taozha@… Even with this patch applied, we have many more instances left to convert. Please could you update the patch to convert all of these ? $ grep "(i)" coresight-etm4x* | grep -v csdev_ coresight-etm4x-core.c: * Check if TRCSSPCICRn(i) is implemented for a given instance. coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); coresight-etm4x-core.c: state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); coresight-etm4x-core.c: state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); coresight-etm4x-core.c: state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); coresight-etm4x-core.c: state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); coresight-etm4x-core.c: state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); coresight-etm4x-core.c: state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); coresight-etm4x-core.c: state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); coresight-etm4x-core.c: state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); coresight-etm4x-core.c: state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); coresight-etm4x-core.c: state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); coresight-etm4x-core.c: state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); coresight-etm4x-core.c: state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); coresight-etm4x-core.c: etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); [0] https://lore.kernel.org/lkml/48162555-2a67-60bc-ea4b-8720e7b98a22@arm.com/ Kind regards Suzuki > > drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 87299e99dabb..7c6bd85e36d4 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -836,13 +836,13 @@ static void etm4_disable_hw(void *info) > /* read the status of the single shot comparators */ > for (i = 0; i < drvdata->nr_ss_cmp; i++) { > config->ss_status[i] = > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > + csdev_access_read32(csa, TRCSSCSRn(i)); > } > > /* read back the current counter values */ > for (i = 0; i < drvdata->nr_cntr; i++) { > config->cntr_val[i] = > - etm4x_relaxed_read32(csa, TRCCNTVRn(i)); > + csdev_access_read32(csa, TRCCNTVRn(i)); > } > > coresight_disclaim_device_unlocked(csdev); > @@ -1177,7 +1177,7 @@ static void etm4_init_arch_data(void *info) > drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); > for (i = 0; i < drvdata->nr_ss_cmp; i++) { > drvdata->config.ss_status[i] = > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > + csdev_access_read32(csa, TRCSSCSRn(i)); > } > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ > drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);

2 years, 4 months

[PATCH v3 0/2] Fix lockdep issues seen in CoreSight configfs interface

by Mike Leach

Issues with lockdep possible deadlock scenarios have been reported when using the coresight configfs interface handling complex configuration, when unloading modules. These are due to holding the main configuration mutex during configfs register, but taking it later when accessing configfs files. The patches improve the clean up of configurations and update load and unload of configurations and initialisation of configfs to fix the locking mechanisms. Applies to coresight/next (5.19-rc2) Tested on DB410c (with patch [0] also applied to fix separate console boot issue). Fixes: eb2ec49606c2 ("coresight: syscfg: Update load API for config loadable modules") Reported-by: Suzuki Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> [0] https://lkml.kernel.org/r/20220614124618.2830569-1-suzuki.poulose@arm.com Changes since v2: Added additional work to fix load and unload ops after issue recurred due to file access. Mike Leach (2): coresight: configfs: Fix unload of configurations on module exit coresight: syscfg: Update load and unload operations .../hwtracing/coresight/coresight-config.h | 2 + .../hwtracing/coresight/coresight-syscfg.c | 297 +++++++++++++++--- .../hwtracing/coresight/coresight-syscfg.h | 13 + 3 files changed, 263 insertions(+), 49 deletions(-) -- 2.17.1

2 years, 4 months

[PATCH] coresight: Clear the connection field properly

by Suzuki K Poulose

coresight devices track their connections (output connections) and hold a reference to the fwnode. When a device goes away, we walk through the devices on the coresight bus and make sure that the references are dropped. This happens both ways: a) For all output connections from the device, drop the reference to the target device via coresight_release_platform_data() b) Iterate over all the devices on the coresight bus and drop the reference to fwnode if *this* device is the target of the output connection, via coresight_remove_conns()->coresight_remove_match(). However, the coresight_remove_match() doesn't clear the fwnode field, after dropping the reference, this causes use-after-free and additional refcount drops on the fwnode. e.g., if we have two devices, A and B, with a connection, A -> B. If we remove B first, B would clear the reference on B, from A via coresight_remove_match(). But when A is removed, it still has a connection with fwnode still pointing to B. Thus it tries to drops the reference in coresight_release_platform_data(), raising the bells like : [ 91.990153] ------------[ cut here ]------------ [ 91.990163] refcount_t: addition on 0; use-after-free. [ 91.990212] WARNING: CPU: 0 PID: 461 at lib/refcount.c:25 refcount_warn_saturate+0xa0/0x144 [ 91.990260] Modules linked in: coresight_funnel coresight_replicator coresight_etm4x(-) crct10dif_ce coresight ip_tables x_tables ipv6 [last unloaded: coresight_cpu_debug] [ 91.990398] CPU: 0 PID: 461 Comm: rmmod Tainted: G W T 5.19.0-rc2+ #53 [ 91.990418] Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Feb 1 2019 [ 91.990434] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 91.990454] pc : refcount_warn_saturate+0xa0/0x144 [ 91.990476] lr : refcount_warn_saturate+0xa0/0x144 [ 91.990496] sp : ffff80000c843640 [ 91.990509] x29: ffff80000c843640 x28: ffff800009957c28 x27: ffff80000c8439a8 [ 91.990560] x26: ffff00097eff1990 x25: ffff8000092b6ad8 x24: ffff00097eff19a8 [ 91.990610] x23: ffff80000c8439a8 x22: 0000000000000000 x21: ffff80000c8439c2 [ 91.990659] x20: 0000000000000000 x19: ffff00097eff1a10 x18: ffff80000ab99c40 [ 91.990708] x17: 0000000000000000 x16: 0000000000000000 x15: ffff80000abf6fa0 [ 91.990756] x14: 000000000000001d x13: 0a2e656572662d72 x12: 657466612d657375 [ 91.990805] x11: 203b30206e6f206e x10: 6f69746964646120 x9 : ffff8000081aba28 [ 91.990854] x8 : 206e6f206e6f6974 x7 : 69646461203a745f x6 : 746e756f63666572 [ 91.990903] x5 : ffff00097648ec58 x4 : 0000000000000000 x3 : 0000000000000027 [ 91.990952] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff00080260ba00 [ 91.991000] Call trace: [ 91.991012] refcount_warn_saturate+0xa0/0x144 [ 91.991034] kobject_get+0xac/0xb0 [ 91.991055] of_node_get+0x2c/0x40 [ 91.991076] of_fwnode_get+0x40/0x60 [ 91.991094] fwnode_handle_get+0x3c/0x60 [ 91.991116] fwnode_get_nth_parent+0xf4/0x110 [ 91.991137] fwnode_full_name_string+0x48/0xc0 [ 91.991158] device_node_string+0x41c/0x530 [ 91.991178] pointer+0x320/0x3ec [ 91.991198] vsnprintf+0x23c/0x750 [ 91.991217] vprintk_store+0x104/0x4b0 [ 91.991238] vprintk_emit+0x8c/0x360 [ 91.991257] vprintk_default+0x44/0x50 [ 91.991276] vprintk+0xcc/0xf0 [ 91.991295] _printk+0x68/0x90 [ 91.991315] of_node_release+0x13c/0x14c [ 91.991334] kobject_put+0x98/0x114 [ 91.991354] of_node_put+0x24/0x34 [ 91.991372] of_fwnode_put+0x40/0x5c [ 91.991390] fwnode_handle_put+0x38/0x50 [ 91.991411] coresight_release_platform_data+0x74/0xb0 [coresight] [ 91.991472] coresight_unregister+0x64/0xcc [coresight] [ 91.991525] etm4_remove_dev+0x64/0x78 [coresight_etm4x] [ 91.991563] etm4_remove_amba+0x1c/0x2c [coresight_etm4x] [ 91.991598] amba_remove+0x3c/0x19c Reproducible by: (Build all coresight components as modules): #!/bin/sh while true do for m in tmc stm cpu_debug etm4x replicator funnel do modprobe coresight_${m} done for m in tmc stm cpu_debug etm4x replicator funnel do rmmode coresight_${m} done done Cc: stable(a)vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ee6ce92ab4c3..1edfec1e9d18 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1424,6 +1424,7 @@ static int coresight_remove_match(struct device *dev, void *data) * platform data. */ fwnode_handle_put(conn->child_fwnode); + conn->child_fwnode = NULL; /* No need to continue */ break; } -- 2.35.3

2 years, 4 months

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